1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * AMD Versal SysMon core driver 4 * 5 * Copyright (C) 2019 - 2022, Xilinx, Inc. 6 * Copyright (C) 2022 - 2026, Advanced Micro Devices, Inc. 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitfield.h> 11 #include <linux/bitops.h> 12 #include <linux/cleanup.h> 13 #include <linux/device.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/limits.h> 17 #include <linux/minmax.h> 18 #include <linux/module.h> 19 #include <linux/overflow.h> 20 #include <linux/property.h> 21 #include <linux/regmap.h> 22 #include <linux/string.h> 23 #include <linux/sysfs.h> 24 #include <linux/units.h> 25 26 #include <linux/iio/events.h> 27 #include <linux/iio/iio.h> 28 29 #include "versal-sysmon.h" 30 31 /* 32 * Oversampling ratio values exposed to userspace via IIO. 33 * Actual number of samples averaged: 1=none, 2=2x, 4=4x, 8=8x, 16=16x. 34 */ 35 static const int sysmon_oversampling_avail[] = { 1, 2, 4, 8, 16 }; 36 37 /* TEMP hysteresis mode bit in SYSMON_TEMP_EV_CFG */ 38 #define SYSMON_TEMP_HYST_MASK BIT(1) 39 40 /* Compute alarm register offset from a channel address */ 41 #define SYSMON_ALARM_OFFSET(addr) \ 42 (SYSMON_ALARM_REG + ((addr) / SYSMON_ALARM_BITS_PER_REG) * SYSMON_REG_STRIDE) 43 44 #define SYSMON_CHAN_TEMP(_chan, _address, _name) \ 45 { \ 46 .type = IIO_TEMP, \ 47 .indexed = 1, \ 48 .address = _address, \ 49 .channel = _chan, \ 50 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 51 .info_mask_shared_by_type = \ 52 BIT(IIO_CHAN_INFO_SCALE) | \ 53 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 54 .info_mask_shared_by_type_available = \ 55 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 56 .datasheet_name = _name, \ 57 } 58 59 enum sysmon_alarm_bit { 60 SYSMON_BIT_ALARM0 = 0, 61 SYSMON_BIT_ALARM1 = 1, 62 SYSMON_BIT_ALARM2 = 2, 63 SYSMON_BIT_ALARM3 = 3, 64 SYSMON_BIT_ALARM4 = 4, 65 SYSMON_BIT_TEMP = 9, 66 }; 67 68 /* Temperature event specification: rising threshold + hysteresis only */ 69 static const struct iio_event_spec sysmon_temp_events[] = { 70 { 71 .type = IIO_EV_TYPE_THRESH, 72 .dir = IIO_EV_DIR_RISING, 73 .mask_separate = BIT(IIO_EV_INFO_ENABLE) | 74 BIT(IIO_EV_INFO_VALUE) | 75 BIT(IIO_EV_INFO_HYSTERESIS), 76 }, 77 }; 78 79 /* Supply event specifications */ 80 static const struct iio_event_spec sysmon_supply_events[] = { 81 { 82 .type = IIO_EV_TYPE_THRESH, 83 .dir = IIO_EV_DIR_RISING, 84 .mask_separate = BIT(IIO_EV_INFO_VALUE), 85 }, 86 { 87 .type = IIO_EV_TYPE_THRESH, 88 .dir = IIO_EV_DIR_FALLING, 89 .mask_separate = BIT(IIO_EV_INFO_VALUE), 90 }, 91 { 92 .type = IIO_EV_TYPE_THRESH, 93 .dir = IIO_EV_DIR_EITHER, 94 .mask_separate = BIT(IIO_EV_INFO_ENABLE), 95 }, 96 }; 97 98 /* 99 * Static temperature channels (always present). 100 * 101 * These are hardware-computed aggregate registers across all active 102 * temperature satellites: 103 * temp: current max temperature across all active satellites 104 * min: current min temperature across all active satellites 105 * max_max: highest peak recorded since last hardware reset 106 * min_min: lowest trough recorded since last hardware reset 107 */ 108 static const struct iio_chan_spec temp_channels[] = { 109 SYSMON_CHAN_TEMP(0, SYSMON_TEMP_MAX, "temp"), 110 SYSMON_CHAN_TEMP(1, SYSMON_TEMP_MIN, "min"), 111 SYSMON_CHAN_TEMP(2, SYSMON_TEMP_MAX_MAX, "max_max"), 112 SYSMON_CHAN_TEMP(3, SYSMON_TEMP_MIN_MIN, "min_min"), 113 }; 114 115 static void sysmon_q8p7_to_millicelsius(s16 raw_data, int *val) 116 { 117 *val = (raw_data * MILLIDEGREE_PER_DEGREE) >> SYSMON_FRACTIONAL_SHIFT; 118 } 119 120 static void sysmon_millicelsius_to_q8p7(u32 *raw_data, int val) 121 { 122 *raw_data = (val << SYSMON_FRACTIONAL_SHIFT) / MILLIDEGREE_PER_DEGREE; 123 } 124 125 static void sysmon_supply_rawtoprocessed(int raw_data, int *val) 126 { 127 int mantissa, format, exponent; 128 129 mantissa = FIELD_GET(SYSMON_MANTISSA_MASK, raw_data); 130 exponent = SYSMON_SUPPLY_MANTISSA_BITS - FIELD_GET(SYSMON_MODE_MASK, raw_data); 131 format = FIELD_GET(SYSMON_FMT_MASK, raw_data); 132 /* 133 * When format bit is set the mantissa is two's complement 134 * (per hardware spec); sign-extend to int for correct arithmetic. 135 */ 136 if (format) 137 mantissa = sign_extend32(mantissa, 15); 138 139 *val = (mantissa * (int)MILLI) >> exponent; 140 } 141 142 static void sysmon_supply_processedtoraw(int val, u32 reg_val, u32 *raw_data) 143 { 144 int exponent = FIELD_GET(SYSMON_MODE_MASK, reg_val); 145 int format = FIELD_GET(SYSMON_FMT_MASK, reg_val); 146 int scale, tmp; 147 148 scale = BIT(SYSMON_SUPPLY_MANTISSA_BITS - exponent); 149 tmp = (val * scale) / (int)MILLI; 150 151 if (format) 152 tmp = clamp(tmp, S16_MIN, S16_MAX); 153 else 154 tmp = clamp(tmp, 0, U16_MAX); 155 156 *raw_data = (u16)tmp; 157 } 158 159 static int sysmon_supply_thresh_offset(unsigned long address, enum iio_event_direction dir) 160 { 161 if (dir == IIO_EV_DIR_RISING) 162 return (address * SYSMON_REG_STRIDE) + SYSMON_SUPPLY_TH_UP; 163 if (dir == IIO_EV_DIR_FALLING) 164 return (address * SYSMON_REG_STRIDE) + SYSMON_SUPPLY_TH_LOW; 165 166 return -EINVAL; 167 } 168 169 static int sysmon_read_raw(struct iio_dev *indio_dev, 170 struct iio_chan_spec const *chan, 171 int *val, int *val2, long mask) 172 { 173 struct sysmon *sysmon = iio_priv(indio_dev); 174 unsigned int regval; 175 int ret; 176 177 guard(mutex)(&sysmon->lock); 178 179 if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) { 180 *val = (chan->type == IIO_TEMP) ? sysmon->temp_oversampling : 181 sysmon->supply_oversampling; 182 return IIO_VAL_INT; 183 } 184 185 switch (chan->type) { 186 case IIO_TEMP: 187 if (mask == IIO_CHAN_INFO_SCALE) { 188 /* Q8.7 to millicelsius: raw * 1000 / 128 */ 189 *val = MILLIDEGREE_PER_DEGREE; 190 *val2 = BIT(SYSMON_FRACTIONAL_SHIFT); 191 return IIO_VAL_FRACTIONAL; 192 } 193 if (mask != IIO_CHAN_INFO_RAW) 194 return -EINVAL; 195 196 ret = regmap_read(sysmon->regmap, chan->address, ®val); 197 if (ret) 198 return ret; 199 200 *val = sign_extend32(regval, 15); 201 return IIO_VAL_INT; 202 203 case IIO_VOLTAGE: 204 if (mask != IIO_CHAN_INFO_PROCESSED) 205 return -EINVAL; 206 207 ret = regmap_read(sysmon->regmap, 208 chan->address * SYSMON_REG_STRIDE + 209 SYSMON_SUPPLY_BASE, ®val); 210 if (ret) 211 return ret; 212 213 sysmon_supply_rawtoprocessed(regval, val); 214 return IIO_VAL_INT; 215 216 default: 217 return -EINVAL; 218 } 219 } 220 221 static u32 sysmon_get_event_mask(const struct iio_chan_spec *chan) 222 { 223 if (chan->type == IIO_TEMP) 224 return BIT(SYSMON_BIT_TEMP); 225 226 return BIT(chan->address / SYSMON_ALARM_BITS_PER_REG); 227 } 228 229 static int sysmon_read_alarm_config(struct sysmon *sysmon, 230 unsigned long address) 231 { 232 u32 shift = address % SYSMON_ALARM_BITS_PER_REG; 233 u32 offset = SYSMON_ALARM_OFFSET(address); 234 235 return regmap_test_bits(sysmon->regmap, offset, BIT(shift)); 236 } 237 238 static int sysmon_write_alarm_config(struct sysmon *sysmon, 239 unsigned long address, bool enable) 240 { 241 u32 shift = address % SYSMON_ALARM_BITS_PER_REG; 242 u32 offset = SYSMON_ALARM_OFFSET(address); 243 244 return regmap_assign_bits(sysmon->regmap, offset, BIT(shift), enable); 245 } 246 247 static int sysmon_read_event_config(struct iio_dev *indio_dev, 248 const struct iio_chan_spec *chan, 249 enum iio_event_type type, 250 enum iio_event_direction dir) 251 { 252 struct sysmon *sysmon = iio_priv(indio_dev); 253 u32 mask = sysmon_get_event_mask(chan); 254 unsigned int imr; 255 int config_value; 256 int ret; 257 258 ret = regmap_read(sysmon->regmap, SYSMON_IMR, &imr); 259 if (ret) 260 return ret; 261 262 /* IMR bits are 1=masked, invert to get 1=enabled */ 263 imr = ~imr; 264 265 switch (chan->type) { 266 case IIO_VOLTAGE: 267 config_value = sysmon_read_alarm_config(sysmon, chan->address); 268 if (config_value < 0) 269 return config_value; 270 return config_value && (imr & mask); 271 272 case IIO_TEMP: 273 /* 274 * Return the administrative state, not the hardware IMR. 275 * The IRQ handler temporarily masks the interrupt during 276 * the polling window; reading IMR would show it as disabled. 277 * temp_mask bit is set when administratively disabled. 278 */ 279 return !(sysmon->temp_mask & mask); 280 281 default: 282 return -EINVAL; 283 } 284 } 285 286 static int sysmon_write_event_config(struct iio_dev *indio_dev, 287 const struct iio_chan_spec *chan, 288 enum iio_event_type type, 289 enum iio_event_direction dir, 290 bool state) 291 { 292 u32 offset = SYSMON_ALARM_OFFSET(chan->address); 293 struct sysmon *sysmon = iio_priv(indio_dev); 294 u32 mask = sysmon_get_event_mask(chan); 295 unsigned int alarm_config; 296 int ret; 297 298 guard(mutex)(&sysmon->lock); 299 300 switch (chan->type) { 301 case IIO_VOLTAGE: 302 ret = sysmon_write_alarm_config(sysmon, chan->address, state); 303 if (ret) 304 return ret; 305 306 ret = regmap_read(sysmon->regmap, offset, &alarm_config); 307 if (ret) 308 return ret; 309 310 if (alarm_config) 311 return regmap_write(sysmon->regmap, SYSMON_IER, mask); 312 313 return regmap_write(sysmon->regmap, SYSMON_IDR, mask); 314 315 case IIO_TEMP: 316 if (state) { 317 ret = regmap_write(sysmon->regmap, SYSMON_IER, mask); 318 if (ret) 319 return ret; 320 321 scoped_guard(spinlock_irq, &sysmon->irq_lock) 322 sysmon->temp_mask &= ~mask; 323 } else { 324 ret = regmap_write(sysmon->regmap, SYSMON_IDR, mask); 325 if (ret) 326 return ret; 327 328 scoped_guard(spinlock_irq, &sysmon->irq_lock) 329 sysmon->temp_mask |= mask; 330 } 331 return 0; 332 333 default: 334 return -EINVAL; 335 } 336 } 337 338 /* 339 * Recompute the lower threshold register from upper threshold and 340 * cached hysteresis. Called when either upper threshold or hysteresis 341 * is written. 342 */ 343 static int sysmon_update_temp_lower(struct sysmon *sysmon) 344 { 345 unsigned int upper_reg; 346 int upper_mc, lower_mc; 347 u32 raw_val; 348 int ret; 349 350 ret = regmap_read(sysmon->regmap, SYSMON_TEMP_TH_UP, &upper_reg); 351 if (ret) 352 return ret; 353 354 sysmon_q8p7_to_millicelsius(upper_reg, &upper_mc); 355 lower_mc = clamp(upper_mc - sysmon->temp_hysteresis, -256000, 255992); 356 sysmon_millicelsius_to_q8p7(&raw_val, lower_mc); 357 358 return regmap_write(sysmon->regmap, SYSMON_TEMP_TH_LOW, raw_val); 359 } 360 361 static int sysmon_read_event_value(struct iio_dev *indio_dev, 362 const struct iio_chan_spec *chan, 363 enum iio_event_type type, 364 enum iio_event_direction dir, 365 enum iio_event_info info, 366 int *val, int *val2) 367 { 368 struct sysmon *sysmon = iio_priv(indio_dev); 369 unsigned int reg_val; 370 int offset; 371 int ret; 372 373 guard(mutex)(&sysmon->lock); 374 375 switch (chan->type) { 376 case IIO_TEMP: 377 switch (info) { 378 case IIO_EV_INFO_VALUE: 379 ret = regmap_read(sysmon->regmap, SYSMON_TEMP_TH_UP, ®_val); 380 if (ret) 381 return ret; 382 383 sysmon_q8p7_to_millicelsius(reg_val, val); 384 385 return IIO_VAL_INT; 386 387 case IIO_EV_INFO_HYSTERESIS: 388 *val = sysmon->temp_hysteresis; 389 return IIO_VAL_INT; 390 391 default: 392 return -EINVAL; 393 } 394 395 case IIO_VOLTAGE: 396 offset = sysmon_supply_thresh_offset(chan->address, dir); 397 if (offset < 0) 398 return offset; 399 400 ret = regmap_read(sysmon->regmap, offset, ®_val); 401 if (ret) 402 return ret; 403 404 sysmon_supply_rawtoprocessed(reg_val, val); 405 406 return IIO_VAL_INT; 407 408 default: 409 return -EINVAL; 410 } 411 } 412 413 static int sysmon_write_event_value(struct iio_dev *indio_dev, 414 const struct iio_chan_spec *chan, 415 enum iio_event_type type, 416 enum iio_event_direction dir, 417 enum iio_event_info info, 418 int val, int val2) 419 { 420 struct sysmon *sysmon = iio_priv(indio_dev); 421 unsigned int reg_val; 422 u32 raw_val; 423 int offset; 424 int ret; 425 426 guard(mutex)(&sysmon->lock); 427 428 switch (chan->type) { 429 case IIO_TEMP: 430 switch (info) { 431 case IIO_EV_INFO_VALUE: 432 /* Q8.7 signed range: -256000 to +255992 mC */ 433 if (val < -256000 || val > 255992) 434 return -EINVAL; 435 436 sysmon_millicelsius_to_q8p7(&raw_val, val); 437 438 ret = regmap_write(sysmon->regmap, SYSMON_TEMP_TH_UP, raw_val); 439 if (ret) 440 return ret; 441 442 /* Recompute lower = upper - hysteresis */ 443 return sysmon_update_temp_lower(sysmon); 444 445 case IIO_EV_INFO_HYSTERESIS: 446 if (val < 0) 447 return -EINVAL; 448 449 sysmon->temp_hysteresis = val; 450 451 return sysmon_update_temp_lower(sysmon); 452 453 default: 454 return -EINVAL; 455 } 456 457 case IIO_VOLTAGE: 458 offset = sysmon_supply_thresh_offset(chan->address, dir); 459 if (offset < 0) 460 return offset; 461 462 ret = regmap_read(sysmon->regmap, offset, ®_val); 463 if (ret) 464 return ret; 465 466 /* Clamp to prevent overflow in processedtoraw conversion */ 467 if (val < -32768 || val > 32767) 468 return -EINVAL; 469 470 sysmon_supply_processedtoraw(val, reg_val, &raw_val); 471 472 /* 473 * The hardware threshold register returns FMT and MODE 474 * bits in the upper 16 bits on read, but only the lower 475 * 16-bit mantissa is used on write. 476 */ 477 return regmap_write(sysmon->regmap, offset, raw_val); 478 479 default: 480 return -EINVAL; 481 } 482 } 483 484 static int sysmon_set_avg_enable(struct sysmon *sysmon, 485 u32 base, u32 count, u32 val) 486 { 487 struct regmap *map = sysmon->regmap; 488 int ret; 489 490 for (unsigned int i = 0; i < count; i++) { 491 ret = regmap_write(map, base + i * SYSMON_REG_STRIDE, val); 492 if (ret) 493 return ret; 494 } 495 496 return 0; 497 } 498 499 static int sysmon_osr_write_temp(struct sysmon *sysmon, unsigned int val) 500 { 501 /* 502 * HW register encoding is sample_count / 2: 503 * 0=none, 1=2x, 2=4x, 4=8x, 8=16x (not log2-based). 504 */ 505 unsigned int hw_val = val >> 1; 506 unsigned int readback; 507 int ret; 508 509 ret = regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, 510 SYSMON_CONFIG_TEMP_SAT_OSR, 511 FIELD_PREP(SYSMON_CONFIG_TEMP_SAT_OSR, hw_val)); 512 if (ret) 513 return ret; 514 515 /* 516 * Readback fence: the SysMon CONFIG register resides in the 517 * PMC domain behind the NoC. A posted write may not reach the 518 * hardware before the next MMIO access. Reading the register 519 * back forces the interconnect to complete the write, preventing 520 * a bus hang on the subsequent access. 521 */ 522 regmap_read(sysmon->regmap, SYSMON_CONFIG, &readback); 523 524 return sysmon_set_avg_enable(sysmon, SYSMON_TEMP_EN_AVG_BASE, 525 SYSMON_TEMP_EN_AVG_COUNT, 526 hw_val ? ~0 : 0); 527 } 528 529 static int sysmon_osr_write_supply(struct sysmon *sysmon, unsigned int val) 530 { 531 /* HW encoding: sample_count / 2 (see sysmon_osr_write_temp) */ 532 unsigned int hw_val = val >> 1; 533 unsigned int readback; 534 int ret; 535 536 ret = regmap_update_bits(sysmon->regmap, SYSMON_CONFIG, 537 SYSMON_CONFIG_SUPPLY_OSR, 538 FIELD_PREP(SYSMON_CONFIG_SUPPLY_OSR, hw_val)); 539 if (ret) 540 return ret; 541 542 /* Readback fence -- see sysmon_osr_write_temp for details */ 543 regmap_read(sysmon->regmap, SYSMON_CONFIG, &readback); 544 545 return sysmon_set_avg_enable(sysmon, SYSMON_SUPPLY_EN_AVG_BASE, 546 SYSMON_SUPPLY_EN_AVG_COUNT, 547 hw_val ? ~0 : 0); 548 } 549 550 static int sysmon_write_raw(struct iio_dev *indio_dev, 551 struct iio_chan_spec const *chan, 552 int val, int val2, long mask) 553 { 554 struct sysmon *sysmon = iio_priv(indio_dev); 555 unsigned int i; 556 int ret; 557 558 if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) 559 return -EINVAL; 560 561 for (i = 0; i < ARRAY_SIZE(sysmon_oversampling_avail); i++) { 562 if (val == sysmon_oversampling_avail[i]) 563 break; 564 } 565 if (i == ARRAY_SIZE(sysmon_oversampling_avail)) 566 return -EINVAL; 567 568 guard(mutex)(&sysmon->lock); 569 570 if (chan->type == IIO_TEMP) { 571 ret = sysmon_osr_write_temp(sysmon, val); 572 if (ret) 573 return ret; 574 sysmon->temp_oversampling = val; 575 } else { 576 ret = sysmon_osr_write_supply(sysmon, val); 577 if (ret) 578 return ret; 579 sysmon->supply_oversampling = val; 580 } 581 582 return 0; 583 } 584 585 static int sysmon_write_raw_get_fmt(struct iio_dev *indio_dev, 586 struct iio_chan_spec const *chan, 587 long mask) 588 { 589 if (mask == IIO_CHAN_INFO_OVERSAMPLING_RATIO) 590 return IIO_VAL_INT; 591 592 return -EINVAL; 593 } 594 595 static int sysmon_read_avail(struct iio_dev *indio_dev, 596 struct iio_chan_spec const *chan, 597 const int **vals, int *type, 598 int *length, long mask) 599 { 600 if (mask != IIO_CHAN_INFO_OVERSAMPLING_RATIO) 601 return -EINVAL; 602 603 *vals = sysmon_oversampling_avail; 604 *type = IIO_VAL_INT; 605 *length = ARRAY_SIZE(sysmon_oversampling_avail); 606 607 return IIO_AVAIL_LIST; 608 } 609 610 static int sysmon_read_label(struct iio_dev *indio_dev, 611 struct iio_chan_spec const *chan, 612 char *label) 613 { 614 if (chan->datasheet_name) 615 return sysfs_emit(label, "%s\n", chan->datasheet_name); 616 617 return -EINVAL; 618 } 619 620 static const struct iio_info sysmon_iio_info = { 621 .read_raw = sysmon_read_raw, 622 .write_raw = sysmon_write_raw, 623 .write_raw_get_fmt = sysmon_write_raw_get_fmt, 624 .read_avail = sysmon_read_avail, 625 .read_label = sysmon_read_label, 626 .read_event_config = sysmon_read_event_config, 627 .write_event_config = sysmon_write_event_config, 628 .read_event_value = sysmon_read_event_value, 629 .write_event_value = sysmon_write_event_value, 630 }; 631 632 static void sysmon_push_event(struct iio_dev *indio_dev, u32 address) 633 { 634 const struct iio_chan_spec *chan; 635 enum iio_event_direction dir; 636 637 for (unsigned int i = 0; i < indio_dev->num_channels; i++) { 638 if (indio_dev->channels[i].address != address) 639 continue; 640 641 chan = &indio_dev->channels[i]; 642 /* Temp uses hysteresis mode (rising only), voltage uses window */ 643 dir = (chan->type == IIO_TEMP) ? IIO_EV_DIR_RISING : 644 IIO_EV_DIR_EITHER; 645 iio_push_event(indio_dev, 646 IIO_UNMOD_EVENT_CODE(chan->type, 647 chan->channel, 648 IIO_EV_TYPE_THRESH, 649 dir), 650 iio_get_time_ns(indio_dev)); 651 } 652 } 653 654 static int sysmon_handle_event(struct iio_dev *indio_dev, u32 event) 655 { 656 u32 alarm_flag_offset = SYSMON_ALARM_FLAG + event * SYSMON_REG_STRIDE; 657 u32 alarm_reg_offset = SYSMON_ALARM_REG + event * SYSMON_REG_STRIDE; 658 struct sysmon *sysmon = iio_priv(indio_dev); 659 unsigned long alarm_flag_reg; 660 unsigned int reg_val; 661 u32 address, bit; 662 int ret; 663 664 switch (event) { 665 case SYSMON_BIT_TEMP: 666 sysmon_push_event(indio_dev, SYSMON_TEMP_MAX); 667 668 ret = regmap_write(sysmon->regmap, SYSMON_IDR, BIT(SYSMON_BIT_TEMP)); 669 if (ret) 670 return ret; 671 672 sysmon->masked_temp |= BIT(SYSMON_BIT_TEMP); 673 return 0; 674 675 case SYSMON_BIT_ALARM0: 676 case SYSMON_BIT_ALARM1: 677 case SYSMON_BIT_ALARM2: 678 case SYSMON_BIT_ALARM3: 679 case SYSMON_BIT_ALARM4: 680 ret = regmap_read(sysmon->regmap, alarm_flag_offset, ®_val); 681 if (ret) 682 return ret; 683 684 alarm_flag_reg = reg_val; 685 686 for_each_set_bit(bit, &alarm_flag_reg, SYSMON_ALARM_BITS_PER_REG) { 687 address = bit + SYSMON_ALARM_BITS_PER_REG * event; 688 sysmon_push_event(indio_dev, address); 689 ret = regmap_clear_bits(sysmon->regmap, alarm_reg_offset, BIT(bit)); 690 if (ret) 691 return ret; 692 } 693 694 return regmap_write(sysmon->regmap, alarm_flag_offset, alarm_flag_reg); 695 696 default: 697 return -EINVAL; 698 } 699 } 700 701 static void sysmon_handle_events(struct iio_dev *indio_dev, 702 unsigned long events) 703 { 704 unsigned int bit; 705 706 for_each_set_bit(bit, &events, SYSMON_NO_OF_EVENTS) 707 sysmon_handle_event(indio_dev, bit); 708 } 709 710 static void sysmon_unmask_temp(struct sysmon *sysmon, unsigned int isr) 711 { 712 unsigned int status; 713 u32 ier; 714 715 status = isr & SYSMON_TEMP_INTR_MASK; 716 717 ier = ~status & sysmon->masked_temp; 718 sysmon->masked_temp &= status; 719 720 /* Only unmask if not administratively disabled by userspace */ 721 ier &= ~sysmon->temp_mask; 722 723 regmap_write(sysmon->regmap, SYSMON_IER, ier); 724 } 725 726 /* 727 * Versal threshold interrupts are level-sensitive. Active threshold 728 * interrupts are masked in the handler and polled via delayed work 729 * until the condition clears, then unmasked. 730 */ 731 static void sysmon_unmask_worker(struct work_struct *work) 732 { 733 struct sysmon *sysmon = 734 container_of(work, struct sysmon, sysmon_unmask_work.work); 735 unsigned int isr; 736 737 /* 738 * If the ISR read fails, skip processing to avoid acting 739 * on undefined data. 740 */ 741 scoped_guard(spinlock_irq, &sysmon->irq_lock) { 742 if (regmap_read(sysmon->regmap, SYSMON_ISR, &isr)) 743 break; 744 regmap_write(sysmon->regmap, SYSMON_ISR, isr); 745 sysmon_unmask_temp(sysmon, isr); 746 } 747 748 if (sysmon->masked_temp) 749 schedule_delayed_work(&sysmon->sysmon_unmask_work, 750 msecs_to_jiffies(SYSMON_UNMASK_WORK_DELAY_MS)); 751 else 752 regmap_write(sysmon->regmap, SYSMON_STATUS_RESET, 1); 753 } 754 755 static irqreturn_t sysmon_iio_irq(int irq, void *data) 756 { 757 struct iio_dev *indio_dev = data; 758 struct sysmon *sysmon = iio_priv(indio_dev); 759 unsigned int isr, imr; 760 761 guard(spinlock)(&sysmon->irq_lock); 762 763 if (regmap_read(sysmon->regmap, SYSMON_ISR, &isr) || 764 regmap_read(sysmon->regmap, SYSMON_IMR, &imr)) 765 return IRQ_NONE; 766 767 isr &= ~imr; 768 if (!isr) 769 return IRQ_NONE; 770 771 regmap_write(sysmon->regmap, SYSMON_ISR, isr); 772 773 sysmon_handle_events(indio_dev, isr); 774 schedule_delayed_work(&sysmon->sysmon_unmask_work, 775 msecs_to_jiffies(SYSMON_UNMASK_WORK_DELAY_MS)); 776 777 return IRQ_HANDLED; 778 } 779 780 static void sysmon_disable_interrupts(void *data) 781 { 782 struct sysmon *sysmon = data; 783 784 regmap_write(sysmon->regmap, SYSMON_IDR, SYSMON_INTR_ALL_MASK); 785 786 scoped_guard(spinlock_irq, &sysmon->irq_lock) 787 sysmon->masked_temp = 0; 788 789 cancel_delayed_work_sync(&sysmon->sysmon_unmask_work); 790 } 791 792 static int sysmon_init_interrupt(struct sysmon *sysmon, 793 struct device *dev, 794 struct iio_dev *indio_dev, 795 int irq) 796 { 797 unsigned int imr; 798 int ret; 799 800 /* Events not supported without IRQ (e.g. I2C path) */ 801 if (!irq) 802 return 0; 803 804 INIT_DELAYED_WORK(&sysmon->sysmon_unmask_work, sysmon_unmask_worker); 805 806 ret = regmap_read(sysmon->regmap, SYSMON_IMR, &imr); 807 if (ret) 808 return ret; 809 sysmon->temp_mask = imr & SYSMON_TEMP_INTR_MASK; 810 811 ret = devm_request_irq(dev, irq, sysmon_iio_irq, 0, "sysmon-irq", indio_dev); 812 if (ret) 813 return ret; 814 815 return devm_add_action_or_reset(dev, sysmon_disable_interrupts, sysmon); 816 } 817 818 /* 819 * Initialize the cached hysteresis for a temperature channel from the 820 * current hardware threshold registers: hysteresis = upper - lower. 821 */ 822 static int sysmon_init_hysteresis(struct sysmon *sysmon, int *hysteresis) 823 { 824 unsigned int upper_reg, lower_reg; 825 int upper_mc, lower_mc; 826 int ret; 827 828 ret = regmap_read(sysmon->regmap, SYSMON_TEMP_TH_UP, &upper_reg); 829 if (ret) 830 return ret; 831 832 ret = regmap_read(sysmon->regmap, SYSMON_TEMP_TH_LOW, &lower_reg); 833 if (ret) 834 return ret; 835 836 sysmon_q8p7_to_millicelsius(upper_reg, &upper_mc); 837 sysmon_q8p7_to_millicelsius(lower_reg, &lower_mc); 838 *hysteresis = upper_mc - lower_mc; 839 840 return 0; 841 } 842 843 /** 844 * sysmon_parse_fw() - Parse firmware nodes and configure IIO channels. 845 * @indio_dev: IIO device instance 846 * @dev: Parent device 847 * @irq: IRQ number (positive enables event channels, 0 disables) 848 * 849 * Reads voltage-channels and temperature-channels container nodes from 850 * firmware and builds the IIO channel array. Static temperature channels 851 * and event channels are prepended, followed by supply and satellite 852 * channels from DT. 853 * 854 * Event channels and per-channel event specs are only added when the 855 * device has an IRQ. I2C devices have no interrupt line, and the I2C 856 * regmap cannot be called from atomic context, so events are not 857 * supported on that path. 858 * 859 * Return: 0 on success, negative errno on failure. 860 */ 861 static int sysmon_parse_fw(struct iio_dev *indio_dev, struct device *dev, int irq) 862 { 863 unsigned int num_chan, num_static, num_supply, num_temp; 864 unsigned int idx, temp_chan_idx, volt_chan_idx; 865 struct iio_chan_spec *sysmon_channels; 866 const char *label; 867 u32 reg; 868 int ret; 869 870 struct fwnode_handle *supply_node __free(fwnode_handle) = 871 device_get_named_child_node(dev, "voltage-channels"); 872 num_supply = fwnode_get_child_node_count(supply_node); 873 874 struct fwnode_handle *temp_node __free(fwnode_handle) = 875 device_get_named_child_node(dev, "temperature-channels"); 876 num_temp = fwnode_get_child_node_count(temp_node); 877 878 num_static = ARRAY_SIZE(temp_channels); 879 num_chan = size_add(num_temp, size_add(num_static, num_supply)); 880 sysmon_channels = devm_kcalloc(dev, num_chan, sizeof(*sysmon_channels), GFP_KERNEL); 881 if (!sysmon_channels) 882 return -ENOMEM; 883 884 memcpy(sysmon_channels, temp_channels, sizeof(temp_channels)); 885 886 /* Attach event spec to channel 0 when IRQ is available */ 887 if (irq > 0) { 888 sysmon_channels[0].event_spec = sysmon_temp_events; 889 sysmon_channels[0].num_event_specs = ARRAY_SIZE(sysmon_temp_events); 890 } 891 892 idx = num_static; 893 894 /* Supply channels from DT */ 895 fwnode_for_each_child_node_scoped(supply_node, child) { 896 ret = fwnode_property_read_u32(child, "reg", ®); 897 if (ret) 898 return dev_err_probe(dev, ret, 899 "missing reg for supply channel\n"); 900 901 if (reg > SYSMON_SUPPLY_IDX_MAX) 902 return dev_err_probe(dev, -EINVAL, 903 "supply reg %u exceeds max %u\n", 904 reg, SYSMON_SUPPLY_IDX_MAX); 905 906 ret = fwnode_property_read_string(child, "label", &label); 907 if (ret) 908 return dev_err_probe(dev, ret, 909 "missing label for supply channel\n"); 910 911 sysmon_channels[idx++] = (struct iio_chan_spec) { 912 .type = IIO_VOLTAGE, 913 .indexed = 1, 914 .address = reg, 915 .info_mask_separate = BIT(IIO_CHAN_INFO_PROCESSED), 916 .info_mask_shared_by_type = 917 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 918 .info_mask_shared_by_type_available = 919 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 920 .event_spec = irq > 0 ? 921 sysmon_supply_events : NULL, 922 .num_event_specs = irq > 0 ? 923 ARRAY_SIZE(sysmon_supply_events) : 0, 924 .datasheet_name = label, 925 }; 926 } 927 928 /* Temperature satellite channels from DT */ 929 fwnode_for_each_child_node_scoped(temp_node, child) { 930 ret = fwnode_property_read_u32(child, "reg", ®); 931 if (ret) 932 return dev_err_probe(dev, ret, 933 "missing reg for temp channel\n"); 934 935 if (reg < 1 || reg > SYSMON_TEMP_SAT_MAX) 936 return dev_err_probe(dev, -EINVAL, 937 "temp reg %u out of range [1..%u]\n", 938 reg, SYSMON_TEMP_SAT_MAX); 939 940 ret = fwnode_property_read_string(child, "label", &label); 941 if (ret) 942 return dev_err_probe(dev, ret, 943 "missing label for temp channel\n"); 944 945 sysmon_channels[idx++] = (struct iio_chan_spec) { 946 .type = IIO_TEMP, 947 .indexed = 1, 948 .address = SYSMON_TEMP_SAT_BASE + 949 (reg - 1) * SYSMON_REG_STRIDE, 950 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), 951 .info_mask_shared_by_type = 952 BIT(IIO_CHAN_INFO_SCALE) | 953 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 954 .info_mask_shared_by_type_available = 955 BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), 956 .datasheet_name = label, 957 }; 958 } 959 960 indio_dev->num_channels = idx; 961 indio_dev->info = &sysmon_iio_info; 962 963 /* 964 * Assign per-type sequential channel numbers. 965 * IIO sysfs uses type prefix (in_tempN, in_voltageN) 966 * so numbers only need to be unique within each type. 967 */ 968 temp_chan_idx = 0; 969 volt_chan_idx = 0; 970 for (unsigned int idx = 0; idx < indio_dev->num_channels; idx++) { 971 if (sysmon_channels[idx].type == IIO_TEMP) 972 sysmon_channels[idx].channel = temp_chan_idx++; 973 else 974 sysmon_channels[idx].channel = volt_chan_idx++; 975 } 976 977 indio_dev->channels = sysmon_channels; 978 979 return 0; 980 } 981 982 /** 983 * devm_versal_sysmon_core_probe() - Initialize Versal SysMon core 984 * @dev: Parent device 985 * @regmap: Register map for hardware access 986 * 987 * Return: 0 on success, negative errno on failure. 988 */ 989 int devm_versal_sysmon_core_probe(struct device *dev, struct regmap *regmap) 990 { 991 struct iio_dev *indio_dev; 992 struct sysmon *sysmon; 993 int irq; 994 int ret; 995 996 indio_dev = devm_iio_device_alloc(dev, sizeof(*sysmon)); 997 if (!indio_dev) 998 return -ENOMEM; 999 1000 sysmon = iio_priv(indio_dev); 1001 sysmon->regmap = regmap; 1002 sysmon->temp_oversampling = 1; 1003 sysmon->supply_oversampling = 1; 1004 1005 ret = devm_mutex_init(dev, &sysmon->lock); 1006 if (ret) 1007 return ret; 1008 spin_lock_init(&sysmon->irq_lock); 1009 1010 /* Disable all interrupts and clear pending status */ 1011 ret = regmap_write(sysmon->regmap, SYSMON_IDR, SYSMON_INTR_ALL_MASK); 1012 if (ret) 1013 return ret; 1014 ret = regmap_write(sysmon->regmap, SYSMON_ISR, SYSMON_INTR_ALL_MASK); 1015 if (ret) 1016 return ret; 1017 1018 irq = fwnode_irq_get(dev_fwnode(dev), 0); 1019 if (irq == -EPROBE_DEFER) 1020 return dev_err_probe(dev, irq, "failed to get IRQ\n"); 1021 1022 indio_dev->name = "versal-sysmon"; 1023 indio_dev->modes = INDIO_DIRECT_MODE; 1024 1025 ret = sysmon_parse_fw(indio_dev, dev, irq); 1026 if (ret) 1027 return ret; 1028 1029 if (irq > 0) { 1030 /* Set hysteresis mode for temperature threshold */ 1031 ret = regmap_set_bits(sysmon->regmap, SYSMON_TEMP_EV_CFG, 1032 SYSMON_TEMP_HYST_MASK); 1033 if (ret) 1034 return ret; 1035 1036 /* Initialize cached hysteresis from hardware registers */ 1037 ret = sysmon_init_hysteresis(sysmon, &sysmon->temp_hysteresis); 1038 if (ret) 1039 return ret; 1040 1041 ret = sysmon_init_interrupt(sysmon, dev, indio_dev, irq); 1042 if (ret) 1043 return ret; 1044 } 1045 1046 return devm_iio_device_register(dev, indio_dev); 1047 } 1048 EXPORT_SYMBOL_NS_GPL(devm_versal_sysmon_core_probe, "VERSAL_SYSMON"); 1049 1050 MODULE_LICENSE("GPL"); 1051 MODULE_DESCRIPTION("AMD Versal SysMon Core Driver"); 1052 MODULE_AUTHOR("Salih Erim <salih.erim@amd.com>"); 1053