1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Analog Devices LTC2378 ADC series driver 4 * 5 * Copyright (C) 2026 Analog Devices Inc. 6 * Author: Marcelo Schmitt <marcelo.schmitt@analog.com> 7 */ 8 9 #include <linux/array_size.h> 10 #include <linux/bitops.h> 11 #include <linux/bits.h> 12 #include <linux/byteorder/generic.h> 13 #include <linux/cleanup.h> 14 #include <linux/device.h> 15 #include <linux/delay.h> 16 #include <linux/device-id/spi.h> 17 #include <linux/device-id/of.h> 18 #include <linux/err.h> 19 #include <linux/gpio/consumer.h> 20 #include <linux/math64.h> 21 #include <linux/minmax.h> 22 #include <linux/module.h> 23 #include <linux/mutex.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/pwm.h> 26 #include <linux/spi/spi.h> 27 #include <linux/spi/offload/consumer.h> 28 #include <linux/spi/offload/types.h> 29 #include <linux/time64.h> 30 #include <linux/types.h> 31 #include <linux/units.h> 32 33 #include <linux/iio/buffer.h> 34 #include <linux/iio/buffer-dmaengine.h> 35 #include <linux/iio/iio.h> 36 #include <linux/iio/triggered_buffer.h> 37 #include <linux/iio/trigger_consumer.h> 38 #include <linux/iio/types.h> 39 40 #define LTC2378_TDSDOBUSYL_NS 5 41 #define LTC2378_TBUSYLH_NS 13 42 #define LTC2378_TCNV_HIGH_NS 20 43 #define LTC2378_MAX_DATA_WAIT_US 4 /* max(TBUSYLH + TCONV + TDSDOBUSYL) */ 44 45 #define LTC2378_CHANNEL(_sign, _real_bits, _storage_bits) \ 46 { \ 47 .type = IIO_VOLTAGE, \ 48 .indexed = 1, \ 49 .differential = _sign, \ 50 .channel = 0, \ 51 .channel2 = _sign ? 1 : 0, \ 52 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 53 BIT(IIO_CHAN_INFO_SCALE), \ 54 .scan_index = 0, \ 55 .scan_type = { \ 56 .format = _sign ? IIO_SCAN_FORMAT_SIGNED_INT : \ 57 IIO_SCAN_FORMAT_UNSIGNED_INT, \ 58 .realbits = _real_bits, \ 59 .storagebits = _storage_bits, \ 60 .shift = _storage_bits - _real_bits, \ 61 .endianness = IIO_BE, \ 62 }, \ 63 } 64 65 #define LTC2378_DIFF_CHANNEL(_real_bits) \ 66 LTC2378_CHANNEL(1, _real_bits, (((_real_bits) > 16) ? 32 : 16)) 67 68 #define LTC2378_PSEUDO_DIFF_CHANNEL(_real_bits) \ 69 LTC2378_CHANNEL(0, _real_bits, (((_real_bits) > 16) ? 32 : 16)) 70 71 #define LTC2378_OFFLOAD_CHANNEL(_sign, _real_bits, _storage_bits) \ 72 { \ 73 .type = IIO_VOLTAGE, \ 74 .indexed = 1, \ 75 .differential = _sign, \ 76 .channel = 0, \ 77 .channel2 = _sign ? 1 : 0, \ 78 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW) | \ 79 BIT(IIO_CHAN_INFO_SCALE) | \ 80 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 81 .info_mask_separate_available = BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 82 .scan_index = 0, \ 83 .scan_type = { \ 84 .format = _sign ? IIO_SCAN_FORMAT_SIGNED_INT : \ 85 IIO_SCAN_FORMAT_UNSIGNED_INT, \ 86 .realbits = _real_bits, \ 87 .storagebits = _storage_bits, \ 88 .shift = 0, \ 89 .endianness = IIO_CPU, \ 90 }, \ 91 } 92 93 /* 94 * Currently, the available offload hardware + DMA configuration only supports 95 * pushing 32-bit data elements to DMA IIO buffers in CPU endianness. For 16-bit 96 * precision parts, those 32-bit elements (in CPU endianness) contain 2 bytes 97 * with data and 2 bytes always zeroed out. Nevertheless, for the offload use 98 * case, the IIO buffer is configured for 32 storage bits in CPU endianness so 99 * data is correctly aligned in user space despite 2 out of the 4 bytes being 100 * zeros. 101 */ 102 #define LTC2378_OFFLOAD_DIFF_CHANNEL(_real_bits) \ 103 LTC2378_OFFLOAD_CHANNEL(1, (_real_bits), 32) 104 105 #define LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(_real_bits) \ 106 LTC2378_OFFLOAD_CHANNEL(0, (_real_bits), 32) 107 108 struct ltc2378_chip_info { 109 const char *name; 110 unsigned int internal_ref_uV; 111 struct u32_fract internal_div; 112 struct iio_chan_spec chan[2]; /* 1 physical chan + 1 timestamp chan */ 113 struct iio_chan_spec offload_chan; 114 unsigned int max_sample_rate_Hz; 115 unsigned int tconv_ns; 116 }; 117 118 struct ltc2378_state { 119 const struct ltc2378_chip_info *info; 120 struct gpio_desc *cnv_gpio; 121 struct spi_device *spi; 122 struct mutex lock; /* Protect data acquisition cycle */ 123 int ref_uV; 124 struct spi_transfer xfer; 125 struct spi_transfer offload_xfer; 126 struct spi_offload *offload; 127 struct spi_offload_trigger *offload_trigger; 128 struct pwm_waveform cnv_wf; 129 struct spi_message offload_msg; 130 struct spi_offload_trigger_config offload_trigger_config; 131 struct pwm_device *cnv_trigger; 132 unsigned int cnv_Hz; 133 unsigned int sample_freq_range[3]; 134 135 /* 136 * DMA (thus cache coherency maintenance) requires the transfer buffers 137 * to live in their own cache lines. 138 */ 139 struct { 140 union { 141 __be16 sample_buf16_be; 142 __be32 sample_buf32_be; 143 u16 sample_buf16; 144 u32 sample_buf32; 145 } data; 146 aligned_s64 timestamp; 147 } scan __aligned(IIO_DMA_MINALIGN); 148 }; 149 150 static const struct ltc2378_chip_info ltc2338_18_chip_info = { 151 .name = "ltc2338-18", 152 .internal_ref_uV = 2048000, 153 .internal_div = { .numerator = 5, .denominator = 2 }, 154 .chan = { LTC2378_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 155 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(18), 156 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 157 .tconv_ns = 527, 158 }; 159 160 static const struct ltc2378_chip_info ltc2364_16_chip_info = { 161 .name = "ltc2364-16", 162 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 163 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(16), 164 .max_sample_rate_Hz = 250 * HZ_PER_KHZ, 165 .tconv_ns = 3000, 166 }; 167 168 static const struct ltc2378_chip_info ltc2364_18_chip_info = { 169 .name = "ltc2364-18", 170 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 171 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(18), 172 .max_sample_rate_Hz = 250 * HZ_PER_KHZ, 173 .tconv_ns = 3000, 174 }; 175 176 static const struct ltc2378_chip_info ltc2367_16_chip_info = { 177 .name = "ltc2367-16", 178 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 179 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(16), 180 .max_sample_rate_Hz = 500 * HZ_PER_KHZ, 181 .tconv_ns = 1500, 182 }; 183 184 static const struct ltc2378_chip_info ltc2367_18_chip_info = { 185 .name = "ltc2367-18", 186 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 187 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(18), 188 .max_sample_rate_Hz = 500 * HZ_PER_KHZ, 189 .tconv_ns = 1500, 190 }; 191 192 static const struct ltc2378_chip_info ltc2368_16_chip_info = { 193 .name = "ltc2368-16", 194 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 195 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(16), 196 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 197 .tconv_ns = 527, 198 }; 199 200 static const struct ltc2378_chip_info ltc2368_18_chip_info = { 201 .name = "ltc2368-18", 202 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 203 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(18), 204 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 205 .tconv_ns = 527, 206 }; 207 208 static const struct ltc2378_chip_info ltc2369_18_chip_info = { 209 .name = "ltc2369-18", 210 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 211 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(18), 212 .max_sample_rate_Hz = 1600 * HZ_PER_KHZ, 213 .tconv_ns = 412, 214 }; 215 216 static const struct ltc2378_chip_info ltc2370_16_chip_info = { 217 .name = "ltc2370-16", 218 .chan = { LTC2378_PSEUDO_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 219 .offload_chan = LTC2378_OFFLOAD_PSEUDO_DIFF_CHANNEL(16), 220 .max_sample_rate_Hz = 2 * HZ_PER_MHZ, 221 .tconv_ns = 322, 222 }; 223 224 static const struct ltc2378_chip_info ltc2376_16_chip_info = { 225 .name = "ltc2376-16", 226 .chan = { LTC2378_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 227 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(16), 228 .max_sample_rate_Hz = 250 * HZ_PER_KHZ, 229 .tconv_ns = 3000, 230 }; 231 232 static const struct ltc2378_chip_info ltc2376_18_chip_info = { 233 .name = "ltc2376-18", 234 .chan = { LTC2378_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 235 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(18), 236 .max_sample_rate_Hz = 250 * HZ_PER_KHZ, 237 .tconv_ns = 3000, 238 }; 239 240 static const struct ltc2378_chip_info ltc2376_20_chip_info = { 241 .name = "ltc2376-20", 242 .chan = { LTC2378_DIFF_CHANNEL(20), IIO_CHAN_SOFT_TIMESTAMP(1) }, 243 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(20), 244 .max_sample_rate_Hz = 250 * HZ_PER_KHZ, 245 .tconv_ns = 3000, 246 }; 247 248 static const struct ltc2378_chip_info ltc2377_16_chip_info = { 249 .name = "ltc2377-16", 250 .chan = { LTC2378_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 251 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(16), 252 .max_sample_rate_Hz = 500 * HZ_PER_KHZ, 253 .tconv_ns = 1500, 254 }; 255 256 static const struct ltc2378_chip_info ltc2377_18_chip_info = { 257 .name = "ltc2377-18", 258 .chan = { LTC2378_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 259 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(18), 260 .max_sample_rate_Hz = 500 * HZ_PER_KHZ, 261 .tconv_ns = 1500, 262 }; 263 264 static const struct ltc2378_chip_info ltc2377_20_chip_info = { 265 .name = "ltc2377-20", 266 .chan = { LTC2378_DIFF_CHANNEL(20), IIO_CHAN_SOFT_TIMESTAMP(1) }, 267 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(20), 268 .max_sample_rate_Hz = 500 * HZ_PER_KHZ, 269 .tconv_ns = 1500, 270 }; 271 272 static const struct ltc2378_chip_info ltc2378_16_chip_info = { 273 .name = "ltc2378-16", 274 .chan = { LTC2378_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 275 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(16), 276 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 277 .tconv_ns = 527, 278 }; 279 280 static const struct ltc2378_chip_info ltc2378_18_chip_info = { 281 .name = "ltc2378-18", 282 .chan = { LTC2378_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 283 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(18), 284 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 285 .tconv_ns = 527, 286 }; 287 288 static const struct ltc2378_chip_info ltc2378_20_chip_info = { 289 .name = "ltc2378-20", 290 .chan = { LTC2378_DIFF_CHANNEL(20), IIO_CHAN_SOFT_TIMESTAMP(1) }, 291 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(20), 292 .max_sample_rate_Hz = 1 * HZ_PER_MHZ, 293 .tconv_ns = 675, 294 }; 295 296 static const struct ltc2378_chip_info ltc2379_18_chip_info = { 297 .name = "ltc2379-18", 298 .chan = { LTC2378_DIFF_CHANNEL(18), IIO_CHAN_SOFT_TIMESTAMP(1) }, 299 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(18), 300 .max_sample_rate_Hz = 1600 * HZ_PER_KHZ, 301 .tconv_ns = 412, 302 }; 303 304 static const struct ltc2378_chip_info ltc2380_16_chip_info = { 305 .name = "ltc2380-16", 306 .chan = { LTC2378_DIFF_CHANNEL(16), IIO_CHAN_SOFT_TIMESTAMP(1) }, 307 .offload_chan = LTC2378_OFFLOAD_DIFF_CHANNEL(16), 308 .max_sample_rate_Hz = 2 * HZ_PER_MHZ, 309 .tconv_ns = 322, 310 }; 311 312 static int ltc2378_convert_and_acquire(struct ltc2378_state *st) 313 { 314 int ret; 315 316 /* Cause a rising edge of CNV to initiate a new ADC conversion */ 317 gpiod_set_value_cansleep(st->cnv_gpio, 1); 318 fsleep(LTC2378_MAX_DATA_WAIT_US); 319 ret = spi_sync_transfer(st->spi, &st->xfer, 1); 320 gpiod_set_value_cansleep(st->cnv_gpio, 0); 321 322 return ret; 323 } 324 325 static irqreturn_t ltc2378_trigger_handler(int irq, void *p) 326 { 327 struct iio_poll_func *pf = p; 328 struct iio_dev *indio_dev = pf->indio_dev; 329 struct ltc2378_state *st = iio_priv(indio_dev); 330 int ret; 331 332 ret = ltc2378_convert_and_acquire(st); 333 if (ret < 0) 334 goto err_out; 335 336 iio_push_to_buffers_with_ts(indio_dev, &st->scan, sizeof(st->scan), 337 pf->timestamp); 338 339 err_out: 340 iio_trigger_notify_done(indio_dev->trig); 341 return IRQ_HANDLED; 342 } 343 344 static int ltc2378_channel_single_read(const struct iio_chan_spec *chan, 345 struct ltc2378_state *st, int *val) 346 { 347 const struct iio_scan_type *scan_type = &chan->scan_type; 348 u32 sample; 349 int ret; 350 351 guard(mutex)(&st->lock); 352 ret = ltc2378_convert_and_acquire(st); 353 if (ret) 354 return ret; 355 356 if (chan->scan_type.endianness == IIO_BE) { 357 if (chan->scan_type.realbits > 16) 358 sample = be32_to_cpu(st->scan.data.sample_buf32_be); 359 else 360 sample = be16_to_cpu(st->scan.data.sample_buf16_be); 361 } else { /* IIO_CPU */ 362 if (chan->scan_type.realbits > 16) 363 sample = st->scan.data.sample_buf32; 364 else 365 sample = st->scan.data.sample_buf16; 366 } 367 368 sample >>= chan->scan_type.shift; 369 370 if (scan_type->format == IIO_SCAN_FORMAT_SIGNED_INT) 371 *val = sign_extend32(sample, scan_type->realbits - 1); 372 else 373 *val = sample; 374 375 return 0; 376 } 377 378 static int ltc2378_read_raw(struct iio_dev *indio_dev, 379 const struct iio_chan_spec *chan, 380 int *val, int *val2, long mask) 381 { 382 struct ltc2378_state *st = iio_priv(indio_dev); 383 int ret; 384 385 switch (mask) { 386 case IIO_CHAN_INFO_RAW: { 387 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); 388 if (IIO_DEV_ACQUIRE_FAILED(claim)) 389 return -EBUSY; 390 391 ret = ltc2378_channel_single_read(chan, st, val); 392 if (ret) 393 return ret; 394 395 return IIO_VAL_INT; 396 } 397 case IIO_CHAN_INFO_SCALE: { 398 struct u32_fract fract = st->info->internal_div; 399 *val = st->ref_uV / MILLI; 400 if (fract.numerator && fract.denominator) 401 *val = mult_frac(*val, fract.numerator, fract.denominator); 402 /* 403 * For all LTC2378-like devices, the amount of bits that express 404 * voltage magnitude depend on the polarity / output code format: 405 * - straight binary: All precision/resolution bits are used. 406 * - 2's complement: One of the precision bits is used for sign. 407 */ 408 if (chan->scan_type.format == IIO_SCAN_FORMAT_SIGNED_INT) 409 *val2 = chan->scan_type.realbits - 1; 410 else 411 *val2 = chan->scan_type.realbits; 412 413 return IIO_VAL_FRACTIONAL_LOG2; 414 } 415 case IIO_CHAN_INFO_SAMP_FREQ: 416 *val = st->cnv_Hz; 417 return IIO_VAL_INT; 418 default: 419 return -EINVAL; 420 } 421 } 422 423 static int ltc2378_read_avail(struct iio_dev *indio_dev, 424 struct iio_chan_spec const *chan, 425 const int **vals, int *type, int *length, long mask) 426 { 427 struct ltc2378_state *st = iio_priv(indio_dev); 428 429 switch (mask) { 430 case IIO_CHAN_INFO_SAMP_FREQ: 431 *vals = st->sample_freq_range; 432 *type = IIO_VAL_INT; 433 return IIO_AVAIL_RANGE; 434 default: 435 return -EINVAL; 436 } 437 } 438 439 /* 440 * SPI offload wiring schema 441 * 442 * +-------------+ +-------------+ 443 * | CNV |<-----+--| GPIO | 444 * | | +--| PWM0 | 445 * | | | | 446 * | | +--| PWM1 | 447 * | | | +-------------+ 448 * | | +->| TRIGGER | 449 * | | | | 450 * | ADC | | SPI | 451 * | | | controller | 452 * | | | | 453 * | SDI |<--------| SDO | 454 * | SDO |-------->| SDI | 455 * | SCLK |<--------| SCLK | 456 * +-------------+ +-------------+ 457 * 458 */ 459 static int ltc2378_update_conversion_rate(struct ltc2378_state *st, int freq_Hz) 460 { 461 struct spi_offload_trigger_config config = st->offload_trigger_config; 462 unsigned int min_read_offset, offload_period_ns; 463 struct pwm_waveform cnv_wf = { }; 464 u64 target = LTC2378_TCNV_HIGH_NS; 465 unsigned int count; 466 u64 offload_offset_ns; 467 int ret; 468 469 if (freq_Hz == 0) 470 return -EINVAL; 471 472 if (!in_range(freq_Hz, 1, st->info->max_sample_rate_Hz)) 473 return -ERANGE; 474 475 /* Configure CNV PWM waveform */ 476 cnv_wf.period_length_ns = DIV_ROUND_CLOSEST(NSEC_PER_SEC, freq_Hz); 477 478 /* 479 * Ensure CNV high time meets minimum requirement (20ns). The PWM 480 * hardware may round the duty cycle, so iterate until we get at least 481 * the minimum required high time (or reach a try count limit). 482 */ 483 count = 100; 484 do { 485 cnv_wf.duty_length_ns = target; 486 ret = pwm_round_waveform_might_sleep(st->cnv_trigger, &cnv_wf); 487 if (ret) 488 return ret; 489 target += 10; /* Increment by PWM duty cycle period */ 490 } while (count-- && cnv_wf.duty_length_ns < LTC2378_TCNV_HIGH_NS); 491 492 /* Check the minimum CNV high time is met */ 493 if (cnv_wf.duty_length_ns < LTC2378_TCNV_HIGH_NS) 494 return -EDOM; 495 496 /* 497 * Configure SPI offload PWM trigger. 498 * The trigger should fire after tBUSYLH + tCONV + tDSDOBUSYL. 499 * Minimum time needed: TBUSYLH (13ns) + TCONV (part-specific) + TDSDOBUSYL (5ns) 500 * 501 * Use the same period as CNV PWM to avoid timing issues. 502 * Convert back from period to frequency for the SPI offload API. 503 */ 504 offload_period_ns = cnv_wf.period_length_ns; 505 config.periodic.frequency_hz = div_u64(HZ_PER_GHZ, offload_period_ns); 506 min_read_offset = LTC2378_TBUSYLH_NS + st->info->tconv_ns + LTC2378_TDSDOBUSYL_NS; 507 offload_offset_ns = min_read_offset; 508 count = 100; 509 do { 510 config.periodic.offset_ns = offload_offset_ns; 511 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 512 if (ret) 513 return ret; 514 offload_offset_ns += 10; 515 } while (count-- && config.periodic.offset_ns < min_read_offset); 516 517 /* Check the minimum CNV to SCLK delay is met */ 518 if (config.periodic.offset_ns < min_read_offset) 519 return -EDOM; 520 521 /* Check the PWM periods remain the same */ 522 offload_period_ns = div64_u64(HZ_PER_GHZ, config.periodic.frequency_hz); 523 if (cnv_wf.period_length_ns != offload_period_ns) 524 return -EDOM; 525 526 st->offload_trigger_config = config; 527 st->cnv_wf = cnv_wf; 528 st->cnv_Hz = DIV_ROUND_CLOSEST_ULL(HZ_PER_GHZ, cnv_wf.period_length_ns); 529 530 return 0; 531 } 532 533 static int ltc2378_write_raw(struct iio_dev *indio_dev, 534 struct iio_chan_spec const *chan, 535 int val, int val2, long mask) 536 { 537 struct ltc2378_state *st = iio_priv(indio_dev); 538 539 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); 540 if (IIO_DEV_ACQUIRE_FAILED(claim)) 541 return -EBUSY; 542 543 switch (mask) { 544 case IIO_CHAN_INFO_SAMP_FREQ: 545 return ltc2378_update_conversion_rate(st, val); 546 default: 547 return -EINVAL; 548 } 549 } 550 551 static const struct iio_info ltc2378_iio_info = { 552 .read_raw = <c2378_read_raw, 553 }; 554 555 static const struct iio_info ltc2378_offload_iio_info = { 556 .read_raw = <c2378_read_raw, 557 .read_avail = <c2378_read_avail, 558 .write_raw = <c2378_write_raw, 559 }; 560 561 static int ltc2378_offload_buffer_postenable(struct iio_dev *indio_dev) 562 { 563 struct ltc2378_state *st = iio_priv(indio_dev); 564 int ret; 565 566 ret = pwm_set_waveform_might_sleep(st->cnv_trigger, &st->cnv_wf, true); 567 if (ret) 568 return ret; 569 570 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, 571 &st->offload_trigger_config); 572 if (ret) 573 goto out_pwm_disable; 574 575 return 0; 576 577 out_pwm_disable: 578 pwm_disable(st->cnv_trigger); 579 return ret; 580 } 581 582 static int ltc2378_offload_buffer_predisable(struct iio_dev *indio_dev) 583 { 584 struct ltc2378_state *st = iio_priv(indio_dev); 585 586 spi_offload_trigger_disable(st->offload, st->offload_trigger); 587 pwm_disable(st->cnv_trigger); 588 589 return 0; 590 } 591 592 static const struct iio_buffer_setup_ops ltc2378_offload_buffer_ops = { 593 .postenable = <c2378_offload_buffer_postenable, 594 .predisable = <c2378_offload_buffer_predisable, 595 }; 596 597 static int ltc2378_prepare_offload_message(struct device *dev, 598 struct ltc2378_state *st) 599 { 600 unsigned int resolution = st->info->offload_chan.scan_type.realbits; 601 602 st->offload_xfer.bits_per_word = resolution; 603 st->offload_xfer.len = spi_bpw_to_bytes(resolution); 604 st->offload_xfer.offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 605 606 /* Initialize message with offload */ 607 spi_message_init_with_transfers(&st->offload_msg, &st->offload_xfer, 1); 608 st->offload_msg.offload = st->offload; 609 610 return devm_spi_optimize_message(dev, st->spi, &st->offload_msg); 611 } 612 613 static int ltc2378_spi_offload_setup(struct iio_dev *indio_dev, 614 struct ltc2378_state *st) 615 { 616 struct device *dev = &st->spi->dev; 617 struct dma_chan *rx_dma; 618 619 indio_dev->setup_ops = <c2378_offload_buffer_ops; 620 621 st->offload_trigger = devm_spi_offload_trigger_get(dev, st->offload, 622 SPI_OFFLOAD_TRIGGER_PERIODIC); 623 if (IS_ERR(st->offload_trigger)) 624 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 625 "failed to get offload trigger\n"); 626 627 st->offload_trigger_config.type = SPI_OFFLOAD_TRIGGER_PERIODIC; 628 629 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 630 if (IS_ERR(rx_dma)) 631 return dev_err_probe(dev, PTR_ERR(rx_dma), "failed to get offload RX DMA\n"); 632 633 return devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 634 IIO_BUFFER_DIRECTION_IN); 635 } 636 637 static int ltc2378_pwm_get(struct ltc2378_state *st) 638 { 639 struct device *dev = &st->spi->dev; 640 641 st->cnv_trigger = devm_pwm_get(dev, NULL); 642 if (IS_ERR(st->cnv_trigger)) 643 return dev_err_probe(dev, PTR_ERR(st->cnv_trigger), 644 "failed to get cnv pwm\n"); 645 646 /* 647 * Disable the PWM connected to CNV in case it was left running by 648 * something else. 649 */ 650 pwm_disable(st->cnv_trigger); 651 652 return 0; 653 } 654 655 static const struct spi_offload_config ltc2378_offload_config = { 656 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 657 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 658 }; 659 660 static int ltc2378_refin_setup(struct device *dev, struct ltc2378_state *st) 661 { 662 int ret; 663 664 /* 665 * The internal reference buffer amplifies both the internal reference 666 * and REFIN by a factor of 2. 667 */ 668 ret = devm_regulator_get_enable_read_voltage(dev, "refin"); 669 if (ret == -ENODEV) { /* refin is optional */ 670 st->ref_uV = st->info->internal_ref_uV * 2; 671 return 0; 672 } 673 674 if (ret < 0) 675 return dev_err_probe(dev, ret, "failed to read refin regulator\n"); 676 677 st->ref_uV = ret * 2; 678 679 return 0; 680 } 681 682 static int ltc2378_ref_setup(struct device *dev, struct ltc2378_state *st) 683 { 684 int ret; 685 686 ret = devm_regulator_get_enable_read_voltage(dev, "ref"); 687 if (ret < 0) 688 return dev_err_probe(dev, ret, "failed to read ref regulator\n"); 689 690 st->ref_uV = ret; 691 692 return 0; 693 } 694 695 static int ltc2378_probe(struct spi_device *spi) 696 { 697 struct device *dev = &spi->dev; 698 struct iio_dev *indio_dev; 699 struct ltc2378_state *st; 700 int ret; 701 702 indio_dev = devm_iio_device_alloc(&spi->dev, sizeof(*st)); 703 if (!indio_dev) 704 return -ENOMEM; 705 706 st = iio_priv(indio_dev); 707 st->spi = spi; 708 709 ret = devm_mutex_init(dev, &st->lock); 710 if (ret) 711 return ret; 712 713 st->info = spi_get_device_match_data(spi); 714 if (!st->info) 715 return -EINVAL; 716 717 if (st->info->internal_ref_uV) 718 ret = ltc2378_refin_setup(dev, st); 719 else 720 ret = ltc2378_ref_setup(dev, st); 721 if (ret) 722 return ret; 723 724 indio_dev->name = st->info->name; 725 indio_dev->modes = INDIO_DIRECT_MODE; 726 727 st->cnv_gpio = devm_gpiod_get(dev, "cnv", GPIOD_OUT_LOW); 728 if (IS_ERR(st->cnv_gpio)) 729 return dev_err_probe(dev, PTR_ERR(st->cnv_gpio), 730 "failed to get CNV GPIO"); 731 732 st->offload = devm_spi_offload_get(dev, spi, <c2378_offload_config); 733 ret = PTR_ERR_OR_ZERO(st->offload); 734 /* Fall back to low speed usage when no SPI offload is available. */ 735 if (ret == -ENODEV) { 736 indio_dev->info = <c2378_iio_info; 737 indio_dev->channels = st->info->chan; 738 indio_dev->num_channels = ARRAY_SIZE(st->info->chan); 739 740 ret = devm_iio_triggered_buffer_setup(dev, indio_dev, 741 iio_pollfunc_store_time, 742 ltc2378_trigger_handler, 743 NULL); 744 if (ret) 745 return ret; 746 } else if (ret) { 747 return dev_err_probe(dev, ret, "failed to get offload\n"); 748 } else { 749 indio_dev->info = <c2378_offload_iio_info; 750 indio_dev->channels = &st->info->offload_chan; 751 indio_dev->num_channels = 1; 752 ret = ltc2378_spi_offload_setup(indio_dev, st); 753 if (ret) 754 return dev_err_probe(dev, ret, 755 "failed to setup SPI offload\n"); 756 757 ret = ltc2378_pwm_get(st); 758 if (ret) 759 return dev_err_probe(dev, ret, "failed to get PWM\n"); 760 761 st->sample_freq_range[0] = 1; /* min */ 762 st->sample_freq_range[1] = 1; /* step */ 763 st->sample_freq_range[2] = st->info->max_sample_rate_Hz; /* max */ 764 765 /* 766 * Start with a slower sampling rate so there is some room for 767 * adjusting the sample averaging and the sampling frequency 768 * without hitting the maximum conversion rate. 769 */ 770 ret = ltc2378_update_conversion_rate(st, st->info->max_sample_rate_Hz >> 4); 771 if (ret) 772 return dev_err_probe(dev, ret, 773 "failed to set offload samp freq\n"); 774 775 ret = ltc2378_prepare_offload_message(&spi->dev, st); 776 if (ret) 777 return dev_err_probe(dev, ret, "failed to optimize SPI message\n"); 778 779 /* 780 * Set single-read transfer bits_per_word so the SPI subsystem 781 * rearranges data to CPU endianness, enabling us to reuse 782 * offload_chan specifications for single-shot reads. 783 */ 784 st->xfer.bits_per_word = st->info->offload_chan.scan_type.realbits; 785 } 786 787 st->xfer.rx_buf = &st->scan.data; 788 st->xfer.len = spi_bpw_to_bytes(indio_dev->channels[0].scan_type.realbits); 789 790 return devm_iio_device_register(&spi->dev, indio_dev); 791 } 792 793 static const struct of_device_id ltc2378_of_match[] = { 794 { .compatible = "adi,ltc2338-18", .data = <c2338_18_chip_info }, 795 { .compatible = "adi,ltc2364-16", .data = <c2364_16_chip_info }, 796 { .compatible = "adi,ltc2364-18", .data = <c2364_18_chip_info }, 797 { .compatible = "adi,ltc2367-16", .data = <c2367_16_chip_info }, 798 { .compatible = "adi,ltc2367-18", .data = <c2367_18_chip_info }, 799 { .compatible = "adi,ltc2368-16", .data = <c2368_16_chip_info }, 800 { .compatible = "adi,ltc2368-18", .data = <c2368_18_chip_info }, 801 { .compatible = "adi,ltc2369-18", .data = <c2369_18_chip_info }, 802 { .compatible = "adi,ltc2370-16", .data = <c2370_16_chip_info }, 803 { .compatible = "adi,ltc2376-16", .data = <c2376_16_chip_info }, 804 { .compatible = "adi,ltc2376-18", .data = <c2376_18_chip_info }, 805 { .compatible = "adi,ltc2376-20", .data = <c2376_20_chip_info }, 806 { .compatible = "adi,ltc2377-16", .data = <c2377_16_chip_info }, 807 { .compatible = "adi,ltc2377-18", .data = <c2377_18_chip_info }, 808 { .compatible = "adi,ltc2377-20", .data = <c2377_20_chip_info }, 809 { .compatible = "adi,ltc2378-16", .data = <c2378_16_chip_info }, 810 { .compatible = "adi,ltc2378-18", .data = <c2378_18_chip_info }, 811 { .compatible = "adi,ltc2378-20", .data = <c2378_20_chip_info }, 812 { .compatible = "adi,ltc2379-18", .data = <c2379_18_chip_info }, 813 { .compatible = "adi,ltc2380-16", .data = <c2380_16_chip_info }, 814 { } 815 }; 816 MODULE_DEVICE_TABLE(of, ltc2378_of_match); 817 818 static const struct spi_device_id ltc2378_spi_id[] = { 819 { .name = "ltc2338-18", .driver_data = (kernel_ulong_t)<c2338_18_chip_info }, 820 { .name = "ltc2364-16", .driver_data = (kernel_ulong_t)<c2364_16_chip_info }, 821 { .name = "ltc2364-18", .driver_data = (kernel_ulong_t)<c2364_18_chip_info }, 822 { .name = "ltc2367-16", .driver_data = (kernel_ulong_t)<c2367_16_chip_info }, 823 { .name = "ltc2367-18", .driver_data = (kernel_ulong_t)<c2367_18_chip_info }, 824 { .name = "ltc2368-16", .driver_data = (kernel_ulong_t)<c2368_16_chip_info }, 825 { .name = "ltc2368-18", .driver_data = (kernel_ulong_t)<c2368_18_chip_info }, 826 { .name = "ltc2369-18", .driver_data = (kernel_ulong_t)<c2369_18_chip_info }, 827 { .name = "ltc2370-16", .driver_data = (kernel_ulong_t)<c2370_16_chip_info }, 828 { .name = "ltc2376-16", .driver_data = (kernel_ulong_t)<c2376_16_chip_info }, 829 { .name = "ltc2376-18", .driver_data = (kernel_ulong_t)<c2376_18_chip_info }, 830 { .name = "ltc2376-20", .driver_data = (kernel_ulong_t)<c2376_20_chip_info }, 831 { .name = "ltc2377-16", .driver_data = (kernel_ulong_t)<c2377_16_chip_info }, 832 { .name = "ltc2377-18", .driver_data = (kernel_ulong_t)<c2377_18_chip_info }, 833 { .name = "ltc2377-20", .driver_data = (kernel_ulong_t)<c2377_20_chip_info }, 834 { .name = "ltc2378-16", .driver_data = (kernel_ulong_t)<c2378_16_chip_info }, 835 { .name = "ltc2378-18", .driver_data = (kernel_ulong_t)<c2378_18_chip_info }, 836 { .name = "ltc2378-20", .driver_data = (kernel_ulong_t)<c2378_20_chip_info }, 837 { .name = "ltc2379-18", .driver_data = (kernel_ulong_t)<c2379_18_chip_info }, 838 { .name = "ltc2380-16", .driver_data = (kernel_ulong_t)<c2380_16_chip_info }, 839 { } 840 }; 841 MODULE_DEVICE_TABLE(spi, ltc2378_spi_id); 842 843 static struct spi_driver ltc2378_driver = { 844 .driver = { 845 .name = "ltc2378", 846 .of_match_table = ltc2378_of_match 847 }, 848 .probe = ltc2378_probe, 849 .id_table = ltc2378_spi_id, 850 }; 851 module_spi_driver(ltc2378_driver); 852 853 MODULE_AUTHOR("Marcelo Schmitt <marcelo.schmitt@analog.com>"); 854 MODULE_DESCRIPTION("Analog Devices LTC2378 ADC series driver"); 855 MODULE_LICENSE("GPL"); 856 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 857 MODULE_IMPORT_NS("SPI_OFFLOAD"); 858