1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2024-2026 Analog Devices, Inc. 4 * Author: Radu Sabau <radu.sabau@analog.com> 5 */ 6 #include <linux/array_size.h> 7 #include <linux/bitfield.h> 8 #include <linux/bitmap.h> 9 #include <linux/cleanup.h> 10 #include <linux/delay.h> 11 #include <linux/dev_printk.h> 12 #include <linux/device/devres.h> 13 #include <linux/dmaengine.h> 14 #include <linux/err.h> 15 #include <linux/interrupt.h> 16 #include <linux/kstrtox.h> 17 #include <linux/limits.h> 18 #include <linux/math.h> 19 #include <linux/module.h> 20 #include <linux/mod_devicetable.h> 21 #include <linux/property.h> 22 #include <linux/pwm.h> 23 #include <linux/regmap.h> 24 #include <linux/regulator/consumer.h> 25 #include <linux/reset.h> 26 #include <linux/string.h> 27 #include <linux/spi/spi.h> 28 #include <linux/spi/offload/consumer.h> 29 #include <linux/spi/offload/provider.h> 30 #include <linux/types.h> 31 #include <linux/units.h> 32 #include <linux/unaligned.h> 33 34 #include <linux/iio/buffer.h> 35 #include <linux/iio/buffer-dma.h> 36 #include <linux/iio/buffer-dmaengine.h> 37 #include <linux/iio/iio.h> 38 #include <linux/iio/sysfs.h> 39 #include <linux/iio/trigger.h> 40 #include <linux/iio/triggered_buffer.h> 41 #include <linux/iio/trigger_consumer.h> 42 43 #define AD4691_VREF_uV_MIN 2400000 44 #define AD4691_VREF_uV_MAX 5250000 45 #define AD4691_VREF_2P5_uV_MAX 2750000 46 #define AD4691_VREF_3P0_uV_MAX 3250000 47 #define AD4691_VREF_3P3_uV_MAX 3750000 48 #define AD4691_VREF_4P096_uV_MAX 4500000 49 50 #define AD4691_CNV_DUTY_CYCLE_NS 380 51 #define AD4691_CNV_HIGH_TIME_NS 430 52 /* 53 * Conservative default for the manual offload periodic trigger. Low enough 54 * to work safely out of the box across all OSR and channel count combinations. 55 */ 56 #define AD4691_OFFLOAD_INITIAL_TRIGGER_HZ (100 * HZ_PER_KHZ) 57 58 #define AD4691_SPI_CONFIG_A_REG 0x000 59 #define AD4691_SW_RESET (BIT(7) | BIT(0)) 60 61 #define AD4691_STATUS_REG 0x014 62 #define AD4691_CLAMP_STATUS1_REG 0x01A 63 #define AD4691_CLAMP_STATUS2_REG 0x01B 64 #define AD4691_DEVICE_SETUP 0x020 65 #define AD4691_MANUAL_MODE BIT(2) 66 #define AD4691_LDO_EN BIT(4) 67 #define AD4691_REF_CTRL 0x021 68 #define AD4691_REF_CTRL_MASK GENMASK(4, 2) 69 #define AD4691_REFBUF_EN BIT(0) 70 #define AD4691_OSC_FREQ_REG 0x023 71 #define AD4691_OSC_FREQ_MASK GENMASK(3, 0) 72 #define AD4691_STD_SEQ_CONFIG 0x025 73 #define AD4691_SEQ_ALL_CHANNELS_OFF 0x00 74 #define AD4691_SPARE_CONTROL 0x02A 75 76 #define AD4691_MAX_CHANNELS 16 77 78 #define AD4691_NOOP 0x00 79 #define AD4691_ADC_CHAN(ch) ((0x10 + (ch)) << 3) 80 #define AD4691_EXIT_COMMAND 0x5000 81 82 #define AD4691_OSC_EN_REG 0x180 83 #define AD4691_STATE_RESET_REG 0x181 84 #define AD4691_STATE_RESET_ALL BIT(0) 85 #define AD4691_ADC_SETUP 0x182 86 #define AD4691_ADC_MODE_MASK GENMASK(1, 0) 87 #define AD4691_CNV_BURST_MODE 0x01 88 #define AD4691_AUTONOMOUS_MODE 0x02 89 /* 90 * ACC_MASK_REG covers both mask bytes via ADDR_DESCENDING SPI: writing a 91 * 16-bit BE value to 0x185 auto-decrements to 0x184 for the second byte. 92 */ 93 #define AD4691_ACC_MASK_REG 0x185 94 #define AD4691_ACC_DEPTH_IN(n) (0x186 + (n)) 95 #define AD4691_GPIO_MODE1_REG 0x196 96 #define AD4691_GPIO_MODE2_REG 0x197 97 #define AD4691_GP_MODE_MASK GENMASK(3, 0) 98 #define AD4691_GP_MODE_DATA_READY 0x06 99 #define AD4691_GPIO_READ 0x1A0 100 #define AD4691_ACC_STATUS_FULL1_REG 0x1B0 101 #define AD4691_ACC_STATUS_FULL2_REG 0x1B1 102 #define AD4691_ACC_STATUS_OVERRUN1_REG 0x1B2 103 #define AD4691_ACC_STATUS_OVERRUN2_REG 0x1B3 104 #define AD4691_ACC_STATUS_SAT1_REG 0x1B4 105 #define AD4691_ACC_STATUS_SAT2_REG 0x1BE 106 #define AD4691_ACC_SAT_OVR_REG(n) (0x1C0 + (n)) 107 #define AD4691_AVG_IN(n) (0x201 + (2 * (n))) 108 #define AD4691_AVG_STS_IN(n) (0x222 + (3 * (n))) 109 #define AD4691_ACC_IN(n) (0x252 + (3 * (n))) 110 #define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n))) 111 112 113 static const char * const ad4691_supplies[] = { "avdd", "vio" }; 114 115 enum ad4691_ref_ctrl { 116 AD4691_VREF_2P5, 117 AD4691_VREF_3P0, 118 AD4691_VREF_3P3, 119 AD4691_VREF_4P096, 120 AD4691_VREF_5P0 121 }; 122 123 struct ad4691_channel_info { 124 const struct iio_chan_spec *channels __counted_by_ptr(num_channels); 125 const struct iio_chan_spec *manual_channels __counted_by_ptr(num_channels); 126 unsigned int num_channels; 127 }; 128 129 struct ad4691_chip_info { 130 const char *name; 131 unsigned int max_rate; 132 const struct ad4691_channel_info *sw_info; 133 const struct ad4691_channel_info *offload_info; 134 }; 135 136 /* CNV burst mode channel — exposes oversampling ratio. */ 137 #define AD4691_CHANNEL(ch) \ 138 { \ 139 .type = IIO_VOLTAGE, \ 140 .indexed = 1, \ 141 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 142 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \ 143 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 144 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 145 .info_mask_shared_by_all_available = \ 146 BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 147 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 148 .channel = ch, \ 149 .scan_index = ch, \ 150 .scan_type = { \ 151 .format = 'u', \ 152 .realbits = 16, \ 153 .storagebits = 16, \ 154 .endianness = IIO_BE, \ 155 }, \ 156 } 157 158 /* 159 * Manual mode channel — no oversampling ratio attribute. OSR is not 160 * supported in manual mode; ACC_DEPTH_IN is not configured during manual 161 * buffer enable. 162 */ 163 #define AD4691_MANUAL_CHANNEL(ch) \ 164 { \ 165 .type = IIO_VOLTAGE, \ 166 .indexed = 1, \ 167 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 168 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \ 169 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 170 .info_mask_shared_by_all_available = \ 171 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 172 .channel = ch, \ 173 .scan_index = ch, \ 174 .scan_type = { \ 175 .format = 'u', \ 176 .realbits = 16, \ 177 .storagebits = 16, \ 178 .endianness = IIO_BE, \ 179 }, \ 180 } 181 182 /* 183 * Offload path (bits_per_word=16): the SPI Engine assembles received 184 * bits into native 16-bit words before DMA, so samples are in 185 * CPU-native byte order (IIO_CPU). storagebits=16 matches the 16-bit 186 * DMA word size. 187 * 188 * CNV burst offload configures ACC_DEPTH_IN per channel, so the 189 * oversampling_ratio attribute is exposed. Manual offload does not; 190 * use AD4691_OFFLOAD_MANUAL_CHANNEL for that path. 191 */ 192 #define AD4691_OFFLOAD_CHANNEL(ch) \ 193 { \ 194 .type = IIO_VOLTAGE, \ 195 .indexed = 1, \ 196 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 197 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \ 198 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 199 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 200 .info_mask_shared_by_all_available = \ 201 BIT(IIO_CHAN_INFO_SAMP_FREQ) \ 202 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \ 203 .channel = ch, \ 204 .scan_index = ch, \ 205 .scan_type = { \ 206 .format = 'u', \ 207 .realbits = 16, \ 208 .storagebits = 16, \ 209 }, \ 210 } 211 212 /* Manual offload — same IIO_CPU layout but no oversampling_ratio attribute. */ 213 #define AD4691_OFFLOAD_MANUAL_CHANNEL(ch) \ 214 { \ 215 .type = IIO_VOLTAGE, \ 216 .indexed = 1, \ 217 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \ 218 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \ 219 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 220 .info_mask_shared_by_all_available = \ 221 BIT(IIO_CHAN_INFO_SAMP_FREQ), \ 222 .channel = ch, \ 223 .scan_index = ch, \ 224 .scan_type = { \ 225 .format = 'u', \ 226 .realbits = 16, \ 227 .storagebits = 16, \ 228 }, \ 229 } 230 231 static const struct iio_chan_spec ad4691_channels[] = { 232 AD4691_CHANNEL(0), 233 AD4691_CHANNEL(1), 234 AD4691_CHANNEL(2), 235 AD4691_CHANNEL(3), 236 AD4691_CHANNEL(4), 237 AD4691_CHANNEL(5), 238 AD4691_CHANNEL(6), 239 AD4691_CHANNEL(7), 240 AD4691_CHANNEL(8), 241 AD4691_CHANNEL(9), 242 AD4691_CHANNEL(10), 243 AD4691_CHANNEL(11), 244 AD4691_CHANNEL(12), 245 AD4691_CHANNEL(13), 246 AD4691_CHANNEL(14), 247 AD4691_CHANNEL(15), 248 IIO_CHAN_SOFT_TIMESTAMP(16), 249 }; 250 251 static const struct iio_chan_spec ad4693_channels[] = { 252 AD4691_CHANNEL(0), 253 AD4691_CHANNEL(1), 254 AD4691_CHANNEL(2), 255 AD4691_CHANNEL(3), 256 AD4691_CHANNEL(4), 257 AD4691_CHANNEL(5), 258 AD4691_CHANNEL(6), 259 AD4691_CHANNEL(7), 260 IIO_CHAN_SOFT_TIMESTAMP(8), 261 }; 262 263 /* 264 * Offload channel arrays: no IIO_CHAN_SOFT_TIMESTAMP because DMA delivers 265 * data directly to userspace without a software timestamp. 266 */ 267 static const struct iio_chan_spec ad4691_offload_channels[] = { 268 AD4691_OFFLOAD_CHANNEL(0), 269 AD4691_OFFLOAD_CHANNEL(1), 270 AD4691_OFFLOAD_CHANNEL(2), 271 AD4691_OFFLOAD_CHANNEL(3), 272 AD4691_OFFLOAD_CHANNEL(4), 273 AD4691_OFFLOAD_CHANNEL(5), 274 AD4691_OFFLOAD_CHANNEL(6), 275 AD4691_OFFLOAD_CHANNEL(7), 276 AD4691_OFFLOAD_CHANNEL(8), 277 AD4691_OFFLOAD_CHANNEL(9), 278 AD4691_OFFLOAD_CHANNEL(10), 279 AD4691_OFFLOAD_CHANNEL(11), 280 AD4691_OFFLOAD_CHANNEL(12), 281 AD4691_OFFLOAD_CHANNEL(13), 282 AD4691_OFFLOAD_CHANNEL(14), 283 AD4691_OFFLOAD_CHANNEL(15), 284 }; 285 286 static const struct iio_chan_spec ad4693_offload_channels[] = { 287 AD4691_OFFLOAD_CHANNEL(0), 288 AD4691_OFFLOAD_CHANNEL(1), 289 AD4691_OFFLOAD_CHANNEL(2), 290 AD4691_OFFLOAD_CHANNEL(3), 291 AD4691_OFFLOAD_CHANNEL(4), 292 AD4691_OFFLOAD_CHANNEL(5), 293 AD4691_OFFLOAD_CHANNEL(6), 294 AD4691_OFFLOAD_CHANNEL(7), 295 }; 296 297 static const struct iio_chan_spec ad4691_manual_channels[] = { 298 AD4691_MANUAL_CHANNEL(0), 299 AD4691_MANUAL_CHANNEL(1), 300 AD4691_MANUAL_CHANNEL(2), 301 AD4691_MANUAL_CHANNEL(3), 302 AD4691_MANUAL_CHANNEL(4), 303 AD4691_MANUAL_CHANNEL(5), 304 AD4691_MANUAL_CHANNEL(6), 305 AD4691_MANUAL_CHANNEL(7), 306 AD4691_MANUAL_CHANNEL(8), 307 AD4691_MANUAL_CHANNEL(9), 308 AD4691_MANUAL_CHANNEL(10), 309 AD4691_MANUAL_CHANNEL(11), 310 AD4691_MANUAL_CHANNEL(12), 311 AD4691_MANUAL_CHANNEL(13), 312 AD4691_MANUAL_CHANNEL(14), 313 AD4691_MANUAL_CHANNEL(15), 314 IIO_CHAN_SOFT_TIMESTAMP(16), 315 }; 316 317 static const struct iio_chan_spec ad4693_manual_channels[] = { 318 AD4691_MANUAL_CHANNEL(0), 319 AD4691_MANUAL_CHANNEL(1), 320 AD4691_MANUAL_CHANNEL(2), 321 AD4691_MANUAL_CHANNEL(3), 322 AD4691_MANUAL_CHANNEL(4), 323 AD4691_MANUAL_CHANNEL(5), 324 AD4691_MANUAL_CHANNEL(6), 325 AD4691_MANUAL_CHANNEL(7), 326 IIO_CHAN_SOFT_TIMESTAMP(8), 327 }; 328 329 static const struct iio_chan_spec ad4691_offload_manual_channels[] = { 330 AD4691_OFFLOAD_MANUAL_CHANNEL(0), 331 AD4691_OFFLOAD_MANUAL_CHANNEL(1), 332 AD4691_OFFLOAD_MANUAL_CHANNEL(2), 333 AD4691_OFFLOAD_MANUAL_CHANNEL(3), 334 AD4691_OFFLOAD_MANUAL_CHANNEL(4), 335 AD4691_OFFLOAD_MANUAL_CHANNEL(5), 336 AD4691_OFFLOAD_MANUAL_CHANNEL(6), 337 AD4691_OFFLOAD_MANUAL_CHANNEL(7), 338 AD4691_OFFLOAD_MANUAL_CHANNEL(8), 339 AD4691_OFFLOAD_MANUAL_CHANNEL(9), 340 AD4691_OFFLOAD_MANUAL_CHANNEL(10), 341 AD4691_OFFLOAD_MANUAL_CHANNEL(11), 342 AD4691_OFFLOAD_MANUAL_CHANNEL(12), 343 AD4691_OFFLOAD_MANUAL_CHANNEL(13), 344 AD4691_OFFLOAD_MANUAL_CHANNEL(14), 345 AD4691_OFFLOAD_MANUAL_CHANNEL(15), 346 }; 347 348 static const struct iio_chan_spec ad4693_offload_manual_channels[] = { 349 AD4691_OFFLOAD_MANUAL_CHANNEL(0), 350 AD4691_OFFLOAD_MANUAL_CHANNEL(1), 351 AD4691_OFFLOAD_MANUAL_CHANNEL(2), 352 AD4691_OFFLOAD_MANUAL_CHANNEL(3), 353 AD4691_OFFLOAD_MANUAL_CHANNEL(4), 354 AD4691_OFFLOAD_MANUAL_CHANNEL(5), 355 AD4691_OFFLOAD_MANUAL_CHANNEL(6), 356 AD4691_OFFLOAD_MANUAL_CHANNEL(7), 357 }; 358 359 static const int ad4691_oversampling_ratios[] = { 1, 2, 4, 8, 16, 32 }; 360 361 static const struct ad4691_channel_info ad4691_sw_info = { 362 .channels = ad4691_channels, 363 .manual_channels = ad4691_manual_channels, 364 .num_channels = ARRAY_SIZE(ad4691_channels), 365 }; 366 367 static const struct ad4691_channel_info ad4693_sw_info = { 368 .channels = ad4693_channels, 369 .manual_channels = ad4693_manual_channels, 370 .num_channels = ARRAY_SIZE(ad4693_channels), 371 }; 372 373 static const struct ad4691_channel_info ad4691_offload_info = { 374 .channels = ad4691_offload_channels, 375 .manual_channels = ad4691_offload_manual_channels, 376 .num_channels = ARRAY_SIZE(ad4691_offload_channels), 377 }; 378 379 static const struct ad4691_channel_info ad4693_offload_info = { 380 .channels = ad4693_offload_channels, 381 .manual_channels = ad4693_offload_manual_channels, 382 .num_channels = ARRAY_SIZE(ad4693_offload_channels), 383 }; 384 385 /* 386 * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] value. 387 * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support 388 * up to 500 kHz and use index 1 as their highest valid rate. 389 */ 390 static const int ad4691_osc_freqs_Hz[] = { 391 [0x0] = 1000000, 392 [0x1] = 500000, 393 [0x2] = 400000, 394 [0x3] = 250000, 395 [0x4] = 200000, 396 [0x5] = 167000, 397 [0x6] = 133000, 398 [0x7] = 125000, 399 [0x8] = 100000, 400 [0x9] = 50000, 401 [0xA] = 25000, 402 [0xB] = 12500, 403 [0xC] = 10000, 404 [0xD] = 5000, 405 [0xE] = 2500, 406 [0xF] = 1250, 407 }; 408 409 static const char * const ad4691_gp_names[] = { "gp0", "gp1", "gp2", "gp3" }; 410 411 static const struct ad4691_chip_info ad4691_chip_info = { 412 .name = "ad4691", 413 .max_rate = 500 * HZ_PER_KHZ, 414 .sw_info = &ad4691_sw_info, 415 .offload_info = &ad4691_offload_info, 416 }; 417 418 static const struct ad4691_chip_info ad4692_chip_info = { 419 .name = "ad4692", 420 .max_rate = 1 * HZ_PER_MHZ, 421 .sw_info = &ad4691_sw_info, 422 .offload_info = &ad4691_offload_info, 423 }; 424 425 static const struct ad4691_chip_info ad4693_chip_info = { 426 .name = "ad4693", 427 .max_rate = 500 * HZ_PER_KHZ, 428 .sw_info = &ad4693_sw_info, 429 .offload_info = &ad4693_offload_info, 430 }; 431 432 static const struct ad4691_chip_info ad4694_chip_info = { 433 .name = "ad4694", 434 .max_rate = 1 * HZ_PER_MHZ, 435 .sw_info = &ad4693_sw_info, 436 .offload_info = &ad4693_offload_info, 437 }; 438 439 struct ad4691_state { 440 const struct ad4691_chip_info *info; 441 struct regmap *regmap; 442 struct spi_device *spi; 443 444 struct pwm_device *conv_trigger; 445 int irq; 446 int vref_uV; 447 u32 cnv_period_ns; 448 /* 449 * Snapped oscillator frequency (Hz) shared by all channels. Set when 450 * sampling_frequency or oversampling_ratio is written; written to 451 * OSC_FREQ_REG at buffer enable and single-shot time so both attributes 452 * can be set in any order. Reading in_voltage_sampling_frequency 453 * returns target_osc_freq_Hz / osr — the effective rate given the 454 * shared oversampling ratio. 455 */ 456 u32 target_osc_freq_Hz; 457 /* Shared oversampling ratio across all channels; always 1 in manual mode. */ 458 unsigned int osr; 459 /* 460 * Precomputed effective-rate lists, one row per entry in 461 * ad4691_oversampling_ratios[]. Populated at probe; read_avail picks 462 * the row for the current shared OSR. The tables are stable after 463 * probe so returning a pointer into them from read_avail is race-free. 464 */ 465 int samp_freq_avail[ARRAY_SIZE(ad4691_oversampling_ratios)][ARRAY_SIZE(ad4691_osc_freqs_Hz)]; 466 int samp_freq_avail_len[ARRAY_SIZE(ad4691_oversampling_ratios)]; 467 468 bool manual_mode; 469 bool irq_enabled; 470 bool refbuf_en; 471 bool ldo_en; 472 /* 473 * Synchronize access to members of the driver state, and ensure 474 * atomicity of consecutive SPI operations. 475 */ 476 struct mutex lock; 477 /* NULL when no SPI offload hardware is present. */ 478 struct spi_offload *offload; 479 struct spi_offload_trigger *offload_trigger; 480 u64 trigger_hz; 481 /* 482 * Per-buffer-enable lifetime resources: 483 * Manual Mode - a pre-built SPI message that clocks out N+1 484 * transfers in one go. 485 * CNV Burst Mode - a pre-built SPI message that clocks out 2*N 486 * transfers in one go. 487 */ 488 struct spi_message scan_msg; 489 /* 490 * max 16 + 1 NOOP (manual) or 2*16 + 1 state-reset (CNV burst). 491 */ 492 struct spi_transfer scan_xfers[34]; 493 /* 494 * CNV burst: 16 AVG_IN addresses = 16. Manual: 16 channel cmds + 495 * 1 NOOP = 17. Stored as native u16. The non-offload path fills slots 496 * with put_unaligned_be16() (bits_per_word=8, bytes go out in memory 497 * order). The offload path assigns native values directly 498 * (bits_per_word=bpw, SPI reads each slot as a native 16-bit word and 499 * shifts it out MSB-first). 500 */ 501 u16 scan_tx[17] __aligned(IIO_DMA_MINALIGN); 502 /* 503 * CNV burst state-reset: 4-byte write [addr_hi, addr_lo, 504 * STATE_RESET_ALL, OSC_EN=1]. CS is asserted throughout, so 505 * ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as a 506 * deliberate side-write, keeping the oscillator enabled. Shared 507 * with the offload path (mutually exclusive at probe). 508 */ 509 u8 scan_tx_reset[4] __aligned(IIO_DMA_MINALIGN); 510 /* 511 * Scan buffer: one BE16 slot per active channel, plus timestamp. 512 * DMA-aligned because scan_xfers point rx_buf directly into vals[]. 513 */ 514 IIO_DECLARE_DMA_BUFFER_WITH_TS(__be16, vals, 16); 515 }; 516 517 /* 518 * Configure the given GP pin (0-3) as DATA_READY output. 519 * GP0/GP1 → GPIO_MODE1_REG, GP2/GP3 → GPIO_MODE2_REG. 520 * Even pins occupy bits [3:0], odd pins bits [7:4]. 521 */ 522 static int ad4691_gpio_setup(struct ad4691_state *st, unsigned int gp_num) 523 { 524 unsigned int bit_off = gp_num % 2; 525 unsigned int reg_off = gp_num / 2; 526 unsigned int shift = 4 * bit_off; 527 528 return regmap_update_bits(st->regmap, 529 AD4691_GPIO_MODE1_REG + reg_off, 530 AD4691_GP_MODE_MASK << shift, 531 AD4691_GP_MODE_DATA_READY << shift); 532 } 533 534 static const struct spi_offload_config ad4691_offload_config = { 535 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER | 536 SPI_OFFLOAD_CAP_RX_STREAM_DMA, 537 }; 538 539 static bool ad4691_offload_trigger_match(struct spi_offload_trigger *trigger, 540 enum spi_offload_trigger_type type, 541 u64 *args, u32 nargs) 542 { 543 return type == SPI_OFFLOAD_TRIGGER_DATA_READY && nargs == 1 && args[0] <= 3; 544 } 545 546 static int ad4691_offload_trigger_request(struct spi_offload_trigger *trigger, 547 enum spi_offload_trigger_type type, 548 u64 *args, u32 nargs) 549 { 550 struct ad4691_state *st = spi_offload_trigger_get_priv(trigger); 551 552 if (nargs != 1 || args[0] > 3) 553 return -EINVAL; 554 555 return ad4691_gpio_setup(st, args[0]); 556 } 557 558 static int ad4691_offload_trigger_validate(struct spi_offload_trigger *trigger, 559 struct spi_offload_trigger_config *config) 560 { 561 if (config->type != SPI_OFFLOAD_TRIGGER_DATA_READY) 562 return -EINVAL; 563 564 return 0; 565 } 566 567 static const struct spi_offload_trigger_ops ad4691_offload_trigger_ops = { 568 .match = ad4691_offload_trigger_match, 569 .request = ad4691_offload_trigger_request, 570 .validate = ad4691_offload_trigger_validate, 571 }; 572 573 static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *val) 574 { 575 struct spi_device *spi = context; 576 u8 tx[2], rx[4]; 577 int ret; 578 579 /* Set bit 15 to mark the operation as READ. */ 580 put_unaligned_be16(0x8000 | reg, tx); 581 582 switch (reg) { 583 case 0 ... AD4691_OSC_FREQ_REG: 584 case AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1: 585 case AD4691_ACC_MASK_REG + 1 ... AD4691_ACC_SAT_OVR_REG(15): 586 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 1); 587 if (ret) 588 return ret; 589 *val = rx[0]; 590 return 0; 591 case AD4691_ACC_MASK_REG: 592 case AD4691_STD_SEQ_CONFIG: 593 case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): 594 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 2); 595 if (ret) 596 return ret; 597 *val = get_unaligned_be16(rx); 598 return 0; 599 case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): 600 case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): 601 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 3); 602 if (ret) 603 return ret; 604 *val = get_unaligned_be24(rx); 605 return 0; 606 case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): 607 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 4); 608 if (ret) 609 return ret; 610 *val = get_unaligned_be32(rx); 611 return 0; 612 default: 613 return -EINVAL; 614 } 615 } 616 617 static int ad4691_reg_write(void *context, unsigned int reg, unsigned int val) 618 { 619 struct spi_device *spi = context; 620 u8 tx[4]; 621 622 put_unaligned_be16(reg, tx); 623 624 switch (reg) { 625 case 0 ... AD4691_OSC_FREQ_REG: 626 case AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1: 627 case AD4691_ACC_MASK_REG + 1 ... AD4691_GPIO_MODE2_REG: 628 if (val > U8_MAX) 629 return -EINVAL; 630 tx[2] = val; 631 return spi_write_then_read(spi, tx, 3, NULL, 0); 632 case AD4691_ACC_MASK_REG: 633 case AD4691_STD_SEQ_CONFIG: 634 if (val > U16_MAX) 635 return -EINVAL; 636 put_unaligned_be16(val, &tx[2]); 637 return spi_write_then_read(spi, tx, 4, NULL, 0); 638 default: 639 return -EINVAL; 640 } 641 } 642 643 static bool ad4691_volatile_reg(struct device *dev, unsigned int reg) 644 { 645 switch (reg) { 646 case AD4691_STATUS_REG: 647 case AD4691_CLAMP_STATUS1_REG: 648 case AD4691_CLAMP_STATUS2_REG: 649 case AD4691_GPIO_READ: 650 case AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG: 651 case AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15): 652 case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15): 653 case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15): 654 case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15): 655 case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15): 656 return true; 657 default: 658 return false; 659 } 660 } 661 662 static bool ad4691_readable_reg(struct device *dev, unsigned int reg) 663 { 664 switch (reg) { 665 case 0 ... AD4691_OSC_FREQ_REG: 666 case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15): 667 case AD4691_STD_SEQ_CONFIG: 668 return true; 669 default: 670 break; 671 } 672 673 /* 674 * Multi-byte result registers have non-unit strides; only the base 675 * address of each entry is a valid single-register read. 676 */ 677 if (reg >= AD4691_AVG_IN(0) && reg <= AD4691_AVG_IN(15)) 678 return (reg - AD4691_AVG_IN(0)) % 2 == 0; 679 if (reg >= AD4691_AVG_STS_IN(0) && reg <= AD4691_AVG_STS_IN(15)) 680 return (reg - AD4691_AVG_STS_IN(0)) % 3 == 0; 681 if (reg >= AD4691_ACC_IN(0) && reg <= AD4691_ACC_IN(15)) 682 return (reg - AD4691_ACC_IN(0)) % 3 == 0; 683 if (reg >= AD4691_ACC_STS_DATA(0) && reg <= AD4691_ACC_STS_DATA(15)) 684 return (reg - AD4691_ACC_STS_DATA(0)) % 4 == 0; 685 686 return false; 687 } 688 689 static bool ad4691_writeable_reg(struct device *dev, unsigned int reg) 690 { 691 switch (reg) { 692 case 0 ... AD4691_OSC_FREQ_REG: 693 case AD4691_STD_SEQ_CONFIG: 694 case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG: 695 return true; 696 default: 697 return false; 698 } 699 } 700 701 static const struct regmap_config ad4691_regmap_config = { 702 .reg_bits = 16, 703 .val_bits = 32, 704 .reg_read = ad4691_reg_read, 705 .reg_write = ad4691_reg_write, 706 .volatile_reg = ad4691_volatile_reg, 707 .readable_reg = ad4691_readable_reg, 708 .writeable_reg = ad4691_writeable_reg, 709 .max_register = AD4691_ACC_STS_DATA(15), 710 .cache_type = REGCACHE_MAPLE, 711 }; 712 713 /* 714 * Index 0 in ad4691_osc_freqs_Hz is 1 MHz — valid only for AD4692/AD4694 715 * (max_rate == 1 MHz). AD4691/AD4693 cap at 500 kHz so their valid range 716 * starts at index 1. 717 */ 718 static unsigned int ad4691_samp_freq_start(const struct ad4691_chip_info *info) 719 { 720 return (info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1; 721 } 722 723 /* 724 * Find the largest oscillator table entry that is both <= needed_osc and 725 * evenly divisible by osr (guaranteeing an integer effective rate on 726 * read-back). Returns 0 if no such entry exists in the chip's valid range. 727 */ 728 static unsigned int ad4691_find_osc_freq(struct ad4691_state *st, 729 unsigned int needed_osc, 730 unsigned int osr) 731 { 732 unsigned int start = ad4691_samp_freq_start(st->info); 733 734 for (unsigned int i = start; i < ARRAY_SIZE(ad4691_osc_freqs_Hz); i++) { 735 if ((unsigned int)ad4691_osc_freqs_Hz[i] > needed_osc) 736 continue; 737 if (ad4691_osc_freqs_Hz[i] % osr) 738 continue; 739 return ad4691_osc_freqs_Hz[i]; 740 } 741 return 0; 742 } 743 744 /* Write target_osc_freq_Hz to OSC_FREQ_REG. Called at use time. */ 745 static int ad4691_write_osc_freq(struct ad4691_state *st) 746 { 747 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_osc_freqs_Hz); i++) { 748 if (ad4691_osc_freqs_Hz[i] == st->target_osc_freq_Hz) 749 return regmap_write(st->regmap, AD4691_OSC_FREQ_REG, i); 750 } 751 return -EINVAL; 752 } 753 754 /* Return the index of osr in ad4691_oversampling_ratios[], defaulting to 0. */ 755 static unsigned int ad4691_osr_index(unsigned int osr) 756 { 757 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_oversampling_ratios) - 1; i++) { 758 if ((unsigned int)ad4691_oversampling_ratios[i] == osr) 759 return i; 760 } 761 return ARRAY_SIZE(ad4691_oversampling_ratios) - 1; 762 } 763 764 /* 765 * Precompute samp_freq_avail[][]: for each OSR value, list the oscillator 766 * table entries that divide evenly by that OSR, expressed as effective rates 767 * (osc_freq / osr). Called once at probe after st->info is set. 768 */ 769 static void ad4691_precompute_samp_freq_avail(struct ad4691_state *st) 770 { 771 unsigned int start = ad4691_samp_freq_start(st->info); 772 773 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_oversampling_ratios); i++) { 774 unsigned int osr = ad4691_oversampling_ratios[i]; 775 int n = 0; 776 777 for (unsigned int j = start; j < ARRAY_SIZE(ad4691_osc_freqs_Hz); j++) { 778 if (ad4691_osc_freqs_Hz[j] % osr) 779 continue; 780 st->samp_freq_avail[i][n++] = ad4691_osc_freqs_Hz[j] / osr; 781 } 782 st->samp_freq_avail_len[i] = n; 783 } 784 } 785 786 static int ad4691_set_sampling_freq(struct ad4691_state *st, int freq) 787 { 788 unsigned int osr, found; 789 790 /* 791 * Read osr under st->lock: osr and target_osc_freq_Hz are modified 792 * together under the lock; reading after acquiring it ensures we see 793 * a consistent snapshot with no concurrent write racing us. 794 */ 795 guard(mutex)(&st->lock); 796 osr = st->osr; 797 798 if (freq <= 0 || (unsigned int)freq > st->info->max_rate / osr) 799 return -EINVAL; 800 801 found = ad4691_find_osc_freq(st, (unsigned int)freq * osr, osr); 802 if (!found) 803 return -EINVAL; 804 805 /* 806 * Store the snapped oscillator frequency; OSC_FREQ_REG is written at 807 * buffer enable and single-shot time so that sampling_frequency and 808 * oversampling_ratio can be set in any order. 809 */ 810 st->target_osc_freq_Hz = found; 811 return 0; 812 } 813 814 static int ad4691_read_avail(struct iio_dev *indio_dev, 815 struct iio_chan_spec const *chan, 816 const int **vals, int *type, 817 int *length, long mask) 818 { 819 struct ad4691_state *st = iio_priv(indio_dev); 820 821 switch (mask) { 822 case IIO_CHAN_INFO_SAMP_FREQ: { 823 unsigned int osr_idx; 824 825 /* 826 * The precomputed tables are stable after probe; only the 827 * current OSR needs to be read under the lock to pick the 828 * right row atomically. 829 */ 830 guard(mutex)(&st->lock); 831 osr_idx = ad4691_osr_index(st->osr); 832 *vals = st->samp_freq_avail[osr_idx]; 833 *type = IIO_VAL_INT; 834 *length = st->samp_freq_avail_len[osr_idx]; 835 return IIO_AVAIL_LIST; 836 } 837 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: 838 *vals = ad4691_oversampling_ratios; 839 *type = IIO_VAL_INT; 840 *length = ARRAY_SIZE(ad4691_oversampling_ratios); 841 return IIO_AVAIL_LIST; 842 default: 843 return -EINVAL; 844 } 845 } 846 847 static int ad4691_single_shot_read(struct iio_dev *indio_dev, 848 struct iio_chan_spec const *chan, int *val) 849 { 850 struct ad4691_state *st = iio_priv(indio_dev); 851 unsigned int reg_val, period_us; 852 int ret; 853 854 guard(mutex)(&st->lock); 855 856 /* Use AUTONOMOUS mode for single-shot reads. */ 857 ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL); 858 if (ret) 859 return ret; 860 861 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, 862 BIT(chan->channel)); 863 if (ret) 864 return ret; 865 866 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG, 867 ~BIT(chan->channel) & GENMASK(15, 0)); 868 if (ret) 869 return ret; 870 871 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr); 872 if (ret) 873 return ret; 874 875 ret = ad4691_write_osc_freq(st); 876 if (ret) 877 return ret; 878 879 ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 1); 880 if (ret) 881 return ret; 882 883 /* 884 * Wait osr + 1 oscillator periods: osr for accumulation, +1 for the 885 * pipeline margin (one extra period ensures the final result is ready). 886 */ 887 period_us = DIV_ROUND_UP((st->osr + 1) * USEC_PER_SEC, 888 st->target_osc_freq_Hz); 889 fsleep(period_us); 890 891 ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 0); 892 if (ret) 893 return ret; 894 895 ret = regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val); 896 if (ret) 897 return ret; 898 899 *val = reg_val; 900 901 ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL); 902 if (ret) 903 return ret; 904 905 return IIO_VAL_INT; 906 } 907 908 static int ad4691_read_raw(struct iio_dev *indio_dev, 909 struct iio_chan_spec const *chan, int *val, 910 int *val2, long info) 911 { 912 struct ad4691_state *st = iio_priv(indio_dev); 913 914 switch (info) { 915 case IIO_CHAN_INFO_RAW: { 916 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); 917 if (IIO_DEV_ACQUIRE_FAILED(claim)) 918 return -EBUSY; 919 920 return ad4691_single_shot_read(indio_dev, chan, val); 921 } 922 case IIO_CHAN_INFO_SAMP_FREQ: { 923 /* 924 * Read target_osc_freq_Hz and osr under st->lock to get a 925 * consistent snapshot: write_raw for SAMP_FREQ or OSR modifies 926 * both fields under the lock, so a concurrent read without the 927 * lock could observe a new oscillator frequency with the old OSR. 928 */ 929 guard(mutex)(&st->lock); 930 *val = st->target_osc_freq_Hz / st->osr; 931 return IIO_VAL_INT; 932 } 933 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 934 guard(mutex)(&st->lock); 935 *val = st->osr; 936 return IIO_VAL_INT; 937 } 938 case IIO_CHAN_INFO_SCALE: 939 *val = st->vref_uV / (MICRO / MILLI); 940 *val2 = chan->scan_type.realbits; 941 return IIO_VAL_FRACTIONAL_LOG2; 942 default: 943 return -EINVAL; 944 } 945 } 946 947 static int ad4691_write_raw(struct iio_dev *indio_dev, 948 struct iio_chan_spec const *chan, 949 int val, int val2, long mask) 950 { 951 struct ad4691_state *st = iio_priv(indio_dev); 952 953 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); 954 if (IIO_DEV_ACQUIRE_FAILED(claim)) 955 return -EBUSY; 956 957 switch (mask) { 958 case IIO_CHAN_INFO_SAMP_FREQ: 959 return ad4691_set_sampling_freq(st, val); 960 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: { 961 unsigned int old_effective, found, osr_idx; 962 963 osr_idx = ad4691_osr_index(val); 964 if (ad4691_oversampling_ratios[osr_idx] != val) 965 return -EINVAL; 966 967 /* 968 * Hold st->lock while computing the new oscillator frequency 969 * and updating both target_osc_freq_Hz and osr atomically: 970 * read_raw for SAMP_FREQ reads both fields under the lock and 971 * must see a consistent pair (new osc ↔ new osr). 972 * 973 * Snap target_osc_freq_Hz to the largest table entry that is 974 * both <= old_effective * new_osr and evenly divisible by 975 * new_osr, preserving an integer read-back of 976 * in_voltage_sampling_frequency after the OSR change. 977 */ 978 guard(mutex)(&st->lock); 979 old_effective = st->target_osc_freq_Hz / st->osr; 980 found = ad4691_find_osc_freq(st, old_effective * (unsigned int)val, val); 981 if (!found) 982 return -EINVAL; 983 st->target_osc_freq_Hz = found; 984 st->osr = val; 985 return 0; 986 } 987 default: 988 return -EINVAL; 989 } 990 } 991 992 static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg, 993 unsigned int writeval, unsigned int *readval) 994 { 995 struct ad4691_state *st = iio_priv(indio_dev); 996 997 guard(mutex)(&st->lock); 998 999 if (readval) 1000 return regmap_read(st->regmap, reg, readval); 1001 1002 return regmap_write(st->regmap, reg, writeval); 1003 } 1004 1005 static int ad4691_set_pwm_freq(struct ad4691_state *st, unsigned int freq) 1006 { 1007 if (!freq) 1008 return -EINVAL; 1009 1010 st->cnv_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, freq); 1011 return 0; 1012 } 1013 1014 static int ad4691_sampling_enable(struct ad4691_state *st, bool enable) 1015 { 1016 struct pwm_state conv_state = { 1017 .period = st->cnv_period_ns, 1018 .duty_cycle = AD4691_CNV_DUTY_CYCLE_NS, 1019 .polarity = PWM_POLARITY_NORMAL, 1020 .enabled = enable, 1021 }; 1022 1023 return pwm_apply_might_sleep(st->conv_trigger, &conv_state); 1024 } 1025 1026 /* 1027 * ad4691_enter_conversion_mode - Switch the chip to its buffer conversion mode. 1028 * 1029 * Configures the ADC hardware registers for the mode selected at probe 1030 * (CNV_BURST or MANUAL). Called from buffer preenable before starting 1031 * sampling. The chip is in AUTONOMOUS mode during idle (for read_raw). 1032 */ 1033 static int ad4691_enter_conversion_mode(struct ad4691_state *st) 1034 { 1035 int ret; 1036 1037 if (st->manual_mode) 1038 return regmap_update_bits(st->regmap, AD4691_DEVICE_SETUP, 1039 AD4691_MANUAL_MODE, AD4691_MANUAL_MODE); 1040 1041 ret = ad4691_write_osc_freq(st); 1042 if (ret) 1043 return ret; 1044 1045 ret = regmap_update_bits(st->regmap, AD4691_ADC_SETUP, 1046 AD4691_ADC_MODE_MASK, AD4691_CNV_BURST_MODE); 1047 if (ret) 1048 return ret; 1049 1050 return regmap_write(st->regmap, AD4691_STATE_RESET_REG, 1051 AD4691_STATE_RESET_ALL); 1052 } 1053 1054 static int ad4691_transfer(struct ad4691_state *st, u16 cmd) 1055 { 1056 u8 buf[2]; 1057 1058 put_unaligned_be16(cmd, buf); 1059 1060 return spi_write_then_read(st->spi, buf, sizeof(buf), NULL, 0); 1061 } 1062 1063 /* 1064 * ad4691_exit_conversion_mode - Return the chip to AUTONOMOUS mode. 1065 * 1066 * Called from buffer postdisable to restore the chip to the 1067 * idle state used by read_raw. Clears the sequencer and resets state. 1068 */ 1069 static int ad4691_exit_conversion_mode(struct ad4691_state *st) 1070 { 1071 if (st->manual_mode) 1072 return ad4691_transfer(st, AD4691_EXIT_COMMAND); 1073 1074 return regmap_update_bits(st->regmap, AD4691_ADC_SETUP, 1075 AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE); 1076 } 1077 1078 static int ad4691_manual_buffer_preenable(struct iio_dev *indio_dev) 1079 { 1080 struct ad4691_state *st = iio_priv(indio_dev); 1081 unsigned int k, i; 1082 int ret; 1083 1084 memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); 1085 memset(st->scan_tx, 0, sizeof(st->scan_tx)); 1086 1087 spi_message_init(&st->scan_msg); 1088 1089 k = 0; 1090 iio_for_each_active_channel(indio_dev, i) { 1091 /* 1092 * Channel-select command occupies the first (high) byte of the 1093 * 16-bit DIN frame; the second byte is a don't-care zero pad. 1094 * put_unaligned_be16() writes [cmd, 0x00] in memory so the 1095 * SPI controller sends the command byte first on the wire. 1096 */ 1097 put_unaligned_be16((u16)(AD4691_ADC_CHAN(i) << 8), &st->scan_tx[k]); 1098 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; 1099 /* 1100 * The pipeline means xfer[0] receives the residual from the 1101 * previous sequence, not a valid sample. Discard it (rx_buf=NULL) 1102 * to avoid aliasing vals[0] across two concurrent DMA mappings. 1103 * xfer[1] (or the NOOP when only one channel is active) writes 1104 * the real ch[0] result to vals[0]. Subsequent transfers write 1105 * into vals[k-1] so each result lands at the next dense slot. 1106 */ 1107 st->scan_xfers[k].rx_buf = (k == 0) ? NULL : &st->vals[k - 1]; 1108 st->scan_xfers[k].len = sizeof(*st->scan_tx); 1109 st->scan_xfers[k].cs_change = 1; 1110 st->scan_xfers[k].cs_change_delay.value = AD4691_CNV_HIGH_TIME_NS; 1111 st->scan_xfers[k].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1112 spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg); 1113 k++; 1114 } 1115 1116 /* Final NOOP transfer retrieves the last channel's result. */ 1117 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; /* scan_tx[k] == 0 == NOOP */ 1118 st->scan_xfers[k].rx_buf = &st->vals[k - 1]; 1119 st->scan_xfers[k].len = sizeof(*st->scan_tx); 1120 spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg); 1121 1122 ret = spi_optimize_message(st->spi, &st->scan_msg); 1123 if (ret) 1124 return ret; 1125 1126 ret = ad4691_enter_conversion_mode(st); 1127 if (ret) { 1128 spi_unoptimize_message(&st->scan_msg); 1129 return ret; 1130 } 1131 1132 return 0; 1133 } 1134 1135 static int ad4691_manual_buffer_postdisable(struct iio_dev *indio_dev) 1136 { 1137 struct ad4691_state *st = iio_priv(indio_dev); 1138 int ret; 1139 1140 ret = ad4691_exit_conversion_mode(st); 1141 spi_unoptimize_message(&st->scan_msg); 1142 return ret; 1143 } 1144 1145 static const struct iio_buffer_setup_ops ad4691_manual_buffer_setup_ops = { 1146 .preenable = ad4691_manual_buffer_preenable, 1147 .postdisable = ad4691_manual_buffer_postdisable, 1148 }; 1149 1150 static int ad4691_cnv_burst_buffer_preenable(struct iio_dev *indio_dev) 1151 { 1152 struct ad4691_state *st = iio_priv(indio_dev); 1153 unsigned int acc_mask, std_seq_config; 1154 unsigned int k, i; 1155 int ret; 1156 1157 memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); 1158 memset(st->scan_tx, 0, sizeof(st->scan_tx)); 1159 1160 spi_message_init(&st->scan_msg); 1161 1162 /* 1163 * Each AVG_IN read needs two transfers: a 2-byte address write phase 1164 * followed by a 2-byte data read phase. CS toggles between channels 1165 * (cs_change=1 on the read phase of all but the last channel). 1166 */ 1167 k = 0; 1168 iio_for_each_active_channel(indio_dev, i) { 1169 put_unaligned_be16(0x8000 | AD4691_AVG_IN(i), &st->scan_tx[k]); 1170 st->scan_xfers[2 * k].tx_buf = &st->scan_tx[k]; 1171 st->scan_xfers[2 * k].len = sizeof(*st->scan_tx); 1172 spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg); 1173 st->scan_xfers[2 * k + 1].rx_buf = &st->vals[k]; 1174 st->scan_xfers[2 * k + 1].len = sizeof(*st->scan_tx); 1175 st->scan_xfers[2 * k + 1].cs_change = 1; 1176 spi_message_add_tail(&st->scan_xfers[2 * k + 1], &st->scan_msg); 1177 k++; 1178 } 1179 1180 /* 1181 * Append a 4-byte state-reset transfer [addr_hi, addr_lo, 1182 * STATE_RESET_ALL, OSC_EN=1]. CS is asserted throughout, so 1183 * ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as a 1184 * deliberate side-write, keeping the oscillator enabled. 1185 * STATE_RESET_ALL starts the next burst; the hardware does not 1186 * accumulate new conversions until after a STATE_RESET pulse, so 1187 * no in-progress data is lost. No cs_change here — CS must 1188 * deassert normally at end of message to frame the next command. 1189 */ 1190 put_unaligned_be16(AD4691_STATE_RESET_REG, st->scan_tx_reset); 1191 st->scan_tx_reset[2] = AD4691_STATE_RESET_ALL; 1192 st->scan_tx_reset[3] = 1; 1193 st->scan_xfers[2 * k].tx_buf = st->scan_tx_reset; 1194 st->scan_xfers[2 * k].len = sizeof(st->scan_tx_reset); 1195 spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg); 1196 1197 ret = spi_optimize_message(st->spi, &st->scan_msg); 1198 if (ret) 1199 return ret; 1200 1201 std_seq_config = bitmap_read(indio_dev->active_scan_mask, 0, 1202 iio_get_masklength(indio_dev)) & GENMASK(15, 0); 1203 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, std_seq_config); 1204 if (ret) 1205 goto err_unoptimize; 1206 1207 acc_mask = ~std_seq_config & GENMASK(15, 0); 1208 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG, acc_mask); 1209 if (ret) 1210 goto err_unoptimize; 1211 1212 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr); 1213 if (ret) 1214 goto err_unoptimize; 1215 1216 ret = ad4691_enter_conversion_mode(st); 1217 if (ret) 1218 goto err_unoptimize; 1219 1220 return 0; 1221 1222 err_unoptimize: 1223 spi_unoptimize_message(&st->scan_msg); 1224 return ret; 1225 } 1226 1227 static int ad4691_cnv_burst_buffer_postenable(struct iio_dev *indio_dev) 1228 { 1229 struct ad4691_state *st = iio_priv(indio_dev); 1230 int ret; 1231 1232 /* 1233 * Start the PWM and unmask the IRQ here in postenable, not in 1234 * preenable. The IIO core attaches the trigger poll function between 1235 * preenable and postenable; enabling sampling or unmasking the IRQ 1236 * before that point risks a DATA_READY assertion landing before the 1237 * poll function is registered. iio_trigger_poll() would drop the 1238 * event, disable_irq_nosync() would fire, and enable_irq() would 1239 * never be called, leaving the IRQ permanently masked. 1240 */ 1241 ret = ad4691_sampling_enable(st, true); 1242 if (ret) 1243 return ret; 1244 1245 enable_irq(st->irq); 1246 st->irq_enabled = true; 1247 return 0; 1248 } 1249 1250 static int ad4691_cnv_burst_buffer_predisable(struct iio_dev *indio_dev) 1251 { 1252 struct ad4691_state *st = iio_priv(indio_dev); 1253 1254 if (st->irq_enabled) { 1255 disable_irq(st->irq); 1256 st->irq_enabled = false; 1257 } 1258 return ad4691_sampling_enable(st, false); 1259 } 1260 1261 static int ad4691_cnv_burst_buffer_postdisable(struct iio_dev *indio_dev) 1262 { 1263 struct ad4691_state *st = iio_priv(indio_dev); 1264 int ret; 1265 1266 ret = ad4691_exit_conversion_mode(st); 1267 spi_unoptimize_message(&st->scan_msg); 1268 return ret; 1269 } 1270 1271 static const struct iio_buffer_setup_ops ad4691_cnv_burst_buffer_setup_ops = { 1272 .preenable = ad4691_cnv_burst_buffer_preenable, 1273 .postenable = ad4691_cnv_burst_buffer_postenable, 1274 .predisable = ad4691_cnv_burst_buffer_predisable, 1275 .postdisable = ad4691_cnv_burst_buffer_postdisable, 1276 }; 1277 1278 static int ad4691_manual_offload_buffer_postenable(struct iio_dev *indio_dev) 1279 { 1280 struct ad4691_state *st = iio_priv(indio_dev); 1281 struct device *dev = regmap_get_device(st->regmap); 1282 struct spi_device *spi = to_spi_device(dev); 1283 struct spi_offload_trigger_config config = { 1284 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1285 }; 1286 unsigned int bpw = indio_dev->channels[0].scan_type.realbits; 1287 unsigned int bit, k; 1288 int ret; 1289 1290 ret = ad4691_enter_conversion_mode(st); 1291 if (ret) 1292 return ret; 1293 1294 memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); 1295 memset(st->scan_tx, 0, sizeof(st->scan_tx)); 1296 1297 /* 1298 * N+1 transfers for N channels. Each CS-low period triggers 1299 * a conversion AND returns the previous result (pipelined). 1300 * TX: [AD4691_ADC_CHAN(n), 0x00] 1301 * RX: [data_hi, data_lo] (storagebits=16, shift=0) 1302 * Transfer 0 RX is garbage; transfers 1..N carry real data. 1303 * scan_tx is reused for TX commands (mutually exclusive with the 1304 * non-offload triggered-buffer path). 1305 * 1306 * bits_per_word=bpw: the SPI controller reads tx_buf as a native 1307 * 16-bit word and shifts it out MSB-first. Store the exact 16-bit 1308 * value we want on the wire as a plain native u16 — no endianness 1309 * macro — so the wire bytes are correct on both LE and BE hosts. 1310 * The channel-select command is a single byte; shift it to the MSB 1311 * position so SPI sends it first, with a zero pad in the LSB. 1312 */ 1313 k = 0; 1314 iio_for_each_active_channel(indio_dev, bit) { 1315 st->scan_tx[k] = AD4691_ADC_CHAN(bit) << 8; 1316 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; 1317 st->scan_xfers[k].len = sizeof(*st->scan_tx); 1318 st->scan_xfers[k].bits_per_word = bpw; 1319 st->scan_xfers[k].cs_change = 1; 1320 st->scan_xfers[k].cs_change_delay.value = AD4691_CNV_HIGH_TIME_NS; 1321 st->scan_xfers[k].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS; 1322 /* First transfer RX is garbage — skip it. */ 1323 if (k > 0) 1324 st->scan_xfers[k].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1325 k++; 1326 } 1327 1328 /* Final NOOP transfer retrieves the last channel's result. */ 1329 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; /* scan_tx[k] == 0 == NOOP */ 1330 st->scan_xfers[k].len = sizeof(*st->scan_tx); 1331 st->scan_xfers[k].bits_per_word = bpw; 1332 st->scan_xfers[k].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1333 k++; 1334 1335 spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, k); 1336 st->scan_msg.offload = st->offload; 1337 1338 ret = spi_optimize_message(spi, &st->scan_msg); 1339 if (ret) 1340 goto err_exit_conversion; 1341 1342 config.periodic.frequency_hz = st->trigger_hz; 1343 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); 1344 if (ret) 1345 goto err_unoptimize; 1346 1347 return 0; 1348 1349 err_unoptimize: 1350 spi_unoptimize_message(&st->scan_msg); 1351 err_exit_conversion: 1352 ad4691_exit_conversion_mode(st); 1353 return ret; 1354 } 1355 1356 static int ad4691_manual_offload_buffer_predisable(struct iio_dev *indio_dev) 1357 { 1358 struct ad4691_state *st = iio_priv(indio_dev); 1359 1360 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1361 spi_unoptimize_message(&st->scan_msg); 1362 1363 return ad4691_exit_conversion_mode(st); 1364 } 1365 1366 static const struct iio_buffer_setup_ops ad4691_manual_offload_buffer_setup_ops = { 1367 .postenable = ad4691_manual_offload_buffer_postenable, 1368 .predisable = ad4691_manual_offload_buffer_predisable, 1369 }; 1370 1371 static int ad4691_cnv_burst_offload_buffer_postenable(struct iio_dev *indio_dev) 1372 { 1373 struct ad4691_state *st = iio_priv(indio_dev); 1374 struct device *dev = regmap_get_device(st->regmap); 1375 struct spi_device *spi = to_spi_device(dev); 1376 struct spi_offload_trigger_config config = { 1377 .type = SPI_OFFLOAD_TRIGGER_DATA_READY, 1378 }; 1379 unsigned int bpw = indio_dev->channels[0].scan_type.realbits; 1380 unsigned int acc_mask, std_seq_config; 1381 unsigned int bit, k; 1382 int ret; 1383 1384 std_seq_config = bitmap_read(indio_dev->active_scan_mask, 0, 1385 iio_get_masklength(indio_dev)) & GENMASK(15, 0); 1386 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, std_seq_config); 1387 if (ret) 1388 return ret; 1389 1390 acc_mask = ~std_seq_config & GENMASK(15, 0); 1391 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG, acc_mask); 1392 if (ret) 1393 return ret; 1394 1395 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr); 1396 if (ret) 1397 return ret; 1398 1399 ret = ad4691_enter_conversion_mode(st); 1400 if (ret) 1401 return ret; 1402 1403 memset(st->scan_xfers, 0, sizeof(st->scan_xfers)); 1404 memset(st->scan_tx, 0, sizeof(st->scan_tx)); 1405 1406 /* 1407 * Each AVG_IN register read uses two transfers: 1408 * TX: [reg_hi | 0x80, reg_lo] (address phase, CS stays asserted) 1409 * RX: [data_hi, data_lo] (bpw-wide data phase, storagebits=16) 1410 * Both TX and RX use bits_per_word=bpw: the SPI controller reads tx_buf 1411 * as a native 16-bit word and shifts it out MSB-first. Store the exact 1412 * 16-bit wire value as a plain native u16 — no endianness macro — so the 1413 * wire bytes are correct on both LE and BE hosts. The read-address 1414 * (0x8000 | reg) is already the 16-bit value we want on the wire. 1415 * scan_tx is reused for TX addresses (mutually exclusive with the 1416 * non-offload triggered-buffer path). 1417 */ 1418 k = 0; 1419 iio_for_each_active_channel(indio_dev, bit) { 1420 st->scan_tx[k] = 0x8000 | AD4691_AVG_IN(bit); 1421 1422 /* TX: address phase, CS stays asserted into data phase */ 1423 st->scan_xfers[2 * k].tx_buf = &st->scan_tx[k]; 1424 st->scan_xfers[2 * k].len = sizeof(*st->scan_tx); 1425 st->scan_xfers[2 * k].bits_per_word = bpw; 1426 1427 /* RX: data phase, CS toggles after to delimit the next register op */ 1428 st->scan_xfers[2 * k + 1].len = sizeof(*st->scan_tx); 1429 st->scan_xfers[2 * k + 1].bits_per_word = bpw; 1430 st->scan_xfers[2 * k + 1].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM; 1431 st->scan_xfers[2 * k + 1].cs_change = 1; 1432 k++; 1433 } 1434 1435 /* 1436 * State reset: single 4-byte write [addr_hi, addr_lo, STATE_RESET_ALL, 1437 * OSC_EN=1]. ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as 1438 * a deliberate side-write, keeping the oscillator enabled. 1439 * scan_tx_reset is shared with the non-offload path (len=4 here vs 1440 * len=3 there) since the two paths are mutually exclusive at probe. 1441 */ 1442 put_unaligned_be16(AD4691_STATE_RESET_REG, st->scan_tx_reset); 1443 st->scan_tx_reset[2] = AD4691_STATE_RESET_ALL; 1444 st->scan_tx_reset[3] = 1; 1445 st->scan_xfers[2 * k].tx_buf = st->scan_tx_reset; 1446 st->scan_xfers[2 * k].len = sizeof(st->scan_tx_reset); 1447 /* 1448 * 4-byte u8 buffer assembled with put_unaligned_be16(); leave 1449 * bits_per_word at the default (8) so bytes go out in memory order. 1450 */ 1451 1452 spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, 2 * k + 1); 1453 st->scan_msg.offload = st->offload; 1454 1455 ret = spi_optimize_message(spi, &st->scan_msg); 1456 if (ret) 1457 goto err_exit_conversion; 1458 1459 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config); 1460 if (ret) 1461 goto err_unoptimize; 1462 1463 ret = ad4691_sampling_enable(st, true); 1464 if (ret) 1465 goto err_disable_trigger; 1466 1467 return 0; 1468 1469 err_disable_trigger: 1470 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1471 err_unoptimize: 1472 spi_unoptimize_message(&st->scan_msg); 1473 err_exit_conversion: 1474 ad4691_exit_conversion_mode(st); 1475 return ret; 1476 } 1477 1478 static int ad4691_cnv_burst_offload_buffer_predisable(struct iio_dev *indio_dev) 1479 { 1480 struct ad4691_state *st = iio_priv(indio_dev); 1481 1482 ad4691_sampling_enable(st, false); 1483 spi_offload_trigger_disable(st->offload, st->offload_trigger); 1484 spi_unoptimize_message(&st->scan_msg); 1485 1486 return ad4691_exit_conversion_mode(st); 1487 } 1488 1489 static const struct iio_buffer_setup_ops ad4691_cnv_burst_offload_buffer_setup_ops = { 1490 .postenable = ad4691_cnv_burst_offload_buffer_postenable, 1491 .predisable = ad4691_cnv_burst_offload_buffer_predisable, 1492 }; 1493 1494 static ssize_t sampling_frequency_show(struct device *dev, 1495 struct device_attribute *attr, 1496 char *buf) 1497 { 1498 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1499 struct ad4691_state *st = iio_priv(indio_dev); 1500 1501 if (st->manual_mode && st->offload) 1502 return sysfs_emit(buf, "%llu\n", READ_ONCE(st->trigger_hz)); 1503 1504 return sysfs_emit(buf, "%lu\n", NSEC_PER_SEC / st->cnv_period_ns); 1505 } 1506 1507 static ssize_t sampling_frequency_store(struct device *dev, 1508 struct device_attribute *attr, 1509 const char *buf, size_t len) 1510 { 1511 struct iio_dev *indio_dev = dev_to_iio_dev(dev); 1512 struct ad4691_state *st = iio_priv(indio_dev); 1513 unsigned int freq; 1514 int ret; 1515 1516 ret = kstrtouint(buf, 10, &freq); 1517 if (ret) 1518 return ret; 1519 1520 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); 1521 if (IIO_DEV_ACQUIRE_FAILED(claim)) 1522 return -EBUSY; 1523 1524 if (st->manual_mode && st->offload) { 1525 struct spi_offload_trigger_config config = { 1526 .type = SPI_OFFLOAD_TRIGGER_PERIODIC, 1527 .periodic = { .frequency_hz = freq }, 1528 }; 1529 1530 ret = spi_offload_trigger_validate(st->offload_trigger, &config); 1531 if (ret) 1532 return ret; 1533 1534 WRITE_ONCE(st->trigger_hz, config.periodic.frequency_hz); 1535 return len; 1536 } 1537 1538 ret = ad4691_set_pwm_freq(st, freq); 1539 if (ret) 1540 return ret; 1541 1542 return len; 1543 } 1544 1545 static IIO_DEVICE_ATTR_RW(sampling_frequency, 0); 1546 1547 static const struct iio_dev_attr *ad4691_buffer_attrs[] = { 1548 &iio_dev_attr_sampling_frequency, 1549 NULL 1550 }; 1551 1552 static irqreturn_t ad4691_irq(int irq, void *private) 1553 { 1554 struct iio_dev *indio_dev = private; 1555 struct ad4691_state *st = iio_priv(indio_dev); 1556 1557 /* 1558 * Disable the IRQ before calling iio_trigger_poll(). The IRQ is 1559 * re-enabled via the trigger .reenable callback, which the IIO core 1560 * calls inside iio_trigger_notify_done() once use_count reaches zero. 1561 * Re-enabling here (before notify_done) would race: a DATA_READY 1562 * between enable_irq() and notify_done() calls iio_trigger_poll() 1563 * while use_count > 0, dropping the event and permanently masking 1564 * the IRQ. 1565 */ 1566 disable_irq_nosync(st->irq); 1567 iio_trigger_poll(indio_dev->trig); 1568 1569 return IRQ_HANDLED; 1570 } 1571 1572 static void ad4691_trigger_reenable(struct iio_trigger *trig) 1573 { 1574 struct ad4691_state *st = iio_trigger_get_drvdata(trig); 1575 1576 enable_irq(st->irq); 1577 } 1578 1579 static const struct iio_trigger_ops ad4691_trigger_ops = { 1580 .reenable = ad4691_trigger_reenable, 1581 .validate_device = iio_trigger_validate_own_device, 1582 }; 1583 1584 static void ad4691_read_scan(struct iio_dev *indio_dev, s64 ts) 1585 { 1586 struct ad4691_state *st = iio_priv(indio_dev); 1587 int ret; 1588 1589 guard(mutex)(&st->lock); 1590 1591 ret = spi_sync(st->spi, &st->scan_msg); 1592 if (ret) { 1593 dev_err_ratelimited(regmap_get_device(st->regmap), 1594 "SPI scan failed: %d\n", ret); 1595 return; 1596 } 1597 1598 /* 1599 * rx_buf pointers in scan_xfers point directly into scan.vals, so no 1600 * copy is needed. The scan_msg already includes a STATE_RESET at the 1601 * end (appended in preenable), so no explicit reset is needed here. 1602 */ 1603 iio_push_to_buffers_with_ts(indio_dev, st->vals, sizeof(st->vals), ts); 1604 } 1605 1606 static irqreturn_t ad4691_trigger_handler(int irq, void *p) 1607 { 1608 struct iio_poll_func *pf = p; 1609 struct iio_dev *indio_dev = pf->indio_dev; 1610 1611 ad4691_read_scan(indio_dev, pf->timestamp); 1612 iio_trigger_notify_done(indio_dev->trig); 1613 return IRQ_HANDLED; 1614 } 1615 1616 /* 1617 * CNV burst mode: only allow our own trigger (driven by DATA_READY IRQ). 1618 * Manual mode: external triggers (e.g. iio-trig-hrtimer) must be allowed 1619 * because manual mode has no DATA_READY IRQ to fire the internal trigger. 1620 * iio_trigger_ops.validate_device = iio_trigger_validate_own_device is 1621 * correct in both modes — it prevents other devices from hijacking our 1622 * internal trigger; the distinction here is only for iio_info.validate_trigger. 1623 */ 1624 static const struct iio_info ad4691_cnv_burst_info = { 1625 .read_raw = ad4691_read_raw, 1626 .write_raw = ad4691_write_raw, 1627 .read_avail = ad4691_read_avail, 1628 .debugfs_reg_access = ad4691_reg_access, 1629 .validate_trigger = iio_validate_own_trigger, 1630 }; 1631 1632 static const struct iio_info ad4691_manual_info = { 1633 .read_raw = ad4691_read_raw, 1634 .write_raw = ad4691_write_raw, 1635 .read_avail = ad4691_read_avail, 1636 .debugfs_reg_access = ad4691_reg_access, 1637 }; 1638 1639 static int ad4691_pwm_setup(struct ad4691_state *st) 1640 { 1641 struct device *dev = regmap_get_device(st->regmap); 1642 1643 st->conv_trigger = devm_pwm_get(dev, "cnv"); 1644 if (IS_ERR(st->conv_trigger)) 1645 return dev_err_probe(dev, PTR_ERR(st->conv_trigger), 1646 "Failed to get CNV PWM\n"); 1647 1648 return ad4691_set_pwm_freq(st, st->info->max_rate); 1649 } 1650 1651 static int ad4691_regulator_setup(struct ad4691_state *st) 1652 { 1653 struct device *dev = regmap_get_device(st->regmap); 1654 int ret; 1655 1656 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4691_supplies), 1657 ad4691_supplies); 1658 if (ret) 1659 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n"); 1660 1661 /* 1662 * vdd-supply and ldo-in-supply are mutually exclusive: 1663 * vdd-supply present → external 1.8V VDD; disable internal LDO. 1664 * vdd-supply absent → enable internal LDO fed from ldo-in-supply. 1665 * Having both simultaneously is strongly inadvisable per the datasheet. 1666 */ 1667 if (device_property_present(dev, "vdd-supply")) { 1668 ret = devm_regulator_get_enable(dev, "vdd"); 1669 if (ret) 1670 return dev_err_probe(dev, ret, 1671 "Failed to get and enable VDD\n"); 1672 } else if (device_property_present(dev, "ldo-in-supply")) { 1673 ret = devm_regulator_get_enable(dev, "ldo-in"); 1674 if (ret) 1675 return dev_err_probe(dev, ret, 1676 "Failed to get and enable LDO-IN\n"); 1677 st->ldo_en = true; 1678 } else { 1679 return dev_err_probe(dev, -EINVAL, 1680 "missing one of vdd-supply, ldo-in-supply\n"); 1681 } 1682 1683 if (device_property_present(dev, "ref-supply")) { 1684 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref"); 1685 if (st->vref_uV < 0) 1686 return dev_err_probe(dev, st->vref_uV, 1687 "Failed to get REF supply voltage\n"); 1688 } else if (device_property_present(dev, "refin-supply")) { 1689 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "refin"); 1690 if (st->vref_uV < 0) 1691 return dev_err_probe(dev, st->vref_uV, 1692 "Failed to get REFIN supply voltage\n"); 1693 st->refbuf_en = true; 1694 } else { 1695 return dev_err_probe(dev, -EINVAL, 1696 "missing one of ref-supply, refin-supply\n"); 1697 } 1698 1699 if (st->vref_uV < AD4691_VREF_uV_MIN || st->vref_uV > AD4691_VREF_uV_MAX) 1700 return dev_err_probe(dev, -EINVAL, 1701 "vref(%d) must be in the range [%u...%u]\n", 1702 st->vref_uV, AD4691_VREF_uV_MIN, 1703 AD4691_VREF_uV_MAX); 1704 1705 return 0; 1706 } 1707 1708 static int ad4691_reset(struct ad4691_state *st) 1709 { 1710 struct device *dev = regmap_get_device(st->regmap); 1711 struct reset_control *rst; 1712 int ret; 1713 1714 rst = devm_reset_control_get_optional_exclusive(dev, NULL); 1715 if (IS_ERR(rst)) 1716 return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n"); 1717 1718 if (rst) { 1719 /* 1720 * Assert the reset line to guarantee a clean reset pulse on 1721 * every probe, including driver reloads where the line may 1722 * already be deasserted (reset_control_put() does not 1723 * re-assert on release). tRESETL (minimum pulse width) = 10 ns 1724 * (Table 5); kernel function-call overhead alone exceeds this, 1725 * so no explicit delay is needed between assert and deassert. 1726 */ 1727 reset_control_assert(rst); 1728 ret = reset_control_deassert(rst); 1729 if (ret) 1730 return ret; 1731 } else { 1732 /* No hardware reset available, fall back to software reset. */ 1733 ret = regmap_write(st->regmap, AD4691_SPI_CONFIG_A_REG, 1734 AD4691_SW_RESET); 1735 if (ret) 1736 return ret; 1737 } 1738 1739 /* 1740 * Wait 300 µs (Table 5) for the device to complete its internal reset 1741 * sequence before accepting SPI commands. 1742 */ 1743 fsleep(300); 1744 return 0; 1745 } 1746 1747 static int ad4691_config(struct ad4691_state *st) 1748 { 1749 struct device *dev = regmap_get_device(st->regmap); 1750 enum ad4691_ref_ctrl ref_val; 1751 unsigned int val; 1752 int ret; 1753 1754 /* 1755 * Determine buffer conversion mode from DT: if a PWM is provided it 1756 * drives the CNV pin (CNV_BURST_MODE); otherwise CNV is tied to CS 1757 * and each SPI transfer triggers a conversion (MANUAL_MODE). 1758 * Both modes idle in AUTONOMOUS mode so that read_raw can use the 1759 * internal oscillator without disturbing the hardware configuration. 1760 */ 1761 if (device_property_present(dev, "pwms")) { 1762 st->manual_mode = false; 1763 ret = ad4691_pwm_setup(st); 1764 if (ret) 1765 return ret; 1766 } else { 1767 st->manual_mode = true; 1768 } 1769 1770 switch (st->vref_uV) { 1771 case AD4691_VREF_uV_MIN ... AD4691_VREF_2P5_uV_MAX: 1772 ref_val = AD4691_VREF_2P5; 1773 break; 1774 case AD4691_VREF_2P5_uV_MAX + 1 ... AD4691_VREF_3P0_uV_MAX: 1775 ref_val = AD4691_VREF_3P0; 1776 break; 1777 case AD4691_VREF_3P0_uV_MAX + 1 ... AD4691_VREF_3P3_uV_MAX: 1778 ref_val = AD4691_VREF_3P3; 1779 break; 1780 case AD4691_VREF_3P3_uV_MAX + 1 ... AD4691_VREF_4P096_uV_MAX: 1781 ref_val = AD4691_VREF_4P096; 1782 break; 1783 case AD4691_VREF_4P096_uV_MAX + 1 ... AD4691_VREF_uV_MAX: 1784 ref_val = AD4691_VREF_5P0; 1785 break; 1786 default: 1787 return dev_err_probe(dev, -EINVAL, 1788 "Unsupported vref voltage: %d uV\n", 1789 st->vref_uV); 1790 } 1791 1792 val = FIELD_PREP(AD4691_REF_CTRL_MASK, ref_val); 1793 if (st->refbuf_en) 1794 val |= AD4691_REFBUF_EN; 1795 1796 ret = regmap_write(st->regmap, AD4691_REF_CTRL, val); 1797 if (ret) 1798 return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n"); 1799 1800 ret = regmap_assign_bits(st->regmap, AD4691_DEVICE_SETUP, 1801 AD4691_LDO_EN, st->ldo_en); 1802 if (ret) 1803 return dev_err_probe(dev, ret, "Failed to write DEVICE_SETUP\n"); 1804 1805 /* 1806 * Set the internal oscillator to the highest rate this chip supports. 1807 * Index 0 (1 MHz) exceeds the 500 kHz max of AD4691/AD4693, so those 1808 * chips start at index 1 (500 kHz). 1809 */ 1810 ret = regmap_write(st->regmap, AD4691_OSC_FREQ_REG, 1811 ad4691_samp_freq_start(st->info)); 1812 if (ret) 1813 return dev_err_probe(dev, ret, "Failed to write OSC_FREQ\n"); 1814 1815 st->target_osc_freq_Hz = ad4691_osc_freqs_Hz[ad4691_samp_freq_start(st->info)]; 1816 1817 ret = regmap_update_bits(st->regmap, AD4691_ADC_SETUP, 1818 AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE); 1819 if (ret) 1820 return dev_err_probe(dev, ret, "Failed to write ADC_SETUP\n"); 1821 1822 ad4691_precompute_samp_freq_avail(st); 1823 1824 return 0; 1825 } 1826 1827 static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev, 1828 struct ad4691_state *st) 1829 { 1830 struct device *dev = regmap_get_device(st->regmap); 1831 struct iio_trigger *trig; 1832 unsigned int i; 1833 int irq, ret; 1834 1835 /* 1836 * Manual mode exposes channels without the oversampling_ratio attribute 1837 * because ACC_DEPTH_IN is not configured in manual mode. 1838 */ 1839 if (st->manual_mode) 1840 indio_dev->channels = st->info->sw_info->manual_channels; 1841 else 1842 indio_dev->channels = st->info->sw_info->channels; 1843 indio_dev->num_channels = st->info->sw_info->num_channels; 1844 indio_dev->info = st->manual_mode ? &ad4691_manual_info : &ad4691_cnv_burst_info; 1845 1846 /* 1847 * Manual mode relies on an external trigger (e.g. iio-trig-hrtimer); 1848 * no internal trigger is needed or registered. 1849 */ 1850 if (st->manual_mode) 1851 return devm_iio_triggered_buffer_setup(dev, indio_dev, 1852 iio_pollfunc_store_time, 1853 ad4691_trigger_handler, 1854 &ad4691_manual_buffer_setup_ops); 1855 1856 /* 1857 * CNV burst mode: allocate an internal trigger driven by the 1858 * DATA_READY IRQ on the GP pin. 1859 */ 1860 trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name, 1861 iio_device_id(indio_dev)); 1862 if (!trig) 1863 return -ENOMEM; 1864 1865 trig->ops = &ad4691_trigger_ops; 1866 iio_trigger_set_drvdata(trig, st); 1867 1868 ret = devm_iio_trigger_register(dev, trig); 1869 if (ret) 1870 return dev_err_probe(dev, ret, "IIO trigger register failed\n"); 1871 1872 indio_dev->trig = iio_trigger_get(trig); 1873 1874 /* 1875 * The GP pin named in interrupt-names asserts at end-of-conversion. 1876 * The IRQ handler fires the IIO trigger so the trigger handler can 1877 * read and push the sample to the buffer. The IRQ is kept disabled 1878 * until the buffer is enabled. 1879 */ 1880 irq = -ENXIO; 1881 for (i = 0; i < ARRAY_SIZE(ad4691_gp_names); i++) { 1882 irq = fwnode_irq_get_byname(dev_fwnode(dev), 1883 ad4691_gp_names[i]); 1884 if (irq > 0 || irq == -EPROBE_DEFER) 1885 break; 1886 } 1887 if (irq < 0) 1888 return dev_err_probe(dev, irq, "failed to get GP interrupt\n"); 1889 1890 st->irq = irq; 1891 1892 ret = ad4691_gpio_setup(st, i); 1893 if (ret) 1894 return ret; 1895 1896 /* 1897 * The handler only calls disable_irq_nosync() and iio_trigger_poll(), 1898 * both safe in hardirq context, so register as a hard IRQ handler. 1899 * IRQF_NO_AUTOEN keeps it disabled until the buffer is enabled. 1900 */ 1901 ret = devm_request_irq(dev, irq, ad4691_irq, IRQF_NO_AUTOEN, 1902 indio_dev->name, indio_dev); 1903 if (ret) 1904 return ret; 1905 1906 return devm_iio_triggered_buffer_setup_ext(dev, indio_dev, 1907 iio_pollfunc_store_time, 1908 ad4691_trigger_handler, 1909 IIO_BUFFER_DIRECTION_IN, 1910 &ad4691_cnv_burst_buffer_setup_ops, 1911 ad4691_buffer_attrs); 1912 } 1913 1914 static int ad4691_setup_offload(struct iio_dev *indio_dev, 1915 struct ad4691_state *st, 1916 struct spi_offload *spi_offload) 1917 { 1918 struct device *dev = regmap_get_device(st->regmap); 1919 struct dma_chan *rx_dma; 1920 int ret; 1921 1922 st->offload = spi_offload; 1923 1924 /* 1925 * CNV burst offload exposes oversampling_ratio (ACC_DEPTH_IN is 1926 * configured per channel at buffer enable). Manual offload does not 1927 * configure ACC_DEPTH_IN, so it uses a separate channel array 1928 * without the oversampling_ratio attribute. Both paths use IIO_CPU 1929 * (no .endianness annotation) because bits_per_word=16 causes the 1930 * SPI Engine to produce native 16-bit DMA words. 1931 */ 1932 if (st->manual_mode) 1933 indio_dev->channels = st->info->offload_info->manual_channels; 1934 else 1935 indio_dev->channels = st->info->offload_info->channels; 1936 indio_dev->num_channels = st->info->offload_info->num_channels; 1937 /* 1938 * Offload path uses DMA directly; no IIO trigger is involved, so 1939 * external triggers are not restricted (no validate_trigger). 1940 */ 1941 indio_dev->info = &ad4691_manual_info; 1942 1943 if (st->manual_mode) { 1944 st->offload_trigger = 1945 devm_spi_offload_trigger_get(dev, st->offload, 1946 SPI_OFFLOAD_TRIGGER_PERIODIC); 1947 if (IS_ERR(st->offload_trigger)) 1948 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1949 "Failed to get periodic offload trigger\n"); 1950 1951 st->trigger_hz = AD4691_OFFLOAD_INITIAL_TRIGGER_HZ; 1952 } else { 1953 struct spi_offload_trigger_info trigger_info = { 1954 .fwnode = dev_fwnode(dev), 1955 .ops = &ad4691_offload_trigger_ops, 1956 .priv = st, 1957 }; 1958 1959 ret = devm_spi_offload_trigger_register(dev, &trigger_info); 1960 if (ret) 1961 return dev_err_probe(dev, ret, 1962 "Failed to register offload trigger\n"); 1963 1964 st->offload_trigger = 1965 devm_spi_offload_trigger_get(dev, st->offload, 1966 SPI_OFFLOAD_TRIGGER_DATA_READY); 1967 if (IS_ERR(st->offload_trigger)) 1968 return dev_err_probe(dev, PTR_ERR(st->offload_trigger), 1969 "Failed to get DATA_READY offload trigger\n"); 1970 } 1971 1972 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload); 1973 if (IS_ERR(rx_dma)) 1974 return dev_err_probe(dev, PTR_ERR(rx_dma), 1975 "Failed to get offload RX DMA channel\n"); 1976 1977 if (st->manual_mode) 1978 indio_dev->setup_ops = &ad4691_manual_offload_buffer_setup_ops; 1979 else 1980 indio_dev->setup_ops = &ad4691_cnv_burst_offload_buffer_setup_ops; 1981 1982 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma, 1983 IIO_BUFFER_DIRECTION_IN); 1984 if (ret) 1985 return ret; 1986 1987 indio_dev->buffer->attrs = ad4691_buffer_attrs; 1988 1989 return 0; 1990 } 1991 1992 static int ad4691_probe(struct spi_device *spi) 1993 { 1994 struct device *dev = &spi->dev; 1995 struct spi_offload *spi_offload; 1996 struct iio_dev *indio_dev; 1997 struct ad4691_state *st; 1998 int ret; 1999 2000 indio_dev = devm_iio_device_alloc(dev, sizeof(*st)); 2001 if (!indio_dev) 2002 return -ENOMEM; 2003 2004 st = iio_priv(indio_dev); 2005 st->spi = spi; 2006 st->info = spi_get_device_match_data(spi); 2007 if (!st->info) 2008 return -ENODEV; 2009 st->osr = 1; 2010 2011 ret = devm_mutex_init(dev, &st->lock); 2012 if (ret) 2013 return ret; 2014 2015 st->regmap = devm_regmap_init(dev, NULL, spi, &ad4691_regmap_config); 2016 if (IS_ERR(st->regmap)) 2017 return dev_err_probe(dev, PTR_ERR(st->regmap), 2018 "Failed to initialize regmap\n"); 2019 2020 ret = ad4691_regulator_setup(st); 2021 if (ret) 2022 return ret; 2023 2024 ret = ad4691_reset(st); 2025 if (ret) 2026 return ret; 2027 2028 ret = ad4691_config(st); 2029 if (ret) 2030 return ret; 2031 2032 spi_offload = devm_spi_offload_get(dev, spi, &ad4691_offload_config); 2033 ret = PTR_ERR_OR_ZERO(spi_offload); 2034 if (ret == -ENODEV) 2035 spi_offload = NULL; 2036 else if (ret) 2037 return dev_err_probe(dev, ret, "Failed to get SPI offload\n"); 2038 2039 indio_dev->name = st->info->name; 2040 indio_dev->modes = INDIO_DIRECT_MODE; 2041 2042 if (spi_offload) 2043 ret = ad4691_setup_offload(indio_dev, st, spi_offload); 2044 else 2045 ret = ad4691_setup_triggered_buffer(indio_dev, st); 2046 if (ret) 2047 return ret; 2048 2049 return devm_iio_device_register(dev, indio_dev); 2050 } 2051 2052 static const struct of_device_id ad4691_of_match[] = { 2053 { .compatible = "adi,ad4691", .data = &ad4691_chip_info }, 2054 { .compatible = "adi,ad4692", .data = &ad4692_chip_info }, 2055 { .compatible = "adi,ad4693", .data = &ad4693_chip_info }, 2056 { .compatible = "adi,ad4694", .data = &ad4694_chip_info }, 2057 { } 2058 }; 2059 MODULE_DEVICE_TABLE(of, ad4691_of_match); 2060 2061 static const struct spi_device_id ad4691_id[] = { 2062 { .name = "ad4691", .driver_data = (kernel_ulong_t)&ad4691_chip_info }, 2063 { .name = "ad4692", .driver_data = (kernel_ulong_t)&ad4692_chip_info }, 2064 { .name = "ad4693", .driver_data = (kernel_ulong_t)&ad4693_chip_info }, 2065 { .name = "ad4694", .driver_data = (kernel_ulong_t)&ad4694_chip_info }, 2066 { } 2067 }; 2068 MODULE_DEVICE_TABLE(spi, ad4691_id); 2069 2070 static struct spi_driver ad4691_driver = { 2071 .driver = { 2072 .name = "ad4691", 2073 .of_match_table = ad4691_of_match, 2074 }, 2075 .probe = ad4691_probe, 2076 .id_table = ad4691_id, 2077 }; 2078 module_spi_driver(ad4691_driver); 2079 2080 MODULE_AUTHOR("Radu Sabau <radu.sabau@analog.com>"); 2081 MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver"); 2082 MODULE_LICENSE("GPL"); 2083 MODULE_IMPORT_NS("IIO_DMA_BUFFER"); 2084 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER"); 2085