1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * Copyright (C) 2024-2026 Analog Devices, Inc.
4 * Author: Radu Sabau <radu.sabau@analog.com>
5 */
6 #include <linux/array_size.h>
7 #include <linux/bitfield.h>
8 #include <linux/bitmap.h>
9 #include <linux/cleanup.h>
10 #include <linux/delay.h>
11 #include <linux/dev_printk.h>
12 #include <linux/device/devres.h>
13 #include <linux/dmaengine.h>
14 #include <linux/err.h>
15 #include <linux/interrupt.h>
16 #include <linux/kstrtox.h>
17 #include <linux/limits.h>
18 #include <linux/math.h>
19 #include <linux/module.h>
20 #include <linux/property.h>
21 #include <linux/pwm.h>
22 #include <linux/regmap.h>
23 #include <linux/regulator/consumer.h>
24 #include <linux/reset.h>
25 #include <linux/string.h>
26 #include <linux/spi/spi.h>
27 #include <linux/spi/offload/consumer.h>
28 #include <linux/spi/offload/provider.h>
29 #include <linux/types.h>
30 #include <linux/units.h>
31 #include <linux/unaligned.h>
32
33 #include <linux/iio/buffer.h>
34 #include <linux/iio/buffer-dma.h>
35 #include <linux/iio/buffer-dmaengine.h>
36 #include <linux/iio/iio.h>
37 #include <linux/iio/sysfs.h>
38 #include <linux/iio/trigger.h>
39 #include <linux/iio/triggered_buffer.h>
40 #include <linux/iio/trigger_consumer.h>
41
42 #define AD4691_VREF_uV_MIN 2400000
43 #define AD4691_VREF_uV_MAX 5250000
44 #define AD4691_VREF_2P5_uV_MAX 2750000
45 #define AD4691_VREF_3P0_uV_MAX 3250000
46 #define AD4691_VREF_3P3_uV_MAX 3750000
47 #define AD4691_VREF_4P096_uV_MAX 4500000
48
49 #define AD4691_CNV_DUTY_CYCLE_NS 380
50 #define AD4691_CNV_HIGH_TIME_NS 430
51 /*
52 * Conservative default for the manual offload periodic trigger. Low enough
53 * to work safely out of the box across all OSR and channel count combinations.
54 */
55 #define AD4691_OFFLOAD_INITIAL_TRIGGER_HZ (100 * HZ_PER_KHZ)
56
57 #define AD4691_SPI_CONFIG_A_REG 0x000
58 #define AD4691_SW_RESET (BIT(7) | BIT(0))
59
60 #define AD4691_STATUS_REG 0x014
61 #define AD4691_CLAMP_STATUS1_REG 0x01A
62 #define AD4691_CLAMP_STATUS2_REG 0x01B
63 #define AD4691_DEVICE_SETUP 0x020
64 #define AD4691_MANUAL_MODE BIT(2)
65 #define AD4691_LDO_EN BIT(4)
66 #define AD4691_REF_CTRL 0x021
67 #define AD4691_REF_CTRL_MASK GENMASK(4, 2)
68 #define AD4691_REFBUF_EN BIT(0)
69 #define AD4691_OSC_FREQ_REG 0x023
70 #define AD4691_OSC_FREQ_MASK GENMASK(3, 0)
71 #define AD4691_STD_SEQ_CONFIG 0x025
72 #define AD4691_SEQ_ALL_CHANNELS_OFF 0x00
73 #define AD4691_SPARE_CONTROL 0x02A
74
75 #define AD4691_MAX_CHANNELS 16
76
77 #define AD4691_NOOP 0x00
78 #define AD4691_ADC_CHAN(ch) ((0x10 + (ch)) << 3)
79 #define AD4691_EXIT_COMMAND 0x5000
80
81 #define AD4691_OSC_EN_REG 0x180
82 #define AD4691_STATE_RESET_REG 0x181
83 #define AD4691_STATE_RESET_ALL BIT(0)
84 #define AD4691_ADC_SETUP 0x182
85 #define AD4691_ADC_MODE_MASK GENMASK(1, 0)
86 #define AD4691_CNV_BURST_MODE 0x01
87 #define AD4691_AUTONOMOUS_MODE 0x02
88 /*
89 * ACC_MASK_REG covers both mask bytes via ADDR_DESCENDING SPI: writing a
90 * 16-bit BE value to 0x185 auto-decrements to 0x184 for the second byte.
91 */
92 #define AD4691_ACC_MASK_REG 0x185
93 #define AD4691_ACC_DEPTH_IN(n) (0x186 + (n))
94 #define AD4691_GPIO_MODE1_REG 0x196
95 #define AD4691_GPIO_MODE2_REG 0x197
96 #define AD4691_GP_MODE_MASK GENMASK(3, 0)
97 #define AD4691_GP_MODE_DATA_READY 0x06
98 #define AD4691_GPIO_READ 0x1A0
99 #define AD4691_ACC_STATUS_FULL1_REG 0x1B0
100 #define AD4691_ACC_STATUS_FULL2_REG 0x1B1
101 #define AD4691_ACC_STATUS_OVERRUN1_REG 0x1B2
102 #define AD4691_ACC_STATUS_OVERRUN2_REG 0x1B3
103 #define AD4691_ACC_STATUS_SAT1_REG 0x1B4
104 #define AD4691_ACC_STATUS_SAT2_REG 0x1BE
105 #define AD4691_ACC_SAT_OVR_REG(n) (0x1C0 + (n))
106 #define AD4691_AVG_IN(n) (0x201 + (2 * (n)))
107 #define AD4691_AVG_STS_IN(n) (0x222 + (3 * (n)))
108 #define AD4691_ACC_IN(n) (0x252 + (3 * (n)))
109 #define AD4691_ACC_STS_DATA(n) (0x283 + (4 * (n)))
110
111
112 static const char * const ad4691_supplies[] = { "avdd", "vio" };
113
114 enum ad4691_ref_ctrl {
115 AD4691_VREF_2P5,
116 AD4691_VREF_3P0,
117 AD4691_VREF_3P3,
118 AD4691_VREF_4P096,
119 AD4691_VREF_5P0
120 };
121
122 struct ad4691_channel_info {
123 const struct iio_chan_spec *channels __counted_by_ptr(num_channels);
124 const struct iio_chan_spec *manual_channels __counted_by_ptr(num_channels);
125 unsigned int num_channels;
126 };
127
128 struct ad4691_chip_info {
129 const char *name;
130 unsigned int max_rate;
131 const struct ad4691_channel_info *sw_info;
132 const struct ad4691_channel_info *offload_info;
133 };
134
135 /* CNV burst mode channel — exposes oversampling ratio. */
136 #define AD4691_CHANNEL(ch) \
137 { \
138 .type = IIO_VOLTAGE, \
139 .indexed = 1, \
140 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
141 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \
142 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
143 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
144 .info_mask_shared_by_all_available = \
145 BIT(IIO_CHAN_INFO_SAMP_FREQ) \
146 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
147 .channel = ch, \
148 .scan_index = ch, \
149 .scan_type = { \
150 .format = 'u', \
151 .realbits = 16, \
152 .storagebits = 16, \
153 .endianness = IIO_BE, \
154 }, \
155 }
156
157 /*
158 * Manual mode channel — no oversampling ratio attribute. OSR is not
159 * supported in manual mode; ACC_DEPTH_IN is not configured during manual
160 * buffer enable.
161 */
162 #define AD4691_MANUAL_CHANNEL(ch) \
163 { \
164 .type = IIO_VOLTAGE, \
165 .indexed = 1, \
166 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
167 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \
168 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \
169 .info_mask_shared_by_all_available = \
170 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
171 .channel = ch, \
172 .scan_index = ch, \
173 .scan_type = { \
174 .format = 'u', \
175 .realbits = 16, \
176 .storagebits = 16, \
177 .endianness = IIO_BE, \
178 }, \
179 }
180
181 /*
182 * Offload path (bits_per_word=16): the SPI Engine assembles received
183 * bits into native 16-bit words before DMA, so samples are in
184 * CPU-native byte order (IIO_CPU). storagebits=16 matches the 16-bit
185 * DMA word size.
186 *
187 * CNV burst offload configures ACC_DEPTH_IN per channel, so the
188 * oversampling_ratio attribute is exposed. Manual offload does not;
189 * use AD4691_OFFLOAD_MANUAL_CHANNEL for that path.
190 */
191 #define AD4691_OFFLOAD_CHANNEL(ch) \
192 { \
193 .type = IIO_VOLTAGE, \
194 .indexed = 1, \
195 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
196 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \
197 | BIT(IIO_CHAN_INFO_SAMP_FREQ) \
198 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
199 .info_mask_shared_by_all_available = \
200 BIT(IIO_CHAN_INFO_SAMP_FREQ) \
201 | BIT(IIO_CHAN_INFO_OVERSAMPLING_RATIO), \
202 .channel = ch, \
203 .scan_index = ch, \
204 .scan_type = { \
205 .format = 'u', \
206 .realbits = 16, \
207 .storagebits = 16, \
208 }, \
209 }
210
211 /* Manual offload — same IIO_CPU layout but no oversampling_ratio attribute. */
212 #define AD4691_OFFLOAD_MANUAL_CHANNEL(ch) \
213 { \
214 .type = IIO_VOLTAGE, \
215 .indexed = 1, \
216 .info_mask_separate = BIT(IIO_CHAN_INFO_RAW), \
217 .info_mask_shared_by_all = BIT(IIO_CHAN_INFO_SCALE) \
218 | BIT(IIO_CHAN_INFO_SAMP_FREQ), \
219 .info_mask_shared_by_all_available = \
220 BIT(IIO_CHAN_INFO_SAMP_FREQ), \
221 .channel = ch, \
222 .scan_index = ch, \
223 .scan_type = { \
224 .format = 'u', \
225 .realbits = 16, \
226 .storagebits = 16, \
227 }, \
228 }
229
230 static const struct iio_chan_spec ad4691_channels[] = {
231 AD4691_CHANNEL(0),
232 AD4691_CHANNEL(1),
233 AD4691_CHANNEL(2),
234 AD4691_CHANNEL(3),
235 AD4691_CHANNEL(4),
236 AD4691_CHANNEL(5),
237 AD4691_CHANNEL(6),
238 AD4691_CHANNEL(7),
239 AD4691_CHANNEL(8),
240 AD4691_CHANNEL(9),
241 AD4691_CHANNEL(10),
242 AD4691_CHANNEL(11),
243 AD4691_CHANNEL(12),
244 AD4691_CHANNEL(13),
245 AD4691_CHANNEL(14),
246 AD4691_CHANNEL(15),
247 IIO_CHAN_SOFT_TIMESTAMP(16),
248 };
249
250 static const struct iio_chan_spec ad4693_channels[] = {
251 AD4691_CHANNEL(0),
252 AD4691_CHANNEL(1),
253 AD4691_CHANNEL(2),
254 AD4691_CHANNEL(3),
255 AD4691_CHANNEL(4),
256 AD4691_CHANNEL(5),
257 AD4691_CHANNEL(6),
258 AD4691_CHANNEL(7),
259 IIO_CHAN_SOFT_TIMESTAMP(8),
260 };
261
262 /*
263 * Offload channel arrays: no IIO_CHAN_SOFT_TIMESTAMP because DMA delivers
264 * data directly to userspace without a software timestamp.
265 */
266 static const struct iio_chan_spec ad4691_offload_channels[] = {
267 AD4691_OFFLOAD_CHANNEL(0),
268 AD4691_OFFLOAD_CHANNEL(1),
269 AD4691_OFFLOAD_CHANNEL(2),
270 AD4691_OFFLOAD_CHANNEL(3),
271 AD4691_OFFLOAD_CHANNEL(4),
272 AD4691_OFFLOAD_CHANNEL(5),
273 AD4691_OFFLOAD_CHANNEL(6),
274 AD4691_OFFLOAD_CHANNEL(7),
275 AD4691_OFFLOAD_CHANNEL(8),
276 AD4691_OFFLOAD_CHANNEL(9),
277 AD4691_OFFLOAD_CHANNEL(10),
278 AD4691_OFFLOAD_CHANNEL(11),
279 AD4691_OFFLOAD_CHANNEL(12),
280 AD4691_OFFLOAD_CHANNEL(13),
281 AD4691_OFFLOAD_CHANNEL(14),
282 AD4691_OFFLOAD_CHANNEL(15),
283 };
284
285 static const struct iio_chan_spec ad4693_offload_channels[] = {
286 AD4691_OFFLOAD_CHANNEL(0),
287 AD4691_OFFLOAD_CHANNEL(1),
288 AD4691_OFFLOAD_CHANNEL(2),
289 AD4691_OFFLOAD_CHANNEL(3),
290 AD4691_OFFLOAD_CHANNEL(4),
291 AD4691_OFFLOAD_CHANNEL(5),
292 AD4691_OFFLOAD_CHANNEL(6),
293 AD4691_OFFLOAD_CHANNEL(7),
294 };
295
296 static const struct iio_chan_spec ad4691_manual_channels[] = {
297 AD4691_MANUAL_CHANNEL(0),
298 AD4691_MANUAL_CHANNEL(1),
299 AD4691_MANUAL_CHANNEL(2),
300 AD4691_MANUAL_CHANNEL(3),
301 AD4691_MANUAL_CHANNEL(4),
302 AD4691_MANUAL_CHANNEL(5),
303 AD4691_MANUAL_CHANNEL(6),
304 AD4691_MANUAL_CHANNEL(7),
305 AD4691_MANUAL_CHANNEL(8),
306 AD4691_MANUAL_CHANNEL(9),
307 AD4691_MANUAL_CHANNEL(10),
308 AD4691_MANUAL_CHANNEL(11),
309 AD4691_MANUAL_CHANNEL(12),
310 AD4691_MANUAL_CHANNEL(13),
311 AD4691_MANUAL_CHANNEL(14),
312 AD4691_MANUAL_CHANNEL(15),
313 IIO_CHAN_SOFT_TIMESTAMP(16),
314 };
315
316 static const struct iio_chan_spec ad4693_manual_channels[] = {
317 AD4691_MANUAL_CHANNEL(0),
318 AD4691_MANUAL_CHANNEL(1),
319 AD4691_MANUAL_CHANNEL(2),
320 AD4691_MANUAL_CHANNEL(3),
321 AD4691_MANUAL_CHANNEL(4),
322 AD4691_MANUAL_CHANNEL(5),
323 AD4691_MANUAL_CHANNEL(6),
324 AD4691_MANUAL_CHANNEL(7),
325 IIO_CHAN_SOFT_TIMESTAMP(8),
326 };
327
328 static const struct iio_chan_spec ad4691_offload_manual_channels[] = {
329 AD4691_OFFLOAD_MANUAL_CHANNEL(0),
330 AD4691_OFFLOAD_MANUAL_CHANNEL(1),
331 AD4691_OFFLOAD_MANUAL_CHANNEL(2),
332 AD4691_OFFLOAD_MANUAL_CHANNEL(3),
333 AD4691_OFFLOAD_MANUAL_CHANNEL(4),
334 AD4691_OFFLOAD_MANUAL_CHANNEL(5),
335 AD4691_OFFLOAD_MANUAL_CHANNEL(6),
336 AD4691_OFFLOAD_MANUAL_CHANNEL(7),
337 AD4691_OFFLOAD_MANUAL_CHANNEL(8),
338 AD4691_OFFLOAD_MANUAL_CHANNEL(9),
339 AD4691_OFFLOAD_MANUAL_CHANNEL(10),
340 AD4691_OFFLOAD_MANUAL_CHANNEL(11),
341 AD4691_OFFLOAD_MANUAL_CHANNEL(12),
342 AD4691_OFFLOAD_MANUAL_CHANNEL(13),
343 AD4691_OFFLOAD_MANUAL_CHANNEL(14),
344 AD4691_OFFLOAD_MANUAL_CHANNEL(15),
345 };
346
347 static const struct iio_chan_spec ad4693_offload_manual_channels[] = {
348 AD4691_OFFLOAD_MANUAL_CHANNEL(0),
349 AD4691_OFFLOAD_MANUAL_CHANNEL(1),
350 AD4691_OFFLOAD_MANUAL_CHANNEL(2),
351 AD4691_OFFLOAD_MANUAL_CHANNEL(3),
352 AD4691_OFFLOAD_MANUAL_CHANNEL(4),
353 AD4691_OFFLOAD_MANUAL_CHANNEL(5),
354 AD4691_OFFLOAD_MANUAL_CHANNEL(6),
355 AD4691_OFFLOAD_MANUAL_CHANNEL(7),
356 };
357
358 static const int ad4691_oversampling_ratios[] = { 1, 2, 4, 8, 16, 32 };
359
360 static const struct ad4691_channel_info ad4691_sw_info = {
361 .channels = ad4691_channels,
362 .manual_channels = ad4691_manual_channels,
363 .num_channels = ARRAY_SIZE(ad4691_channels),
364 };
365
366 static const struct ad4691_channel_info ad4693_sw_info = {
367 .channels = ad4693_channels,
368 .manual_channels = ad4693_manual_channels,
369 .num_channels = ARRAY_SIZE(ad4693_channels),
370 };
371
372 static const struct ad4691_channel_info ad4691_offload_info = {
373 .channels = ad4691_offload_channels,
374 .manual_channels = ad4691_offload_manual_channels,
375 .num_channels = ARRAY_SIZE(ad4691_offload_channels),
376 };
377
378 static const struct ad4691_channel_info ad4693_offload_info = {
379 .channels = ad4693_offload_channels,
380 .manual_channels = ad4693_offload_manual_channels,
381 .num_channels = ARRAY_SIZE(ad4693_offload_channels),
382 };
383
384 /*
385 * Internal oscillator frequency table. Index is the OSC_FREQ_REG[3:0] value.
386 * Index 0 (1 MHz) is only valid for AD4692/AD4694; AD4691/AD4693 support
387 * up to 500 kHz and use index 1 as their highest valid rate.
388 */
389 static const int ad4691_osc_freqs_Hz[] = {
390 [0x0] = 1000000,
391 [0x1] = 500000,
392 [0x2] = 400000,
393 [0x3] = 250000,
394 [0x4] = 200000,
395 [0x5] = 167000,
396 [0x6] = 133000,
397 [0x7] = 125000,
398 [0x8] = 100000,
399 [0x9] = 50000,
400 [0xA] = 25000,
401 [0xB] = 12500,
402 [0xC] = 10000,
403 [0xD] = 5000,
404 [0xE] = 2500,
405 [0xF] = 1250,
406 };
407
408 static const char * const ad4691_gp_names[] = { "gp0", "gp1", "gp2", "gp3" };
409
410 static const struct ad4691_chip_info ad4691_chip_info = {
411 .name = "ad4691",
412 .max_rate = 500 * HZ_PER_KHZ,
413 .sw_info = &ad4691_sw_info,
414 .offload_info = &ad4691_offload_info,
415 };
416
417 static const struct ad4691_chip_info ad4692_chip_info = {
418 .name = "ad4692",
419 .max_rate = 1 * HZ_PER_MHZ,
420 .sw_info = &ad4691_sw_info,
421 .offload_info = &ad4691_offload_info,
422 };
423
424 static const struct ad4691_chip_info ad4693_chip_info = {
425 .name = "ad4693",
426 .max_rate = 500 * HZ_PER_KHZ,
427 .sw_info = &ad4693_sw_info,
428 .offload_info = &ad4693_offload_info,
429 };
430
431 static const struct ad4691_chip_info ad4694_chip_info = {
432 .name = "ad4694",
433 .max_rate = 1 * HZ_PER_MHZ,
434 .sw_info = &ad4693_sw_info,
435 .offload_info = &ad4693_offload_info,
436 };
437
438 struct ad4691_state {
439 const struct ad4691_chip_info *info;
440 struct regmap *regmap;
441 struct spi_device *spi;
442
443 struct pwm_device *conv_trigger;
444 int irq;
445 int vref_uV;
446 u32 cnv_period_ns;
447 /*
448 * Snapped oscillator frequency (Hz) shared by all channels. Set when
449 * sampling_frequency or oversampling_ratio is written; written to
450 * OSC_FREQ_REG at buffer enable and single-shot time so both attributes
451 * can be set in any order. Reading in_voltage_sampling_frequency
452 * returns target_osc_freq_Hz / osr — the effective rate given the
453 * shared oversampling ratio.
454 */
455 u32 target_osc_freq_Hz;
456 /* Shared oversampling ratio across all channels; always 1 in manual mode. */
457 unsigned int osr;
458 /*
459 * Precomputed effective-rate lists, one row per entry in
460 * ad4691_oversampling_ratios[]. Populated at probe; read_avail picks
461 * the row for the current shared OSR. The tables are stable after
462 * probe so returning a pointer into them from read_avail is race-free.
463 */
464 int samp_freq_avail[ARRAY_SIZE(ad4691_oversampling_ratios)][ARRAY_SIZE(ad4691_osc_freqs_Hz)];
465 int samp_freq_avail_len[ARRAY_SIZE(ad4691_oversampling_ratios)];
466
467 bool manual_mode;
468 bool irq_enabled;
469 bool refbuf_en;
470 bool ldo_en;
471 /*
472 * Synchronize access to members of the driver state, and ensure
473 * atomicity of consecutive SPI operations.
474 */
475 struct mutex lock;
476 /* NULL when no SPI offload hardware is present. */
477 struct spi_offload *offload;
478 struct spi_offload_trigger *offload_trigger;
479 u64 trigger_hz;
480 /*
481 * Per-buffer-enable lifetime resources:
482 * Manual Mode - a pre-built SPI message that clocks out N+1
483 * transfers in one go.
484 * CNV Burst Mode - a pre-built SPI message that clocks out 2*N
485 * transfers in one go.
486 */
487 struct spi_message scan_msg;
488 /*
489 * max 16 + 1 NOOP (manual) or 2*16 + 1 state-reset (CNV burst).
490 */
491 struct spi_transfer scan_xfers[34];
492 /*
493 * CNV burst: 16 AVG_IN addresses = 16. Manual: 16 channel cmds +
494 * 1 NOOP = 17. Stored as native u16. The non-offload path fills slots
495 * with put_unaligned_be16() (bits_per_word=8, bytes go out in memory
496 * order). The offload path assigns native values directly
497 * (bits_per_word=bpw, SPI reads each slot as a native 16-bit word and
498 * shifts it out MSB-first).
499 */
500 u16 scan_tx[17] __aligned(IIO_DMA_MINALIGN);
501 /*
502 * CNV burst state-reset: 4-byte write [addr_hi, addr_lo,
503 * STATE_RESET_ALL, OSC_EN=1]. CS is asserted throughout, so
504 * ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as a
505 * deliberate side-write, keeping the oscillator enabled. Shared
506 * with the offload path (mutually exclusive at probe).
507 */
508 u8 scan_tx_reset[4] __aligned(IIO_DMA_MINALIGN);
509 /*
510 * Scan buffer: one BE16 slot per active channel, plus timestamp.
511 * DMA-aligned because scan_xfers point rx_buf directly into vals[].
512 */
513 IIO_DECLARE_DMA_BUFFER_WITH_TS(__be16, vals, 16);
514 };
515
516 /*
517 * Configure the given GP pin (0-3) as DATA_READY output.
518 * GP0/GP1 → GPIO_MODE1_REG, GP2/GP3 → GPIO_MODE2_REG.
519 * Even pins occupy bits [3:0], odd pins bits [7:4].
520 */
ad4691_gpio_setup(struct ad4691_state * st,unsigned int gp_num)521 static int ad4691_gpio_setup(struct ad4691_state *st, unsigned int gp_num)
522 {
523 unsigned int bit_off = gp_num % 2;
524 unsigned int reg_off = gp_num / 2;
525 unsigned int shift = 4 * bit_off;
526
527 return regmap_update_bits(st->regmap,
528 AD4691_GPIO_MODE1_REG + reg_off,
529 AD4691_GP_MODE_MASK << shift,
530 AD4691_GP_MODE_DATA_READY << shift);
531 }
532
533 static const struct spi_offload_config ad4691_offload_config = {
534 .capability_flags = SPI_OFFLOAD_CAP_TRIGGER |
535 SPI_OFFLOAD_CAP_RX_STREAM_DMA,
536 };
537
ad4691_offload_trigger_match(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)538 static bool ad4691_offload_trigger_match(struct spi_offload_trigger *trigger,
539 enum spi_offload_trigger_type type,
540 u64 *args, u32 nargs)
541 {
542 return type == SPI_OFFLOAD_TRIGGER_DATA_READY && nargs == 1 && args[0] <= 3;
543 }
544
ad4691_offload_trigger_request(struct spi_offload_trigger * trigger,enum spi_offload_trigger_type type,u64 * args,u32 nargs)545 static int ad4691_offload_trigger_request(struct spi_offload_trigger *trigger,
546 enum spi_offload_trigger_type type,
547 u64 *args, u32 nargs)
548 {
549 struct ad4691_state *st = spi_offload_trigger_get_priv(trigger);
550
551 if (nargs != 1 || args[0] > 3)
552 return -EINVAL;
553
554 return ad4691_gpio_setup(st, args[0]);
555 }
556
ad4691_offload_trigger_validate(struct spi_offload_trigger * trigger,struct spi_offload_trigger_config * config)557 static int ad4691_offload_trigger_validate(struct spi_offload_trigger *trigger,
558 struct spi_offload_trigger_config *config)
559 {
560 if (config->type != SPI_OFFLOAD_TRIGGER_DATA_READY)
561 return -EINVAL;
562
563 return 0;
564 }
565
566 static const struct spi_offload_trigger_ops ad4691_offload_trigger_ops = {
567 .match = ad4691_offload_trigger_match,
568 .request = ad4691_offload_trigger_request,
569 .validate = ad4691_offload_trigger_validate,
570 };
571
ad4691_reg_read(void * context,unsigned int reg,unsigned int * val)572 static int ad4691_reg_read(void *context, unsigned int reg, unsigned int *val)
573 {
574 struct spi_device *spi = context;
575 u8 tx[2], rx[4];
576 int ret;
577
578 /* Set bit 15 to mark the operation as READ. */
579 put_unaligned_be16(0x8000 | reg, tx);
580
581 switch (reg) {
582 case 0 ... AD4691_OSC_FREQ_REG:
583 case AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1:
584 case AD4691_ACC_MASK_REG + 1 ... AD4691_ACC_SAT_OVR_REG(15):
585 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 1);
586 if (ret)
587 return ret;
588 *val = rx[0];
589 return 0;
590 case AD4691_ACC_MASK_REG:
591 case AD4691_STD_SEQ_CONFIG:
592 case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15):
593 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 2);
594 if (ret)
595 return ret;
596 *val = get_unaligned_be16(rx);
597 return 0;
598 case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15):
599 case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15):
600 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 3);
601 if (ret)
602 return ret;
603 *val = get_unaligned_be24(rx);
604 return 0;
605 case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15):
606 ret = spi_write_then_read(spi, tx, sizeof(tx), rx, 4);
607 if (ret)
608 return ret;
609 *val = get_unaligned_be32(rx);
610 return 0;
611 default:
612 return -EINVAL;
613 }
614 }
615
ad4691_reg_write(void * context,unsigned int reg,unsigned int val)616 static int ad4691_reg_write(void *context, unsigned int reg, unsigned int val)
617 {
618 struct spi_device *spi = context;
619 u8 tx[4];
620
621 put_unaligned_be16(reg, tx);
622
623 switch (reg) {
624 case 0 ... AD4691_OSC_FREQ_REG:
625 case AD4691_SPARE_CONTROL ... AD4691_ACC_MASK_REG - 1:
626 case AD4691_ACC_MASK_REG + 1 ... AD4691_GPIO_MODE2_REG:
627 if (val > U8_MAX)
628 return -EINVAL;
629 tx[2] = val;
630 return spi_write_then_read(spi, tx, 3, NULL, 0);
631 case AD4691_ACC_MASK_REG:
632 case AD4691_STD_SEQ_CONFIG:
633 if (val > U16_MAX)
634 return -EINVAL;
635 put_unaligned_be16(val, &tx[2]);
636 return spi_write_then_read(spi, tx, 4, NULL, 0);
637 default:
638 return -EINVAL;
639 }
640 }
641
ad4691_volatile_reg(struct device * dev,unsigned int reg)642 static bool ad4691_volatile_reg(struct device *dev, unsigned int reg)
643 {
644 switch (reg) {
645 case AD4691_STATUS_REG:
646 case AD4691_CLAMP_STATUS1_REG:
647 case AD4691_CLAMP_STATUS2_REG:
648 case AD4691_GPIO_READ:
649 case AD4691_ACC_STATUS_FULL1_REG ... AD4691_ACC_STATUS_SAT2_REG:
650 case AD4691_ACC_SAT_OVR_REG(0) ... AD4691_ACC_SAT_OVR_REG(15):
651 case AD4691_AVG_IN(0) ... AD4691_AVG_IN(15):
652 case AD4691_AVG_STS_IN(0) ... AD4691_AVG_STS_IN(15):
653 case AD4691_ACC_IN(0) ... AD4691_ACC_IN(15):
654 case AD4691_ACC_STS_DATA(0) ... AD4691_ACC_STS_DATA(15):
655 return true;
656 default:
657 return false;
658 }
659 }
660
ad4691_readable_reg(struct device * dev,unsigned int reg)661 static bool ad4691_readable_reg(struct device *dev, unsigned int reg)
662 {
663 switch (reg) {
664 case 0 ... AD4691_OSC_FREQ_REG:
665 case AD4691_SPARE_CONTROL ... AD4691_ACC_SAT_OVR_REG(15):
666 case AD4691_STD_SEQ_CONFIG:
667 return true;
668 default:
669 break;
670 }
671
672 /*
673 * Multi-byte result registers have non-unit strides; only the base
674 * address of each entry is a valid single-register read.
675 */
676 if (reg >= AD4691_AVG_IN(0) && reg <= AD4691_AVG_IN(15))
677 return (reg - AD4691_AVG_IN(0)) % 2 == 0;
678 if (reg >= AD4691_AVG_STS_IN(0) && reg <= AD4691_AVG_STS_IN(15))
679 return (reg - AD4691_AVG_STS_IN(0)) % 3 == 0;
680 if (reg >= AD4691_ACC_IN(0) && reg <= AD4691_ACC_IN(15))
681 return (reg - AD4691_ACC_IN(0)) % 3 == 0;
682 if (reg >= AD4691_ACC_STS_DATA(0) && reg <= AD4691_ACC_STS_DATA(15))
683 return (reg - AD4691_ACC_STS_DATA(0)) % 4 == 0;
684
685 return false;
686 }
687
ad4691_writeable_reg(struct device * dev,unsigned int reg)688 static bool ad4691_writeable_reg(struct device *dev, unsigned int reg)
689 {
690 switch (reg) {
691 case 0 ... AD4691_OSC_FREQ_REG:
692 case AD4691_STD_SEQ_CONFIG:
693 case AD4691_SPARE_CONTROL ... AD4691_GPIO_MODE2_REG:
694 return true;
695 default:
696 return false;
697 }
698 }
699
700 static const struct regmap_config ad4691_regmap_config = {
701 .reg_bits = 16,
702 .val_bits = 32,
703 .reg_read = ad4691_reg_read,
704 .reg_write = ad4691_reg_write,
705 .volatile_reg = ad4691_volatile_reg,
706 .readable_reg = ad4691_readable_reg,
707 .writeable_reg = ad4691_writeable_reg,
708 .max_register = AD4691_ACC_STS_DATA(15),
709 .cache_type = REGCACHE_MAPLE,
710 };
711
712 /*
713 * Index 0 in ad4691_osc_freqs_Hz is 1 MHz — valid only for AD4692/AD4694
714 * (max_rate == 1 MHz). AD4691/AD4693 cap at 500 kHz so their valid range
715 * starts at index 1.
716 */
ad4691_samp_freq_start(const struct ad4691_chip_info * info)717 static unsigned int ad4691_samp_freq_start(const struct ad4691_chip_info *info)
718 {
719 return (info->max_rate == 1 * HZ_PER_MHZ) ? 0 : 1;
720 }
721
722 /*
723 * Find the largest oscillator table entry that is both <= needed_osc and
724 * evenly divisible by osr (guaranteeing an integer effective rate on
725 * read-back). Returns 0 if no such entry exists in the chip's valid range.
726 */
ad4691_find_osc_freq(struct ad4691_state * st,unsigned int needed_osc,unsigned int osr)727 static unsigned int ad4691_find_osc_freq(struct ad4691_state *st,
728 unsigned int needed_osc,
729 unsigned int osr)
730 {
731 unsigned int start = ad4691_samp_freq_start(st->info);
732
733 for (unsigned int i = start; i < ARRAY_SIZE(ad4691_osc_freqs_Hz); i++) {
734 if ((unsigned int)ad4691_osc_freqs_Hz[i] > needed_osc)
735 continue;
736 if (ad4691_osc_freqs_Hz[i] % osr)
737 continue;
738 return ad4691_osc_freqs_Hz[i];
739 }
740 return 0;
741 }
742
743 /* Write target_osc_freq_Hz to OSC_FREQ_REG. Called at use time. */
ad4691_write_osc_freq(struct ad4691_state * st)744 static int ad4691_write_osc_freq(struct ad4691_state *st)
745 {
746 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_osc_freqs_Hz); i++) {
747 if (ad4691_osc_freqs_Hz[i] == st->target_osc_freq_Hz)
748 return regmap_write(st->regmap, AD4691_OSC_FREQ_REG, i);
749 }
750 return -EINVAL;
751 }
752
753 /* Return the index of osr in ad4691_oversampling_ratios[], defaulting to 0. */
ad4691_osr_index(unsigned int osr)754 static unsigned int ad4691_osr_index(unsigned int osr)
755 {
756 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_oversampling_ratios) - 1; i++) {
757 if ((unsigned int)ad4691_oversampling_ratios[i] == osr)
758 return i;
759 }
760 return ARRAY_SIZE(ad4691_oversampling_ratios) - 1;
761 }
762
763 /*
764 * Precompute samp_freq_avail[][]: for each OSR value, list the oscillator
765 * table entries that divide evenly by that OSR, expressed as effective rates
766 * (osc_freq / osr). Called once at probe after st->info is set.
767 */
ad4691_precompute_samp_freq_avail(struct ad4691_state * st)768 static void ad4691_precompute_samp_freq_avail(struct ad4691_state *st)
769 {
770 unsigned int start = ad4691_samp_freq_start(st->info);
771
772 for (unsigned int i = 0; i < ARRAY_SIZE(ad4691_oversampling_ratios); i++) {
773 unsigned int osr = ad4691_oversampling_ratios[i];
774 int n = 0;
775
776 for (unsigned int j = start; j < ARRAY_SIZE(ad4691_osc_freqs_Hz); j++) {
777 if (ad4691_osc_freqs_Hz[j] % osr)
778 continue;
779 st->samp_freq_avail[i][n++] = ad4691_osc_freqs_Hz[j] / osr;
780 }
781 st->samp_freq_avail_len[i] = n;
782 }
783 }
784
ad4691_set_sampling_freq(struct ad4691_state * st,int freq)785 static int ad4691_set_sampling_freq(struct ad4691_state *st, int freq)
786 {
787 unsigned int osr, found;
788
789 /*
790 * Read osr under st->lock: osr and target_osc_freq_Hz are modified
791 * together under the lock; reading after acquiring it ensures we see
792 * a consistent snapshot with no concurrent write racing us.
793 */
794 guard(mutex)(&st->lock);
795 osr = st->osr;
796
797 if (freq <= 0 || (unsigned int)freq > st->info->max_rate / osr)
798 return -EINVAL;
799
800 found = ad4691_find_osc_freq(st, (unsigned int)freq * osr, osr);
801 if (!found)
802 return -EINVAL;
803
804 /*
805 * Store the snapped oscillator frequency; OSC_FREQ_REG is written at
806 * buffer enable and single-shot time so that sampling_frequency and
807 * oversampling_ratio can be set in any order.
808 */
809 st->target_osc_freq_Hz = found;
810 return 0;
811 }
812
ad4691_read_avail(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,const int ** vals,int * type,int * length,long mask)813 static int ad4691_read_avail(struct iio_dev *indio_dev,
814 struct iio_chan_spec const *chan,
815 const int **vals, int *type,
816 int *length, long mask)
817 {
818 struct ad4691_state *st = iio_priv(indio_dev);
819
820 switch (mask) {
821 case IIO_CHAN_INFO_SAMP_FREQ: {
822 unsigned int osr_idx;
823
824 /*
825 * The precomputed tables are stable after probe; only the
826 * current OSR needs to be read under the lock to pick the
827 * right row atomically.
828 */
829 guard(mutex)(&st->lock);
830 osr_idx = ad4691_osr_index(st->osr);
831 *vals = st->samp_freq_avail[osr_idx];
832 *type = IIO_VAL_INT;
833 *length = st->samp_freq_avail_len[osr_idx];
834 return IIO_AVAIL_LIST;
835 }
836 case IIO_CHAN_INFO_OVERSAMPLING_RATIO:
837 *vals = ad4691_oversampling_ratios;
838 *type = IIO_VAL_INT;
839 *length = ARRAY_SIZE(ad4691_oversampling_ratios);
840 return IIO_AVAIL_LIST;
841 default:
842 return -EINVAL;
843 }
844 }
845
ad4691_single_shot_read(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val)846 static int ad4691_single_shot_read(struct iio_dev *indio_dev,
847 struct iio_chan_spec const *chan, int *val)
848 {
849 struct ad4691_state *st = iio_priv(indio_dev);
850 unsigned int reg_val, period_us;
851 int ret;
852
853 guard(mutex)(&st->lock);
854
855 /* Use AUTONOMOUS mode for single-shot reads. */
856 ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL);
857 if (ret)
858 return ret;
859
860 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG,
861 BIT(chan->channel));
862 if (ret)
863 return ret;
864
865 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG,
866 ~BIT(chan->channel) & GENMASK(15, 0));
867 if (ret)
868 return ret;
869
870 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr);
871 if (ret)
872 return ret;
873
874 ret = ad4691_write_osc_freq(st);
875 if (ret)
876 return ret;
877
878 ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 1);
879 if (ret)
880 return ret;
881
882 /*
883 * Wait osr + 1 oscillator periods: osr for accumulation, +1 for the
884 * pipeline margin (one extra period ensures the final result is ready).
885 */
886 period_us = DIV_ROUND_UP((st->osr + 1) * USEC_PER_SEC,
887 st->target_osc_freq_Hz);
888 fsleep(period_us);
889
890 ret = regmap_write(st->regmap, AD4691_OSC_EN_REG, 0);
891 if (ret)
892 return ret;
893
894 ret = regmap_read(st->regmap, AD4691_AVG_IN(chan->channel), ®_val);
895 if (ret)
896 return ret;
897
898 *val = reg_val;
899
900 ret = regmap_write(st->regmap, AD4691_STATE_RESET_REG, AD4691_STATE_RESET_ALL);
901 if (ret)
902 return ret;
903
904 return IIO_VAL_INT;
905 }
906
ad4691_read_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int * val,int * val2,long info)907 static int ad4691_read_raw(struct iio_dev *indio_dev,
908 struct iio_chan_spec const *chan, int *val,
909 int *val2, long info)
910 {
911 struct ad4691_state *st = iio_priv(indio_dev);
912
913 switch (info) {
914 case IIO_CHAN_INFO_RAW: {
915 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
916 if (IIO_DEV_ACQUIRE_FAILED(claim))
917 return -EBUSY;
918
919 return ad4691_single_shot_read(indio_dev, chan, val);
920 }
921 case IIO_CHAN_INFO_SAMP_FREQ: {
922 /*
923 * Read target_osc_freq_Hz and osr under st->lock to get a
924 * consistent snapshot: write_raw for SAMP_FREQ or OSR modifies
925 * both fields under the lock, so a concurrent read without the
926 * lock could observe a new oscillator frequency with the old OSR.
927 */
928 guard(mutex)(&st->lock);
929 *val = st->target_osc_freq_Hz / st->osr;
930 return IIO_VAL_INT;
931 }
932 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: {
933 guard(mutex)(&st->lock);
934 *val = st->osr;
935 return IIO_VAL_INT;
936 }
937 case IIO_CHAN_INFO_SCALE:
938 *val = st->vref_uV / (MICRO / MILLI);
939 *val2 = chan->scan_type.realbits;
940 return IIO_VAL_FRACTIONAL_LOG2;
941 default:
942 return -EINVAL;
943 }
944 }
945
ad4691_write_raw(struct iio_dev * indio_dev,struct iio_chan_spec const * chan,int val,int val2,long mask)946 static int ad4691_write_raw(struct iio_dev *indio_dev,
947 struct iio_chan_spec const *chan,
948 int val, int val2, long mask)
949 {
950 struct ad4691_state *st = iio_priv(indio_dev);
951
952 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
953 if (IIO_DEV_ACQUIRE_FAILED(claim))
954 return -EBUSY;
955
956 switch (mask) {
957 case IIO_CHAN_INFO_SAMP_FREQ:
958 return ad4691_set_sampling_freq(st, val);
959 case IIO_CHAN_INFO_OVERSAMPLING_RATIO: {
960 unsigned int old_effective, found, osr_idx;
961
962 osr_idx = ad4691_osr_index(val);
963 if (ad4691_oversampling_ratios[osr_idx] != val)
964 return -EINVAL;
965
966 /*
967 * Hold st->lock while computing the new oscillator frequency
968 * and updating both target_osc_freq_Hz and osr atomically:
969 * read_raw for SAMP_FREQ reads both fields under the lock and
970 * must see a consistent pair (new osc ↔ new osr).
971 *
972 * Snap target_osc_freq_Hz to the largest table entry that is
973 * both <= old_effective * new_osr and evenly divisible by
974 * new_osr, preserving an integer read-back of
975 * in_voltage_sampling_frequency after the OSR change.
976 */
977 guard(mutex)(&st->lock);
978 old_effective = st->target_osc_freq_Hz / st->osr;
979 found = ad4691_find_osc_freq(st, old_effective * (unsigned int)val, val);
980 if (!found)
981 return -EINVAL;
982 st->target_osc_freq_Hz = found;
983 st->osr = val;
984 return 0;
985 }
986 default:
987 return -EINVAL;
988 }
989 }
990
ad4691_reg_access(struct iio_dev * indio_dev,unsigned int reg,unsigned int writeval,unsigned int * readval)991 static int ad4691_reg_access(struct iio_dev *indio_dev, unsigned int reg,
992 unsigned int writeval, unsigned int *readval)
993 {
994 struct ad4691_state *st = iio_priv(indio_dev);
995
996 guard(mutex)(&st->lock);
997
998 if (readval)
999 return regmap_read(st->regmap, reg, readval);
1000
1001 return regmap_write(st->regmap, reg, writeval);
1002 }
1003
ad4691_set_pwm_freq(struct ad4691_state * st,unsigned int freq)1004 static int ad4691_set_pwm_freq(struct ad4691_state *st, unsigned int freq)
1005 {
1006 if (!freq)
1007 return -EINVAL;
1008
1009 st->cnv_period_ns = DIV_ROUND_UP(NSEC_PER_SEC, freq);
1010 return 0;
1011 }
1012
ad4691_sampling_enable(struct ad4691_state * st,bool enable)1013 static int ad4691_sampling_enable(struct ad4691_state *st, bool enable)
1014 {
1015 struct pwm_state conv_state = {
1016 .period = st->cnv_period_ns,
1017 .duty_cycle = AD4691_CNV_DUTY_CYCLE_NS,
1018 .polarity = PWM_POLARITY_NORMAL,
1019 .enabled = enable,
1020 };
1021
1022 return pwm_apply_might_sleep(st->conv_trigger, &conv_state);
1023 }
1024
1025 /*
1026 * ad4691_enter_conversion_mode - Switch the chip to its buffer conversion mode.
1027 *
1028 * Configures the ADC hardware registers for the mode selected at probe
1029 * (CNV_BURST or MANUAL). Called from buffer preenable before starting
1030 * sampling. The chip is in AUTONOMOUS mode during idle (for read_raw).
1031 */
ad4691_enter_conversion_mode(struct ad4691_state * st)1032 static int ad4691_enter_conversion_mode(struct ad4691_state *st)
1033 {
1034 int ret;
1035
1036 if (st->manual_mode)
1037 return regmap_update_bits(st->regmap, AD4691_DEVICE_SETUP,
1038 AD4691_MANUAL_MODE, AD4691_MANUAL_MODE);
1039
1040 ret = ad4691_write_osc_freq(st);
1041 if (ret)
1042 return ret;
1043
1044 ret = regmap_update_bits(st->regmap, AD4691_ADC_SETUP,
1045 AD4691_ADC_MODE_MASK, AD4691_CNV_BURST_MODE);
1046 if (ret)
1047 return ret;
1048
1049 return regmap_write(st->regmap, AD4691_STATE_RESET_REG,
1050 AD4691_STATE_RESET_ALL);
1051 }
1052
ad4691_transfer(struct ad4691_state * st,u16 cmd)1053 static int ad4691_transfer(struct ad4691_state *st, u16 cmd)
1054 {
1055 u8 buf[2];
1056
1057 put_unaligned_be16(cmd, buf);
1058
1059 return spi_write_then_read(st->spi, buf, sizeof(buf), NULL, 0);
1060 }
1061
1062 /*
1063 * ad4691_exit_conversion_mode - Return the chip to AUTONOMOUS mode.
1064 *
1065 * Called from buffer postdisable to restore the chip to the
1066 * idle state used by read_raw. Clears the sequencer and resets state.
1067 */
ad4691_exit_conversion_mode(struct ad4691_state * st)1068 static int ad4691_exit_conversion_mode(struct ad4691_state *st)
1069 {
1070 if (st->manual_mode)
1071 return ad4691_transfer(st, AD4691_EXIT_COMMAND);
1072
1073 return regmap_update_bits(st->regmap, AD4691_ADC_SETUP,
1074 AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE);
1075 }
1076
ad4691_manual_buffer_preenable(struct iio_dev * indio_dev)1077 static int ad4691_manual_buffer_preenable(struct iio_dev *indio_dev)
1078 {
1079 struct ad4691_state *st = iio_priv(indio_dev);
1080 unsigned int k, i;
1081 int ret;
1082
1083 memset(st->scan_xfers, 0, sizeof(st->scan_xfers));
1084 memset(st->scan_tx, 0, sizeof(st->scan_tx));
1085
1086 spi_message_init(&st->scan_msg);
1087
1088 k = 0;
1089 iio_for_each_active_channel(indio_dev, i) {
1090 /*
1091 * Channel-select command occupies the first (high) byte of the
1092 * 16-bit DIN frame; the second byte is a don't-care zero pad.
1093 * put_unaligned_be16() writes [cmd, 0x00] in memory so the
1094 * SPI controller sends the command byte first on the wire.
1095 */
1096 put_unaligned_be16((u16)(AD4691_ADC_CHAN(i) << 8), &st->scan_tx[k]);
1097 st->scan_xfers[k].tx_buf = &st->scan_tx[k];
1098 /*
1099 * The pipeline means xfer[0] receives the residual from the
1100 * previous sequence, not a valid sample. Discard it (rx_buf=NULL)
1101 * to avoid aliasing vals[0] across two concurrent DMA mappings.
1102 * xfer[1] (or the NOOP when only one channel is active) writes
1103 * the real ch[0] result to vals[0]. Subsequent transfers write
1104 * into vals[k-1] so each result lands at the next dense slot.
1105 */
1106 st->scan_xfers[k].rx_buf = (k == 0) ? NULL : &st->vals[k - 1];
1107 st->scan_xfers[k].len = sizeof(*st->scan_tx);
1108 st->scan_xfers[k].cs_change = 1;
1109 st->scan_xfers[k].cs_change_delay.value = AD4691_CNV_HIGH_TIME_NS;
1110 st->scan_xfers[k].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1111 spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg);
1112 k++;
1113 }
1114
1115 /* Final NOOP transfer retrieves the last channel's result. */
1116 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; /* scan_tx[k] == 0 == NOOP */
1117 st->scan_xfers[k].rx_buf = &st->vals[k - 1];
1118 st->scan_xfers[k].len = sizeof(*st->scan_tx);
1119 spi_message_add_tail(&st->scan_xfers[k], &st->scan_msg);
1120
1121 ret = spi_optimize_message(st->spi, &st->scan_msg);
1122 if (ret)
1123 return ret;
1124
1125 ret = ad4691_enter_conversion_mode(st);
1126 if (ret) {
1127 spi_unoptimize_message(&st->scan_msg);
1128 return ret;
1129 }
1130
1131 return 0;
1132 }
1133
ad4691_manual_buffer_postdisable(struct iio_dev * indio_dev)1134 static int ad4691_manual_buffer_postdisable(struct iio_dev *indio_dev)
1135 {
1136 struct ad4691_state *st = iio_priv(indio_dev);
1137 int ret;
1138
1139 ret = ad4691_exit_conversion_mode(st);
1140 spi_unoptimize_message(&st->scan_msg);
1141 return ret;
1142 }
1143
1144 static const struct iio_buffer_setup_ops ad4691_manual_buffer_setup_ops = {
1145 .preenable = ad4691_manual_buffer_preenable,
1146 .postdisable = ad4691_manual_buffer_postdisable,
1147 };
1148
ad4691_cnv_burst_buffer_preenable(struct iio_dev * indio_dev)1149 static int ad4691_cnv_burst_buffer_preenable(struct iio_dev *indio_dev)
1150 {
1151 struct ad4691_state *st = iio_priv(indio_dev);
1152 unsigned int acc_mask, std_seq_config;
1153 unsigned int k, i;
1154 int ret;
1155
1156 memset(st->scan_xfers, 0, sizeof(st->scan_xfers));
1157 memset(st->scan_tx, 0, sizeof(st->scan_tx));
1158
1159 spi_message_init(&st->scan_msg);
1160
1161 /*
1162 * Each AVG_IN read needs two transfers: a 2-byte address write phase
1163 * followed by a 2-byte data read phase. CS toggles between channels
1164 * (cs_change=1 on the read phase of all but the last channel).
1165 */
1166 k = 0;
1167 iio_for_each_active_channel(indio_dev, i) {
1168 put_unaligned_be16(0x8000 | AD4691_AVG_IN(i), &st->scan_tx[k]);
1169 st->scan_xfers[2 * k].tx_buf = &st->scan_tx[k];
1170 st->scan_xfers[2 * k].len = sizeof(*st->scan_tx);
1171 spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg);
1172 st->scan_xfers[2 * k + 1].rx_buf = &st->vals[k];
1173 st->scan_xfers[2 * k + 1].len = sizeof(*st->scan_tx);
1174 st->scan_xfers[2 * k + 1].cs_change = 1;
1175 spi_message_add_tail(&st->scan_xfers[2 * k + 1], &st->scan_msg);
1176 k++;
1177 }
1178
1179 /*
1180 * Append a 4-byte state-reset transfer [addr_hi, addr_lo,
1181 * STATE_RESET_ALL, OSC_EN=1]. CS is asserted throughout, so
1182 * ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as a
1183 * deliberate side-write, keeping the oscillator enabled.
1184 * STATE_RESET_ALL starts the next burst; the hardware does not
1185 * accumulate new conversions until after a STATE_RESET pulse, so
1186 * no in-progress data is lost. No cs_change here — CS must
1187 * deassert normally at end of message to frame the next command.
1188 */
1189 put_unaligned_be16(AD4691_STATE_RESET_REG, st->scan_tx_reset);
1190 st->scan_tx_reset[2] = AD4691_STATE_RESET_ALL;
1191 st->scan_tx_reset[3] = 1;
1192 st->scan_xfers[2 * k].tx_buf = st->scan_tx_reset;
1193 st->scan_xfers[2 * k].len = sizeof(st->scan_tx_reset);
1194 spi_message_add_tail(&st->scan_xfers[2 * k], &st->scan_msg);
1195
1196 ret = spi_optimize_message(st->spi, &st->scan_msg);
1197 if (ret)
1198 return ret;
1199
1200 std_seq_config = bitmap_read(indio_dev->active_scan_mask, 0,
1201 iio_get_masklength(indio_dev)) & GENMASK(15, 0);
1202 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, std_seq_config);
1203 if (ret)
1204 goto err_unoptimize;
1205
1206 acc_mask = ~std_seq_config & GENMASK(15, 0);
1207 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG, acc_mask);
1208 if (ret)
1209 goto err_unoptimize;
1210
1211 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr);
1212 if (ret)
1213 goto err_unoptimize;
1214
1215 ret = ad4691_enter_conversion_mode(st);
1216 if (ret)
1217 goto err_unoptimize;
1218
1219 return 0;
1220
1221 err_unoptimize:
1222 spi_unoptimize_message(&st->scan_msg);
1223 return ret;
1224 }
1225
ad4691_cnv_burst_buffer_postenable(struct iio_dev * indio_dev)1226 static int ad4691_cnv_burst_buffer_postenable(struct iio_dev *indio_dev)
1227 {
1228 struct ad4691_state *st = iio_priv(indio_dev);
1229 int ret;
1230
1231 /*
1232 * Start the PWM and unmask the IRQ here in postenable, not in
1233 * preenable. The IIO core attaches the trigger poll function between
1234 * preenable and postenable; enabling sampling or unmasking the IRQ
1235 * before that point risks a DATA_READY assertion landing before the
1236 * poll function is registered. iio_trigger_poll() would drop the
1237 * event, disable_irq_nosync() would fire, and enable_irq() would
1238 * never be called, leaving the IRQ permanently masked.
1239 */
1240 ret = ad4691_sampling_enable(st, true);
1241 if (ret)
1242 return ret;
1243
1244 enable_irq(st->irq);
1245 st->irq_enabled = true;
1246 return 0;
1247 }
1248
ad4691_cnv_burst_buffer_predisable(struct iio_dev * indio_dev)1249 static int ad4691_cnv_burst_buffer_predisable(struct iio_dev *indio_dev)
1250 {
1251 struct ad4691_state *st = iio_priv(indio_dev);
1252
1253 if (st->irq_enabled) {
1254 disable_irq(st->irq);
1255 st->irq_enabled = false;
1256 }
1257 return ad4691_sampling_enable(st, false);
1258 }
1259
ad4691_cnv_burst_buffer_postdisable(struct iio_dev * indio_dev)1260 static int ad4691_cnv_burst_buffer_postdisable(struct iio_dev *indio_dev)
1261 {
1262 struct ad4691_state *st = iio_priv(indio_dev);
1263 int ret;
1264
1265 ret = ad4691_exit_conversion_mode(st);
1266 spi_unoptimize_message(&st->scan_msg);
1267 return ret;
1268 }
1269
1270 static const struct iio_buffer_setup_ops ad4691_cnv_burst_buffer_setup_ops = {
1271 .preenable = ad4691_cnv_burst_buffer_preenable,
1272 .postenable = ad4691_cnv_burst_buffer_postenable,
1273 .predisable = ad4691_cnv_burst_buffer_predisable,
1274 .postdisable = ad4691_cnv_burst_buffer_postdisable,
1275 };
1276
ad4691_manual_offload_buffer_postenable(struct iio_dev * indio_dev)1277 static int ad4691_manual_offload_buffer_postenable(struct iio_dev *indio_dev)
1278 {
1279 struct ad4691_state *st = iio_priv(indio_dev);
1280 struct device *dev = regmap_get_device(st->regmap);
1281 struct spi_device *spi = to_spi_device(dev);
1282 struct spi_offload_trigger_config config = {
1283 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
1284 };
1285 unsigned int bpw = indio_dev->channels[0].scan_type.realbits;
1286 unsigned int bit, k;
1287 int ret;
1288
1289 ret = ad4691_enter_conversion_mode(st);
1290 if (ret)
1291 return ret;
1292
1293 memset(st->scan_xfers, 0, sizeof(st->scan_xfers));
1294 memset(st->scan_tx, 0, sizeof(st->scan_tx));
1295
1296 /*
1297 * N+1 transfers for N channels. Each CS-low period triggers
1298 * a conversion AND returns the previous result (pipelined).
1299 * TX: [AD4691_ADC_CHAN(n), 0x00]
1300 * RX: [data_hi, data_lo] (storagebits=16, shift=0)
1301 * Transfer 0 RX is garbage; transfers 1..N carry real data.
1302 * scan_tx is reused for TX commands (mutually exclusive with the
1303 * non-offload triggered-buffer path).
1304 *
1305 * bits_per_word=bpw: the SPI controller reads tx_buf as a native
1306 * 16-bit word and shifts it out MSB-first. Store the exact 16-bit
1307 * value we want on the wire as a plain native u16 — no endianness
1308 * macro — so the wire bytes are correct on both LE and BE hosts.
1309 * The channel-select command is a single byte; shift it to the MSB
1310 * position so SPI sends it first, with a zero pad in the LSB.
1311 */
1312 k = 0;
1313 iio_for_each_active_channel(indio_dev, bit) {
1314 st->scan_tx[k] = AD4691_ADC_CHAN(bit) << 8;
1315 st->scan_xfers[k].tx_buf = &st->scan_tx[k];
1316 st->scan_xfers[k].len = sizeof(*st->scan_tx);
1317 st->scan_xfers[k].bits_per_word = bpw;
1318 st->scan_xfers[k].cs_change = 1;
1319 st->scan_xfers[k].cs_change_delay.value = AD4691_CNV_HIGH_TIME_NS;
1320 st->scan_xfers[k].cs_change_delay.unit = SPI_DELAY_UNIT_NSECS;
1321 /* First transfer RX is garbage — skip it. */
1322 if (k > 0)
1323 st->scan_xfers[k].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
1324 k++;
1325 }
1326
1327 /* Final NOOP transfer retrieves the last channel's result. */
1328 st->scan_xfers[k].tx_buf = &st->scan_tx[k]; /* scan_tx[k] == 0 == NOOP */
1329 st->scan_xfers[k].len = sizeof(*st->scan_tx);
1330 st->scan_xfers[k].bits_per_word = bpw;
1331 st->scan_xfers[k].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
1332 k++;
1333
1334 spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, k);
1335 st->scan_msg.offload = st->offload;
1336
1337 ret = spi_optimize_message(spi, &st->scan_msg);
1338 if (ret)
1339 goto err_exit_conversion;
1340
1341 config.periodic.frequency_hz = st->trigger_hz;
1342 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config);
1343 if (ret)
1344 goto err_unoptimize;
1345
1346 return 0;
1347
1348 err_unoptimize:
1349 spi_unoptimize_message(&st->scan_msg);
1350 err_exit_conversion:
1351 ad4691_exit_conversion_mode(st);
1352 return ret;
1353 }
1354
ad4691_manual_offload_buffer_predisable(struct iio_dev * indio_dev)1355 static int ad4691_manual_offload_buffer_predisable(struct iio_dev *indio_dev)
1356 {
1357 struct ad4691_state *st = iio_priv(indio_dev);
1358
1359 spi_offload_trigger_disable(st->offload, st->offload_trigger);
1360 spi_unoptimize_message(&st->scan_msg);
1361
1362 return ad4691_exit_conversion_mode(st);
1363 }
1364
1365 static const struct iio_buffer_setup_ops ad4691_manual_offload_buffer_setup_ops = {
1366 .postenable = ad4691_manual_offload_buffer_postenable,
1367 .predisable = ad4691_manual_offload_buffer_predisable,
1368 };
1369
ad4691_cnv_burst_offload_buffer_postenable(struct iio_dev * indio_dev)1370 static int ad4691_cnv_burst_offload_buffer_postenable(struct iio_dev *indio_dev)
1371 {
1372 struct ad4691_state *st = iio_priv(indio_dev);
1373 struct device *dev = regmap_get_device(st->regmap);
1374 struct spi_device *spi = to_spi_device(dev);
1375 struct spi_offload_trigger_config config = {
1376 .type = SPI_OFFLOAD_TRIGGER_DATA_READY,
1377 };
1378 unsigned int bpw = indio_dev->channels[0].scan_type.realbits;
1379 unsigned int acc_mask, std_seq_config;
1380 unsigned int bit, k;
1381 int ret;
1382
1383 std_seq_config = bitmap_read(indio_dev->active_scan_mask, 0,
1384 iio_get_masklength(indio_dev)) & GENMASK(15, 0);
1385 ret = regmap_write(st->regmap, AD4691_STD_SEQ_CONFIG, std_seq_config);
1386 if (ret)
1387 return ret;
1388
1389 acc_mask = ~std_seq_config & GENMASK(15, 0);
1390 ret = regmap_write(st->regmap, AD4691_ACC_MASK_REG, acc_mask);
1391 if (ret)
1392 return ret;
1393
1394 ret = regmap_write(st->regmap, AD4691_ACC_DEPTH_IN(0), st->osr);
1395 if (ret)
1396 return ret;
1397
1398 ret = ad4691_enter_conversion_mode(st);
1399 if (ret)
1400 return ret;
1401
1402 memset(st->scan_xfers, 0, sizeof(st->scan_xfers));
1403 memset(st->scan_tx, 0, sizeof(st->scan_tx));
1404
1405 /*
1406 * Each AVG_IN register read uses two transfers:
1407 * TX: [reg_hi | 0x80, reg_lo] (address phase, CS stays asserted)
1408 * RX: [data_hi, data_lo] (bpw-wide data phase, storagebits=16)
1409 * Both TX and RX use bits_per_word=bpw: the SPI controller reads tx_buf
1410 * as a native 16-bit word and shifts it out MSB-first. Store the exact
1411 * 16-bit wire value as a plain native u16 — no endianness macro — so the
1412 * wire bytes are correct on both LE and BE hosts. The read-address
1413 * (0x8000 | reg) is already the 16-bit value we want on the wire.
1414 * scan_tx is reused for TX addresses (mutually exclusive with the
1415 * non-offload triggered-buffer path).
1416 */
1417 k = 0;
1418 iio_for_each_active_channel(indio_dev, bit) {
1419 st->scan_tx[k] = 0x8000 | AD4691_AVG_IN(bit);
1420
1421 /* TX: address phase, CS stays asserted into data phase */
1422 st->scan_xfers[2 * k].tx_buf = &st->scan_tx[k];
1423 st->scan_xfers[2 * k].len = sizeof(*st->scan_tx);
1424 st->scan_xfers[2 * k].bits_per_word = bpw;
1425
1426 /* RX: data phase, CS toggles after to delimit the next register op */
1427 st->scan_xfers[2 * k + 1].len = sizeof(*st->scan_tx);
1428 st->scan_xfers[2 * k + 1].bits_per_word = bpw;
1429 st->scan_xfers[2 * k + 1].offload_flags = SPI_OFFLOAD_XFER_RX_STREAM;
1430 st->scan_xfers[2 * k + 1].cs_change = 1;
1431 k++;
1432 }
1433
1434 /*
1435 * State reset: single 4-byte write [addr_hi, addr_lo, STATE_RESET_ALL,
1436 * OSC_EN=1]. ADDR_DESCENDING writes byte[3]=1 to OSC_EN_REG (0x180) as
1437 * a deliberate side-write, keeping the oscillator enabled.
1438 * scan_tx_reset is shared with the non-offload path (len=4 here vs
1439 * len=3 there) since the two paths are mutually exclusive at probe.
1440 */
1441 put_unaligned_be16(AD4691_STATE_RESET_REG, st->scan_tx_reset);
1442 st->scan_tx_reset[2] = AD4691_STATE_RESET_ALL;
1443 st->scan_tx_reset[3] = 1;
1444 st->scan_xfers[2 * k].tx_buf = st->scan_tx_reset;
1445 st->scan_xfers[2 * k].len = sizeof(st->scan_tx_reset);
1446 /*
1447 * 4-byte u8 buffer assembled with put_unaligned_be16(); leave
1448 * bits_per_word at the default (8) so bytes go out in memory order.
1449 */
1450
1451 spi_message_init_with_transfers(&st->scan_msg, st->scan_xfers, 2 * k + 1);
1452 st->scan_msg.offload = st->offload;
1453
1454 ret = spi_optimize_message(spi, &st->scan_msg);
1455 if (ret)
1456 goto err_exit_conversion;
1457
1458 ret = spi_offload_trigger_enable(st->offload, st->offload_trigger, &config);
1459 if (ret)
1460 goto err_unoptimize;
1461
1462 ret = ad4691_sampling_enable(st, true);
1463 if (ret)
1464 goto err_disable_trigger;
1465
1466 return 0;
1467
1468 err_disable_trigger:
1469 spi_offload_trigger_disable(st->offload, st->offload_trigger);
1470 err_unoptimize:
1471 spi_unoptimize_message(&st->scan_msg);
1472 err_exit_conversion:
1473 ad4691_exit_conversion_mode(st);
1474 return ret;
1475 }
1476
ad4691_cnv_burst_offload_buffer_predisable(struct iio_dev * indio_dev)1477 static int ad4691_cnv_burst_offload_buffer_predisable(struct iio_dev *indio_dev)
1478 {
1479 struct ad4691_state *st = iio_priv(indio_dev);
1480
1481 ad4691_sampling_enable(st, false);
1482 spi_offload_trigger_disable(st->offload, st->offload_trigger);
1483 spi_unoptimize_message(&st->scan_msg);
1484
1485 return ad4691_exit_conversion_mode(st);
1486 }
1487
1488 static const struct iio_buffer_setup_ops ad4691_cnv_burst_offload_buffer_setup_ops = {
1489 .postenable = ad4691_cnv_burst_offload_buffer_postenable,
1490 .predisable = ad4691_cnv_burst_offload_buffer_predisable,
1491 };
1492
sampling_frequency_show(struct device * dev,struct device_attribute * attr,char * buf)1493 static ssize_t sampling_frequency_show(struct device *dev,
1494 struct device_attribute *attr,
1495 char *buf)
1496 {
1497 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1498 struct ad4691_state *st = iio_priv(indio_dev);
1499
1500 if (st->manual_mode && st->offload)
1501 return sysfs_emit(buf, "%llu\n", READ_ONCE(st->trigger_hz));
1502
1503 return sysfs_emit(buf, "%lu\n", NSEC_PER_SEC / st->cnv_period_ns);
1504 }
1505
sampling_frequency_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t len)1506 static ssize_t sampling_frequency_store(struct device *dev,
1507 struct device_attribute *attr,
1508 const char *buf, size_t len)
1509 {
1510 struct iio_dev *indio_dev = dev_to_iio_dev(dev);
1511 struct ad4691_state *st = iio_priv(indio_dev);
1512 unsigned int freq;
1513 int ret;
1514
1515 ret = kstrtouint(buf, 10, &freq);
1516 if (ret)
1517 return ret;
1518
1519 IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim);
1520 if (IIO_DEV_ACQUIRE_FAILED(claim))
1521 return -EBUSY;
1522
1523 if (st->manual_mode && st->offload) {
1524 struct spi_offload_trigger_config config = {
1525 .type = SPI_OFFLOAD_TRIGGER_PERIODIC,
1526 .periodic = { .frequency_hz = freq },
1527 };
1528
1529 ret = spi_offload_trigger_validate(st->offload_trigger, &config);
1530 if (ret)
1531 return ret;
1532
1533 WRITE_ONCE(st->trigger_hz, config.periodic.frequency_hz);
1534 return len;
1535 }
1536
1537 ret = ad4691_set_pwm_freq(st, freq);
1538 if (ret)
1539 return ret;
1540
1541 return len;
1542 }
1543
1544 static IIO_DEVICE_ATTR_RW(sampling_frequency, 0);
1545
1546 static const struct iio_dev_attr *ad4691_buffer_attrs[] = {
1547 &iio_dev_attr_sampling_frequency,
1548 NULL
1549 };
1550
ad4691_irq(int irq,void * private)1551 static irqreturn_t ad4691_irq(int irq, void *private)
1552 {
1553 struct iio_dev *indio_dev = private;
1554 struct ad4691_state *st = iio_priv(indio_dev);
1555
1556 /*
1557 * Disable the IRQ before calling iio_trigger_poll(). The IRQ is
1558 * re-enabled via the trigger .reenable callback, which the IIO core
1559 * calls inside iio_trigger_notify_done() once use_count reaches zero.
1560 * Re-enabling here (before notify_done) would race: a DATA_READY
1561 * between enable_irq() and notify_done() calls iio_trigger_poll()
1562 * while use_count > 0, dropping the event and permanently masking
1563 * the IRQ.
1564 */
1565 disable_irq_nosync(st->irq);
1566 iio_trigger_poll(indio_dev->trig);
1567
1568 return IRQ_HANDLED;
1569 }
1570
ad4691_trigger_reenable(struct iio_trigger * trig)1571 static void ad4691_trigger_reenable(struct iio_trigger *trig)
1572 {
1573 struct ad4691_state *st = iio_trigger_get_drvdata(trig);
1574
1575 enable_irq(st->irq);
1576 }
1577
1578 static const struct iio_trigger_ops ad4691_trigger_ops = {
1579 .reenable = ad4691_trigger_reenable,
1580 .validate_device = iio_trigger_validate_own_device,
1581 };
1582
ad4691_read_scan(struct iio_dev * indio_dev,s64 ts)1583 static void ad4691_read_scan(struct iio_dev *indio_dev, s64 ts)
1584 {
1585 struct ad4691_state *st = iio_priv(indio_dev);
1586 int ret;
1587
1588 guard(mutex)(&st->lock);
1589
1590 ret = spi_sync(st->spi, &st->scan_msg);
1591 if (ret) {
1592 dev_err_ratelimited(regmap_get_device(st->regmap),
1593 "SPI scan failed: %d\n", ret);
1594 return;
1595 }
1596
1597 /*
1598 * rx_buf pointers in scan_xfers point directly into scan.vals, so no
1599 * copy is needed. The scan_msg already includes a STATE_RESET at the
1600 * end (appended in preenable), so no explicit reset is needed here.
1601 */
1602 iio_push_to_buffers_with_ts(indio_dev, st->vals, sizeof(st->vals), ts);
1603 }
1604
ad4691_trigger_handler(int irq,void * p)1605 static irqreturn_t ad4691_trigger_handler(int irq, void *p)
1606 {
1607 struct iio_poll_func *pf = p;
1608 struct iio_dev *indio_dev = pf->indio_dev;
1609
1610 ad4691_read_scan(indio_dev, pf->timestamp);
1611 iio_trigger_notify_done(indio_dev->trig);
1612 return IRQ_HANDLED;
1613 }
1614
1615 /*
1616 * CNV burst mode: only allow our own trigger (driven by DATA_READY IRQ).
1617 * Manual mode: external triggers (e.g. iio-trig-hrtimer) must be allowed
1618 * because manual mode has no DATA_READY IRQ to fire the internal trigger.
1619 * iio_trigger_ops.validate_device = iio_trigger_validate_own_device is
1620 * correct in both modes — it prevents other devices from hijacking our
1621 * internal trigger; the distinction here is only for iio_info.validate_trigger.
1622 */
1623 static const struct iio_info ad4691_cnv_burst_info = {
1624 .read_raw = ad4691_read_raw,
1625 .write_raw = ad4691_write_raw,
1626 .read_avail = ad4691_read_avail,
1627 .debugfs_reg_access = ad4691_reg_access,
1628 .validate_trigger = iio_validate_own_trigger,
1629 };
1630
1631 static const struct iio_info ad4691_manual_info = {
1632 .read_raw = ad4691_read_raw,
1633 .write_raw = ad4691_write_raw,
1634 .read_avail = ad4691_read_avail,
1635 .debugfs_reg_access = ad4691_reg_access,
1636 };
1637
ad4691_pwm_setup(struct ad4691_state * st)1638 static int ad4691_pwm_setup(struct ad4691_state *st)
1639 {
1640 struct device *dev = regmap_get_device(st->regmap);
1641
1642 st->conv_trigger = devm_pwm_get(dev, "cnv");
1643 if (IS_ERR(st->conv_trigger))
1644 return dev_err_probe(dev, PTR_ERR(st->conv_trigger),
1645 "Failed to get CNV PWM\n");
1646
1647 return ad4691_set_pwm_freq(st, st->info->max_rate);
1648 }
1649
ad4691_regulator_setup(struct ad4691_state * st)1650 static int ad4691_regulator_setup(struct ad4691_state *st)
1651 {
1652 struct device *dev = regmap_get_device(st->regmap);
1653 int ret;
1654
1655 ret = devm_regulator_bulk_get_enable(dev, ARRAY_SIZE(ad4691_supplies),
1656 ad4691_supplies);
1657 if (ret)
1658 return dev_err_probe(dev, ret, "Failed to get and enable supplies\n");
1659
1660 /*
1661 * vdd-supply and ldo-in-supply are mutually exclusive:
1662 * vdd-supply present → external 1.8V VDD; disable internal LDO.
1663 * vdd-supply absent → enable internal LDO fed from ldo-in-supply.
1664 * Having both simultaneously is strongly inadvisable per the datasheet.
1665 */
1666 if (device_property_present(dev, "vdd-supply")) {
1667 ret = devm_regulator_get_enable(dev, "vdd");
1668 if (ret)
1669 return dev_err_probe(dev, ret,
1670 "Failed to get and enable VDD\n");
1671 } else if (device_property_present(dev, "ldo-in-supply")) {
1672 ret = devm_regulator_get_enable(dev, "ldo-in");
1673 if (ret)
1674 return dev_err_probe(dev, ret,
1675 "Failed to get and enable LDO-IN\n");
1676 st->ldo_en = true;
1677 } else {
1678 return dev_err_probe(dev, -EINVAL,
1679 "missing one of vdd-supply, ldo-in-supply\n");
1680 }
1681
1682 if (device_property_present(dev, "ref-supply")) {
1683 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "ref");
1684 if (st->vref_uV < 0)
1685 return dev_err_probe(dev, st->vref_uV,
1686 "Failed to get REF supply voltage\n");
1687 } else if (device_property_present(dev, "refin-supply")) {
1688 st->vref_uV = devm_regulator_get_enable_read_voltage(dev, "refin");
1689 if (st->vref_uV < 0)
1690 return dev_err_probe(dev, st->vref_uV,
1691 "Failed to get REFIN supply voltage\n");
1692 st->refbuf_en = true;
1693 } else {
1694 return dev_err_probe(dev, -EINVAL,
1695 "missing one of ref-supply, refin-supply\n");
1696 }
1697
1698 if (st->vref_uV < AD4691_VREF_uV_MIN || st->vref_uV > AD4691_VREF_uV_MAX)
1699 return dev_err_probe(dev, -EINVAL,
1700 "vref(%d) must be in the range [%u...%u]\n",
1701 st->vref_uV, AD4691_VREF_uV_MIN,
1702 AD4691_VREF_uV_MAX);
1703
1704 return 0;
1705 }
1706
ad4691_reset(struct ad4691_state * st)1707 static int ad4691_reset(struct ad4691_state *st)
1708 {
1709 struct device *dev = regmap_get_device(st->regmap);
1710 struct reset_control *rst;
1711 int ret;
1712
1713 rst = devm_reset_control_get_optional_exclusive(dev, NULL);
1714 if (IS_ERR(rst))
1715 return dev_err_probe(dev, PTR_ERR(rst), "Failed to get reset\n");
1716
1717 if (rst) {
1718 /*
1719 * Assert the reset line to guarantee a clean reset pulse on
1720 * every probe, including driver reloads where the line may
1721 * already be deasserted (reset_control_put() does not
1722 * re-assert on release). tRESETL (minimum pulse width) = 10 ns
1723 * (Table 5); kernel function-call overhead alone exceeds this,
1724 * so no explicit delay is needed between assert and deassert.
1725 */
1726 reset_control_assert(rst);
1727 ret = reset_control_deassert(rst);
1728 if (ret)
1729 return ret;
1730 } else {
1731 /* No hardware reset available, fall back to software reset. */
1732 ret = regmap_write(st->regmap, AD4691_SPI_CONFIG_A_REG,
1733 AD4691_SW_RESET);
1734 if (ret)
1735 return ret;
1736 }
1737
1738 /*
1739 * Wait 300 µs (Table 5) for the device to complete its internal reset
1740 * sequence before accepting SPI commands.
1741 */
1742 fsleep(300);
1743 return 0;
1744 }
1745
ad4691_config(struct ad4691_state * st)1746 static int ad4691_config(struct ad4691_state *st)
1747 {
1748 struct device *dev = regmap_get_device(st->regmap);
1749 enum ad4691_ref_ctrl ref_val;
1750 unsigned int val;
1751 int ret;
1752
1753 /*
1754 * Determine buffer conversion mode from DT: if a PWM is provided it
1755 * drives the CNV pin (CNV_BURST_MODE); otherwise CNV is tied to CS
1756 * and each SPI transfer triggers a conversion (MANUAL_MODE).
1757 * Both modes idle in AUTONOMOUS mode so that read_raw can use the
1758 * internal oscillator without disturbing the hardware configuration.
1759 */
1760 if (device_property_present(dev, "pwms")) {
1761 st->manual_mode = false;
1762 ret = ad4691_pwm_setup(st);
1763 if (ret)
1764 return ret;
1765 } else {
1766 st->manual_mode = true;
1767 }
1768
1769 switch (st->vref_uV) {
1770 case AD4691_VREF_uV_MIN ... AD4691_VREF_2P5_uV_MAX:
1771 ref_val = AD4691_VREF_2P5;
1772 break;
1773 case AD4691_VREF_2P5_uV_MAX + 1 ... AD4691_VREF_3P0_uV_MAX:
1774 ref_val = AD4691_VREF_3P0;
1775 break;
1776 case AD4691_VREF_3P0_uV_MAX + 1 ... AD4691_VREF_3P3_uV_MAX:
1777 ref_val = AD4691_VREF_3P3;
1778 break;
1779 case AD4691_VREF_3P3_uV_MAX + 1 ... AD4691_VREF_4P096_uV_MAX:
1780 ref_val = AD4691_VREF_4P096;
1781 break;
1782 case AD4691_VREF_4P096_uV_MAX + 1 ... AD4691_VREF_uV_MAX:
1783 ref_val = AD4691_VREF_5P0;
1784 break;
1785 default:
1786 return dev_err_probe(dev, -EINVAL,
1787 "Unsupported vref voltage: %d uV\n",
1788 st->vref_uV);
1789 }
1790
1791 val = FIELD_PREP(AD4691_REF_CTRL_MASK, ref_val);
1792 if (st->refbuf_en)
1793 val |= AD4691_REFBUF_EN;
1794
1795 ret = regmap_write(st->regmap, AD4691_REF_CTRL, val);
1796 if (ret)
1797 return dev_err_probe(dev, ret, "Failed to write REF_CTRL\n");
1798
1799 ret = regmap_assign_bits(st->regmap, AD4691_DEVICE_SETUP,
1800 AD4691_LDO_EN, st->ldo_en);
1801 if (ret)
1802 return dev_err_probe(dev, ret, "Failed to write DEVICE_SETUP\n");
1803
1804 /*
1805 * Set the internal oscillator to the highest rate this chip supports.
1806 * Index 0 (1 MHz) exceeds the 500 kHz max of AD4691/AD4693, so those
1807 * chips start at index 1 (500 kHz).
1808 */
1809 ret = regmap_write(st->regmap, AD4691_OSC_FREQ_REG,
1810 ad4691_samp_freq_start(st->info));
1811 if (ret)
1812 return dev_err_probe(dev, ret, "Failed to write OSC_FREQ\n");
1813
1814 st->target_osc_freq_Hz = ad4691_osc_freqs_Hz[ad4691_samp_freq_start(st->info)];
1815
1816 ret = regmap_update_bits(st->regmap, AD4691_ADC_SETUP,
1817 AD4691_ADC_MODE_MASK, AD4691_AUTONOMOUS_MODE);
1818 if (ret)
1819 return dev_err_probe(dev, ret, "Failed to write ADC_SETUP\n");
1820
1821 ad4691_precompute_samp_freq_avail(st);
1822
1823 return 0;
1824 }
1825
ad4691_setup_triggered_buffer(struct iio_dev * indio_dev,struct ad4691_state * st)1826 static int ad4691_setup_triggered_buffer(struct iio_dev *indio_dev,
1827 struct ad4691_state *st)
1828 {
1829 struct device *dev = regmap_get_device(st->regmap);
1830 struct iio_trigger *trig;
1831 unsigned int i;
1832 int irq, ret;
1833
1834 /*
1835 * Manual mode exposes channels without the oversampling_ratio attribute
1836 * because ACC_DEPTH_IN is not configured in manual mode.
1837 */
1838 if (st->manual_mode)
1839 indio_dev->channels = st->info->sw_info->manual_channels;
1840 else
1841 indio_dev->channels = st->info->sw_info->channels;
1842 indio_dev->num_channels = st->info->sw_info->num_channels;
1843 indio_dev->info = st->manual_mode ? &ad4691_manual_info : &ad4691_cnv_burst_info;
1844
1845 /*
1846 * Manual mode relies on an external trigger (e.g. iio-trig-hrtimer);
1847 * no internal trigger is needed or registered.
1848 */
1849 if (st->manual_mode)
1850 return devm_iio_triggered_buffer_setup(dev, indio_dev,
1851 iio_pollfunc_store_time,
1852 ad4691_trigger_handler,
1853 &ad4691_manual_buffer_setup_ops);
1854
1855 /*
1856 * CNV burst mode: allocate an internal trigger driven by the
1857 * DATA_READY IRQ on the GP pin.
1858 */
1859 trig = devm_iio_trigger_alloc(dev, "%s-dev%d", indio_dev->name,
1860 iio_device_id(indio_dev));
1861 if (!trig)
1862 return -ENOMEM;
1863
1864 trig->ops = &ad4691_trigger_ops;
1865 iio_trigger_set_drvdata(trig, st);
1866
1867 ret = devm_iio_trigger_register(dev, trig);
1868 if (ret)
1869 return dev_err_probe(dev, ret, "IIO trigger register failed\n");
1870
1871 indio_dev->trig = iio_trigger_get(trig);
1872
1873 /*
1874 * The GP pin named in interrupt-names asserts at end-of-conversion.
1875 * The IRQ handler fires the IIO trigger so the trigger handler can
1876 * read and push the sample to the buffer. The IRQ is kept disabled
1877 * until the buffer is enabled.
1878 */
1879 irq = -ENXIO;
1880 for (i = 0; i < ARRAY_SIZE(ad4691_gp_names); i++) {
1881 irq = fwnode_irq_get_byname(dev_fwnode(dev),
1882 ad4691_gp_names[i]);
1883 if (irq > 0 || irq == -EPROBE_DEFER)
1884 break;
1885 }
1886 if (irq < 0)
1887 return dev_err_probe(dev, irq, "failed to get GP interrupt\n");
1888
1889 st->irq = irq;
1890
1891 ret = ad4691_gpio_setup(st, i);
1892 if (ret)
1893 return ret;
1894
1895 /*
1896 * The handler only calls disable_irq_nosync() and iio_trigger_poll(),
1897 * both safe in hardirq context, so register as a hard IRQ handler.
1898 * IRQF_NO_AUTOEN keeps it disabled until the buffer is enabled.
1899 */
1900 ret = devm_request_irq(dev, irq, ad4691_irq, IRQF_NO_AUTOEN,
1901 indio_dev->name, indio_dev);
1902 if (ret)
1903 return ret;
1904
1905 return devm_iio_triggered_buffer_setup_ext(dev, indio_dev,
1906 iio_pollfunc_store_time,
1907 ad4691_trigger_handler,
1908 IIO_BUFFER_DIRECTION_IN,
1909 &ad4691_cnv_burst_buffer_setup_ops,
1910 ad4691_buffer_attrs);
1911 }
1912
ad4691_setup_offload(struct iio_dev * indio_dev,struct ad4691_state * st,struct spi_offload * spi_offload)1913 static int ad4691_setup_offload(struct iio_dev *indio_dev,
1914 struct ad4691_state *st,
1915 struct spi_offload *spi_offload)
1916 {
1917 struct device *dev = regmap_get_device(st->regmap);
1918 struct dma_chan *rx_dma;
1919 int ret;
1920
1921 st->offload = spi_offload;
1922
1923 /*
1924 * CNV burst offload exposes oversampling_ratio (ACC_DEPTH_IN is
1925 * configured per channel at buffer enable). Manual offload does not
1926 * configure ACC_DEPTH_IN, so it uses a separate channel array
1927 * without the oversampling_ratio attribute. Both paths use IIO_CPU
1928 * (no .endianness annotation) because bits_per_word=16 causes the
1929 * SPI Engine to produce native 16-bit DMA words.
1930 */
1931 if (st->manual_mode)
1932 indio_dev->channels = st->info->offload_info->manual_channels;
1933 else
1934 indio_dev->channels = st->info->offload_info->channels;
1935 indio_dev->num_channels = st->info->offload_info->num_channels;
1936 /*
1937 * Offload path uses DMA directly; no IIO trigger is involved, so
1938 * external triggers are not restricted (no validate_trigger).
1939 */
1940 indio_dev->info = &ad4691_manual_info;
1941
1942 if (st->manual_mode) {
1943 st->offload_trigger =
1944 devm_spi_offload_trigger_get(dev, st->offload,
1945 SPI_OFFLOAD_TRIGGER_PERIODIC);
1946 if (IS_ERR(st->offload_trigger))
1947 return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
1948 "Failed to get periodic offload trigger\n");
1949
1950 st->trigger_hz = AD4691_OFFLOAD_INITIAL_TRIGGER_HZ;
1951 } else {
1952 struct spi_offload_trigger_info trigger_info = {
1953 .fwnode = dev_fwnode(dev),
1954 .ops = &ad4691_offload_trigger_ops,
1955 .priv = st,
1956 };
1957
1958 ret = devm_spi_offload_trigger_register(dev, &trigger_info);
1959 if (ret)
1960 return dev_err_probe(dev, ret,
1961 "Failed to register offload trigger\n");
1962
1963 st->offload_trigger =
1964 devm_spi_offload_trigger_get(dev, st->offload,
1965 SPI_OFFLOAD_TRIGGER_DATA_READY);
1966 if (IS_ERR(st->offload_trigger))
1967 return dev_err_probe(dev, PTR_ERR(st->offload_trigger),
1968 "Failed to get DATA_READY offload trigger\n");
1969 }
1970
1971 rx_dma = devm_spi_offload_rx_stream_request_dma_chan(dev, st->offload);
1972 if (IS_ERR(rx_dma))
1973 return dev_err_probe(dev, PTR_ERR(rx_dma),
1974 "Failed to get offload RX DMA channel\n");
1975
1976 if (st->manual_mode)
1977 indio_dev->setup_ops = &ad4691_manual_offload_buffer_setup_ops;
1978 else
1979 indio_dev->setup_ops = &ad4691_cnv_burst_offload_buffer_setup_ops;
1980
1981 ret = devm_iio_dmaengine_buffer_setup_with_handle(dev, indio_dev, rx_dma,
1982 IIO_BUFFER_DIRECTION_IN);
1983 if (ret)
1984 return ret;
1985
1986 indio_dev->buffer->attrs = ad4691_buffer_attrs;
1987
1988 return 0;
1989 }
1990
ad4691_probe(struct spi_device * spi)1991 static int ad4691_probe(struct spi_device *spi)
1992 {
1993 struct device *dev = &spi->dev;
1994 struct spi_offload *spi_offload;
1995 struct iio_dev *indio_dev;
1996 struct ad4691_state *st;
1997 int ret;
1998
1999 indio_dev = devm_iio_device_alloc(dev, sizeof(*st));
2000 if (!indio_dev)
2001 return -ENOMEM;
2002
2003 st = iio_priv(indio_dev);
2004 st->spi = spi;
2005 st->info = spi_get_device_match_data(spi);
2006 if (!st->info)
2007 return -ENODEV;
2008 st->osr = 1;
2009
2010 ret = devm_mutex_init(dev, &st->lock);
2011 if (ret)
2012 return ret;
2013
2014 st->regmap = devm_regmap_init(dev, NULL, spi, &ad4691_regmap_config);
2015 if (IS_ERR(st->regmap))
2016 return dev_err_probe(dev, PTR_ERR(st->regmap),
2017 "Failed to initialize regmap\n");
2018
2019 ret = ad4691_regulator_setup(st);
2020 if (ret)
2021 return ret;
2022
2023 ret = ad4691_reset(st);
2024 if (ret)
2025 return ret;
2026
2027 ret = ad4691_config(st);
2028 if (ret)
2029 return ret;
2030
2031 spi_offload = devm_spi_offload_get(dev, spi, &ad4691_offload_config);
2032 ret = PTR_ERR_OR_ZERO(spi_offload);
2033 if (ret == -ENODEV)
2034 spi_offload = NULL;
2035 else if (ret)
2036 return dev_err_probe(dev, ret, "Failed to get SPI offload\n");
2037
2038 indio_dev->name = st->info->name;
2039 indio_dev->modes = INDIO_DIRECT_MODE;
2040
2041 if (spi_offload)
2042 ret = ad4691_setup_offload(indio_dev, st, spi_offload);
2043 else
2044 ret = ad4691_setup_triggered_buffer(indio_dev, st);
2045 if (ret)
2046 return ret;
2047
2048 return devm_iio_device_register(dev, indio_dev);
2049 }
2050
2051 static const struct of_device_id ad4691_of_match[] = {
2052 { .compatible = "adi,ad4691", .data = &ad4691_chip_info },
2053 { .compatible = "adi,ad4692", .data = &ad4692_chip_info },
2054 { .compatible = "adi,ad4693", .data = &ad4693_chip_info },
2055 { .compatible = "adi,ad4694", .data = &ad4694_chip_info },
2056 { }
2057 };
2058 MODULE_DEVICE_TABLE(of, ad4691_of_match);
2059
2060 static const struct spi_device_id ad4691_id[] = {
2061 { .name = "ad4691", .driver_data = (kernel_ulong_t)&ad4691_chip_info },
2062 { .name = "ad4692", .driver_data = (kernel_ulong_t)&ad4692_chip_info },
2063 { .name = "ad4693", .driver_data = (kernel_ulong_t)&ad4693_chip_info },
2064 { .name = "ad4694", .driver_data = (kernel_ulong_t)&ad4694_chip_info },
2065 { }
2066 };
2067 MODULE_DEVICE_TABLE(spi, ad4691_id);
2068
2069 static struct spi_driver ad4691_driver = {
2070 .driver = {
2071 .name = "ad4691",
2072 .of_match_table = ad4691_of_match,
2073 },
2074 .probe = ad4691_probe,
2075 .id_table = ad4691_id,
2076 };
2077 module_spi_driver(ad4691_driver);
2078
2079 MODULE_AUTHOR("Radu Sabau <radu.sabau@analog.com>");
2080 MODULE_DESCRIPTION("Analog Devices AD4691 Family ADC Driver");
2081 MODULE_LICENSE("GPL");
2082 MODULE_IMPORT_NS("IIO_DMA_BUFFER");
2083 MODULE_IMPORT_NS("IIO_DMAENGINE_BUFFER");
2084