1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * i2c-xiic.c 4 * Copyright (c) 2002-2007 Xilinx Inc. 5 * Copyright (c) 2009-2010 Intel Corporation 6 * 7 * This code was implemented by Mocean Laboratories AB when porting linux 8 * to the automotive development board Russellville. The copyright holder 9 * as seen in the header is Intel corporation. 10 * Mocean Laboratories forked off the GNU/Linux platform work into a 11 * separate company called Pelagicore AB, which committed the code to the 12 * kernel. 13 */ 14 15 /* Supports: 16 * Xilinx IIC 17 */ 18 #include <linux/kernel.h> 19 #include <linux/module.h> 20 #include <linux/errno.h> 21 #include <linux/err.h> 22 #include <linux/delay.h> 23 #include <linux/platform_device.h> 24 #include <linux/i2c.h> 25 #include <linux/interrupt.h> 26 #include <linux/completion.h> 27 #include <linux/platform_data/i2c-xiic.h> 28 #include <linux/io.h> 29 #include <linux/slab.h> 30 #include <linux/of.h> 31 #include <linux/clk.h> 32 #include <linux/pm_runtime.h> 33 34 #define DRIVER_NAME "xiic-i2c" 35 36 enum xilinx_i2c_state { 37 STATE_DONE, 38 STATE_ERROR, 39 STATE_START 40 }; 41 42 enum xiic_endian { 43 LITTLE, 44 BIG 45 }; 46 47 /** 48 * struct xiic_i2c - Internal representation of the XIIC I2C bus 49 * @dev: Pointer to device structure 50 * @base: Memory base of the HW registers 51 * @completion: Completion for callers 52 * @adap: Kernel adapter representation 53 * @tx_msg: Messages from above to be sent 54 * @lock: Mutual exclusion 55 * @tx_pos: Current pos in TX message 56 * @nmsgs: Number of messages in tx_msg 57 * @rx_msg: Current RX message 58 * @rx_pos: Position within current RX message 59 * @endianness: big/little-endian byte order 60 * @clk: Pointer to AXI4-lite input clock 61 * @state: See STATE_ 62 * @singlemaster: Indicates bus is single master 63 */ 64 struct xiic_i2c { 65 struct device *dev; 66 void __iomem *base; 67 struct completion completion; 68 struct i2c_adapter adap; 69 struct i2c_msg *tx_msg; 70 struct mutex lock; 71 unsigned int tx_pos; 72 unsigned int nmsgs; 73 struct i2c_msg *rx_msg; 74 int rx_pos; 75 enum xiic_endian endianness; 76 struct clk *clk; 77 enum xilinx_i2c_state state; 78 bool singlemaster; 79 }; 80 81 #define XIIC_MSB_OFFSET 0 82 #define XIIC_REG_OFFSET (0x100 + XIIC_MSB_OFFSET) 83 84 /* 85 * Register offsets in bytes from RegisterBase. Three is added to the 86 * base offset to access LSB (IBM style) of the word 87 */ 88 #define XIIC_CR_REG_OFFSET (0x00 + XIIC_REG_OFFSET) /* Control Register */ 89 #define XIIC_SR_REG_OFFSET (0x04 + XIIC_REG_OFFSET) /* Status Register */ 90 #define XIIC_DTR_REG_OFFSET (0x08 + XIIC_REG_OFFSET) /* Data Tx Register */ 91 #define XIIC_DRR_REG_OFFSET (0x0C + XIIC_REG_OFFSET) /* Data Rx Register */ 92 #define XIIC_ADR_REG_OFFSET (0x10 + XIIC_REG_OFFSET) /* Address Register */ 93 #define XIIC_TFO_REG_OFFSET (0x14 + XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 94 #define XIIC_RFO_REG_OFFSET (0x18 + XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 95 #define XIIC_TBA_REG_OFFSET (0x1C + XIIC_REG_OFFSET) /* 10 Bit Address reg */ 96 #define XIIC_RFD_REG_OFFSET (0x20 + XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 97 #define XIIC_GPO_REG_OFFSET (0x24 + XIIC_REG_OFFSET) /* Output Register */ 98 99 /* Control Register masks */ 100 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 101 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 102 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 103 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 104 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 105 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 106 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 107 108 /* Status Register masks */ 109 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 110 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 111 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 112 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 113 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 114 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 115 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 116 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 117 118 /* Interrupt Status Register masks Interrupt occurs when... */ 119 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 120 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 121 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 122 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 123 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 124 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 125 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 126 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 127 128 /* The following constants specify the depth of the FIFOs */ 129 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 130 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 131 132 /* The following constants specify groups of interrupts that are typically 133 * enabled or disables at the same time 134 */ 135 #define XIIC_TX_INTERRUPTS \ 136 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 137 138 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 139 140 /* 141 * Tx Fifo upper bit masks. 142 */ 143 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 144 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 145 146 /* 147 * The following constants define the register offsets for the Interrupt 148 * registers. There are some holes in the memory map for reserved addresses 149 * to allow other registers to be added and still match the memory map of the 150 * interrupt controller registers 151 */ 152 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 153 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 154 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 155 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 156 157 #define XIIC_RESET_MASK 0xAUL 158 159 #define XIIC_PM_TIMEOUT 1000 /* ms */ 160 /* timeout waiting for the controller to respond */ 161 #define XIIC_I2C_TIMEOUT (msecs_to_jiffies(1000)) 162 /* timeout waiting for the controller finish transfers */ 163 #define XIIC_XFER_TIMEOUT (msecs_to_jiffies(10000)) 164 165 /* 166 * The following constant is used for the device global interrupt enable 167 * register, to enable all interrupts for the device, this is the only bit 168 * in the register 169 */ 170 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 171 172 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 173 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 174 175 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num); 176 static void __xiic_start_xfer(struct xiic_i2c *i2c); 177 178 /* 179 * For the register read and write functions, a little-endian and big-endian 180 * version are necessary. Endianness is detected during the probe function. 181 * Only the least significant byte [doublet] of the register are ever 182 * accessed. This requires an offset of 3 [2] from the base address for 183 * big-endian systems. 184 */ 185 186 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 187 { 188 if (i2c->endianness == LITTLE) 189 iowrite8(value, i2c->base + reg); 190 else 191 iowrite8(value, i2c->base + reg + 3); 192 } 193 194 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 195 { 196 u8 ret; 197 198 if (i2c->endianness == LITTLE) 199 ret = ioread8(i2c->base + reg); 200 else 201 ret = ioread8(i2c->base + reg + 3); 202 return ret; 203 } 204 205 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 206 { 207 if (i2c->endianness == LITTLE) 208 iowrite16(value, i2c->base + reg); 209 else 210 iowrite16be(value, i2c->base + reg + 2); 211 } 212 213 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 214 { 215 if (i2c->endianness == LITTLE) 216 iowrite32(value, i2c->base + reg); 217 else 218 iowrite32be(value, i2c->base + reg); 219 } 220 221 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 222 { 223 u32 ret; 224 225 if (i2c->endianness == LITTLE) 226 ret = ioread32(i2c->base + reg); 227 else 228 ret = ioread32be(i2c->base + reg); 229 return ret; 230 } 231 232 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 233 { 234 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 235 236 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 237 } 238 239 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 240 { 241 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 242 243 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 244 } 245 246 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 247 { 248 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 249 250 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 251 } 252 253 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 254 { 255 xiic_irq_clr(i2c, mask); 256 xiic_irq_en(i2c, mask); 257 } 258 259 static int xiic_clear_rx_fifo(struct xiic_i2c *i2c) 260 { 261 u8 sr; 262 unsigned long timeout; 263 264 timeout = jiffies + XIIC_I2C_TIMEOUT; 265 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 266 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 267 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) { 268 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 269 if (time_after(jiffies, timeout)) { 270 dev_err(i2c->dev, "Failed to clear rx fifo\n"); 271 return -ETIMEDOUT; 272 } 273 } 274 275 return 0; 276 } 277 278 static int xiic_reinit(struct xiic_i2c *i2c) 279 { 280 int ret; 281 282 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 283 284 /* Set receive Fifo depth to maximum (zero based). */ 285 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 286 287 /* Reset Tx Fifo. */ 288 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 289 290 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 291 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 292 293 /* make sure RX fifo is empty */ 294 ret = xiic_clear_rx_fifo(i2c); 295 if (ret) 296 return ret; 297 298 /* Enable interrupts */ 299 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 300 301 xiic_irq_clr_en(i2c, XIIC_INTR_ARB_LOST_MASK); 302 303 return 0; 304 } 305 306 static void xiic_deinit(struct xiic_i2c *i2c) 307 { 308 u8 cr; 309 310 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 311 312 /* Disable IIC Device. */ 313 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 314 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 315 } 316 317 static void xiic_read_rx(struct xiic_i2c *i2c) 318 { 319 u8 bytes_in_fifo; 320 int i; 321 322 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 323 324 dev_dbg(i2c->adap.dev.parent, 325 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 326 __func__, bytes_in_fifo, xiic_rx_space(i2c), 327 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 328 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 329 330 if (bytes_in_fifo > xiic_rx_space(i2c)) 331 bytes_in_fifo = xiic_rx_space(i2c); 332 333 for (i = 0; i < bytes_in_fifo; i++) 334 i2c->rx_msg->buf[i2c->rx_pos++] = 335 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 336 337 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 338 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 339 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 340 } 341 342 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 343 { 344 /* return the actual space left in the FIFO */ 345 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 346 } 347 348 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 349 { 350 u8 fifo_space = xiic_tx_fifo_space(i2c); 351 int len = xiic_tx_space(i2c); 352 353 len = (len > fifo_space) ? fifo_space : len; 354 355 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 356 __func__, len, fifo_space); 357 358 while (len--) { 359 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 360 361 if (!xiic_tx_space(i2c) && i2c->nmsgs == 1) { 362 /* last message in transfer -> STOP */ 363 data |= XIIC_TX_DYN_STOP_MASK; 364 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 365 } 366 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 367 } 368 } 369 370 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 371 { 372 i2c->tx_msg = NULL; 373 i2c->rx_msg = NULL; 374 i2c->nmsgs = 0; 375 i2c->state = code; 376 complete(&i2c->completion); 377 } 378 379 static irqreturn_t xiic_process(int irq, void *dev_id) 380 { 381 struct xiic_i2c *i2c = dev_id; 382 u32 pend, isr, ier; 383 u32 clr = 0; 384 int xfer_more = 0; 385 int wakeup_req = 0; 386 int wakeup_code = 0; 387 int ret; 388 389 /* Get the interrupt Status from the IPIF. There is no clearing of 390 * interrupts in the IPIF. Interrupts must be cleared at the source. 391 * To find which interrupts are pending; AND interrupts pending with 392 * interrupts masked. 393 */ 394 mutex_lock(&i2c->lock); 395 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 396 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 397 pend = isr & ier; 398 399 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 400 __func__, ier, isr, pend); 401 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 402 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 403 i2c->tx_msg, i2c->nmsgs); 404 405 406 /* Service requesting interrupt */ 407 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 408 ((pend & XIIC_INTR_TX_ERROR_MASK) && 409 !(pend & XIIC_INTR_RX_FULL_MASK))) { 410 /* bus arbritration lost, or... 411 * Transmit error _OR_ RX completed 412 * if this happens when RX_FULL is not set 413 * this is probably a TX error 414 */ 415 416 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 417 418 /* dynamic mode seem to suffer from problems if we just flushes 419 * fifos and the next message is a TX with len 0 (only addr) 420 * reset the IP instead of just flush fifos 421 */ 422 ret = xiic_reinit(i2c); 423 if (!ret) 424 dev_dbg(i2c->adap.dev.parent, "reinit failed\n"); 425 426 if (i2c->rx_msg) { 427 wakeup_req = 1; 428 wakeup_code = STATE_ERROR; 429 } 430 if (i2c->tx_msg) { 431 wakeup_req = 1; 432 wakeup_code = STATE_ERROR; 433 } 434 } 435 if (pend & XIIC_INTR_RX_FULL_MASK) { 436 /* Receive register/FIFO is full */ 437 438 clr |= XIIC_INTR_RX_FULL_MASK; 439 if (!i2c->rx_msg) { 440 dev_dbg(i2c->adap.dev.parent, 441 "%s unexpected RX IRQ\n", __func__); 442 xiic_clear_rx_fifo(i2c); 443 goto out; 444 } 445 446 xiic_read_rx(i2c); 447 if (xiic_rx_space(i2c) == 0) { 448 /* this is the last part of the message */ 449 i2c->rx_msg = NULL; 450 451 /* also clear TX error if there (RX complete) */ 452 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 453 454 dev_dbg(i2c->adap.dev.parent, 455 "%s end of message, nmsgs: %d\n", 456 __func__, i2c->nmsgs); 457 458 /* send next message if this wasn't the last, 459 * otherwise the transfer will be finialise when 460 * receiving the bus not busy interrupt 461 */ 462 if (i2c->nmsgs > 1) { 463 i2c->nmsgs--; 464 i2c->tx_msg++; 465 dev_dbg(i2c->adap.dev.parent, 466 "%s will start next...\n", __func__); 467 xfer_more = 1; 468 } 469 } 470 } 471 if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 472 /* Transmit register/FIFO is empty or ½ empty */ 473 474 clr |= (pend & 475 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)); 476 477 if (!i2c->tx_msg) { 478 dev_dbg(i2c->adap.dev.parent, 479 "%s unexpected TX IRQ\n", __func__); 480 goto out; 481 } 482 483 xiic_fill_tx_fifo(i2c); 484 485 /* current message sent and there is space in the fifo */ 486 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 487 dev_dbg(i2c->adap.dev.parent, 488 "%s end of message sent, nmsgs: %d\n", 489 __func__, i2c->nmsgs); 490 if (i2c->nmsgs > 1) { 491 i2c->nmsgs--; 492 i2c->tx_msg++; 493 xfer_more = 1; 494 } else { 495 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 496 497 dev_dbg(i2c->adap.dev.parent, 498 "%s Got TX IRQ but no more to do...\n", 499 __func__); 500 } 501 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 502 /* current frame is sent and is last, 503 * make sure to disable tx half 504 */ 505 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 506 } 507 508 if (pend & XIIC_INTR_BNB_MASK) { 509 /* IIC bus has transitioned to not busy */ 510 clr |= XIIC_INTR_BNB_MASK; 511 512 /* The bus is not busy, disable BusNotBusy interrupt */ 513 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 514 515 if (!i2c->tx_msg) 516 goto out; 517 518 wakeup_req = 1; 519 520 if (i2c->nmsgs == 1 && !i2c->rx_msg && 521 xiic_tx_space(i2c) == 0) 522 wakeup_code = STATE_DONE; 523 else 524 wakeup_code = STATE_ERROR; 525 } 526 527 out: 528 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 529 530 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 531 if (xfer_more) 532 __xiic_start_xfer(i2c); 533 if (wakeup_req) 534 xiic_wakeup(i2c, wakeup_code); 535 536 WARN_ON(xfer_more && wakeup_req); 537 538 mutex_unlock(&i2c->lock); 539 return IRQ_HANDLED; 540 } 541 542 static int xiic_bus_busy(struct xiic_i2c *i2c) 543 { 544 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 545 546 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 547 } 548 549 static int xiic_busy(struct xiic_i2c *i2c) 550 { 551 int tries = 3; 552 int err; 553 554 if (i2c->tx_msg || i2c->rx_msg) 555 return -EBUSY; 556 557 /* In single master mode bus can only be busy, when in use by this 558 * driver. If the register indicates bus being busy for some reason we 559 * should ignore it, since bus will never be released and i2c will be 560 * stuck forever. 561 */ 562 if (i2c->singlemaster) { 563 return 0; 564 } 565 566 /* for instance if previous transfer was terminated due to TX error 567 * it might be that the bus is on it's way to become available 568 * give it at most 3 ms to wake 569 */ 570 err = xiic_bus_busy(i2c); 571 while (err && tries--) { 572 msleep(1); 573 err = xiic_bus_busy(i2c); 574 } 575 576 return err; 577 } 578 579 static void xiic_start_recv(struct xiic_i2c *i2c) 580 { 581 u16 rx_watermark; 582 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 583 584 /* Clear and enable Rx full interrupt. */ 585 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 586 587 /* we want to get all but last byte, because the TX_ERROR IRQ is used 588 * to inidicate error ACK on the address, and negative ack on the last 589 * received byte, so to not mix them receive all but last. 590 * In the case where there is only one byte to receive 591 * we can check if ERROR and RX full is set at the same time 592 */ 593 rx_watermark = msg->len; 594 if (rx_watermark > IIC_RX_FIFO_DEPTH) 595 rx_watermark = IIC_RX_FIFO_DEPTH; 596 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, (u8)(rx_watermark - 1)); 597 598 if (!(msg->flags & I2C_M_NOSTART)) 599 /* write the address */ 600 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 601 i2c_8bit_addr_from_msg(msg) | XIIC_TX_DYN_START_MASK); 602 603 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 604 605 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 606 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 607 608 if (i2c->nmsgs == 1) 609 /* very last, enable bus not busy as well */ 610 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 611 612 /* the message is tx:ed */ 613 i2c->tx_pos = msg->len; 614 } 615 616 static void xiic_start_send(struct xiic_i2c *i2c) 617 { 618 struct i2c_msg *msg = i2c->tx_msg; 619 620 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 621 __func__, msg, msg->len); 622 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 623 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 624 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 625 626 if (!(msg->flags & I2C_M_NOSTART)) { 627 /* write the address */ 628 u16 data = i2c_8bit_addr_from_msg(msg) | 629 XIIC_TX_DYN_START_MASK; 630 if ((i2c->nmsgs == 1) && msg->len == 0) 631 /* no data and last message -> add STOP */ 632 data |= XIIC_TX_DYN_STOP_MASK; 633 634 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 635 } 636 637 /* Clear any pending Tx empty, Tx Error and then enable them. */ 638 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 639 XIIC_INTR_BNB_MASK | 640 ((i2c->nmsgs > 1 || xiic_tx_space(i2c)) ? 641 XIIC_INTR_TX_HALF_MASK : 0)); 642 643 xiic_fill_tx_fifo(i2c); 644 } 645 646 static void __xiic_start_xfer(struct xiic_i2c *i2c) 647 { 648 int fifo_space = xiic_tx_fifo_space(i2c); 649 650 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 651 __func__, i2c->tx_msg, fifo_space); 652 653 if (!i2c->tx_msg) 654 return; 655 656 i2c->rx_pos = 0; 657 i2c->tx_pos = 0; 658 i2c->state = STATE_START; 659 if (i2c->tx_msg->flags & I2C_M_RD) { 660 /* we dont date putting several reads in the FIFO */ 661 xiic_start_recv(i2c); 662 } else { 663 xiic_start_send(i2c); 664 } 665 } 666 667 static int xiic_start_xfer(struct xiic_i2c *i2c, struct i2c_msg *msgs, int num) 668 { 669 int ret; 670 671 mutex_lock(&i2c->lock); 672 673 ret = xiic_busy(i2c); 674 if (ret) 675 goto out; 676 677 i2c->tx_msg = msgs; 678 i2c->rx_msg = NULL; 679 i2c->nmsgs = num; 680 init_completion(&i2c->completion); 681 682 ret = xiic_reinit(i2c); 683 if (!ret) 684 __xiic_start_xfer(i2c); 685 686 out: 687 mutex_unlock(&i2c->lock); 688 689 return ret; 690 } 691 692 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 693 { 694 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 695 int err; 696 697 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 698 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 699 700 err = pm_runtime_resume_and_get(i2c->dev); 701 if (err < 0) 702 return err; 703 704 err = xiic_start_xfer(i2c, msgs, num); 705 if (err < 0) { 706 dev_err(adap->dev.parent, "Error xiic_start_xfer\n"); 707 return err; 708 } 709 710 err = wait_for_completion_timeout(&i2c->completion, XIIC_XFER_TIMEOUT); 711 mutex_lock(&i2c->lock); 712 if (err == 0) { /* Timeout */ 713 i2c->tx_msg = NULL; 714 i2c->rx_msg = NULL; 715 i2c->nmsgs = 0; 716 err = -ETIMEDOUT; 717 } else if (err < 0) { /* Completion error */ 718 i2c->tx_msg = NULL; 719 i2c->rx_msg = NULL; 720 i2c->nmsgs = 0; 721 } else { 722 err = (i2c->state == STATE_DONE) ? num : -EIO; 723 } 724 mutex_unlock(&i2c->lock); 725 pm_runtime_mark_last_busy(i2c->dev); 726 pm_runtime_put_autosuspend(i2c->dev); 727 return err; 728 } 729 730 static u32 xiic_func(struct i2c_adapter *adap) 731 { 732 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 733 } 734 735 static const struct i2c_algorithm xiic_algorithm = { 736 .master_xfer = xiic_xfer, 737 .functionality = xiic_func, 738 }; 739 740 static const struct i2c_adapter_quirks xiic_quirks = { 741 .max_read_len = 255, 742 }; 743 744 static const struct i2c_adapter xiic_adapter = { 745 .owner = THIS_MODULE, 746 .class = I2C_CLASS_DEPRECATED, 747 .algo = &xiic_algorithm, 748 .quirks = &xiic_quirks, 749 }; 750 751 static int xiic_i2c_probe(struct platform_device *pdev) 752 { 753 struct xiic_i2c *i2c; 754 struct xiic_i2c_platform_data *pdata; 755 struct resource *res; 756 int ret, irq; 757 u8 i; 758 u32 sr; 759 760 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 761 if (!i2c) 762 return -ENOMEM; 763 764 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 765 i2c->base = devm_ioremap_resource(&pdev->dev, res); 766 if (IS_ERR(i2c->base)) 767 return PTR_ERR(i2c->base); 768 769 irq = platform_get_irq(pdev, 0); 770 if (irq < 0) 771 return irq; 772 773 pdata = dev_get_platdata(&pdev->dev); 774 775 /* hook up driver to tree */ 776 platform_set_drvdata(pdev, i2c); 777 i2c->adap = xiic_adapter; 778 i2c_set_adapdata(&i2c->adap, i2c); 779 i2c->adap.dev.parent = &pdev->dev; 780 i2c->adap.dev.of_node = pdev->dev.of_node; 781 snprintf(i2c->adap.name, sizeof(i2c->adap.name), 782 DRIVER_NAME " %s", pdev->name); 783 784 mutex_init(&i2c->lock); 785 786 i2c->clk = devm_clk_get(&pdev->dev, NULL); 787 if (IS_ERR(i2c->clk)) 788 return dev_err_probe(&pdev->dev, PTR_ERR(i2c->clk), 789 "input clock not found.\n"); 790 791 ret = clk_prepare_enable(i2c->clk); 792 if (ret) { 793 dev_err(&pdev->dev, "Unable to enable clock.\n"); 794 return ret; 795 } 796 i2c->dev = &pdev->dev; 797 pm_runtime_set_autosuspend_delay(i2c->dev, XIIC_PM_TIMEOUT); 798 pm_runtime_use_autosuspend(i2c->dev); 799 pm_runtime_set_active(i2c->dev); 800 pm_runtime_enable(i2c->dev); 801 ret = devm_request_threaded_irq(&pdev->dev, irq, NULL, 802 xiic_process, IRQF_ONESHOT, 803 pdev->name, i2c); 804 805 if (ret < 0) { 806 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 807 goto err_clk_dis; 808 } 809 810 i2c->singlemaster = 811 of_property_read_bool(pdev->dev.of_node, "single-master"); 812 813 /* 814 * Detect endianness 815 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 816 * set, assume that the endianness was wrong and swap. 817 */ 818 i2c->endianness = LITTLE; 819 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 820 /* Reset is cleared in xiic_reinit */ 821 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 822 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 823 i2c->endianness = BIG; 824 825 ret = xiic_reinit(i2c); 826 if (ret < 0) { 827 dev_err(&pdev->dev, "Cannot xiic_reinit\n"); 828 goto err_clk_dis; 829 } 830 831 /* add i2c adapter to i2c tree */ 832 ret = i2c_add_adapter(&i2c->adap); 833 if (ret) { 834 xiic_deinit(i2c); 835 goto err_clk_dis; 836 } 837 838 if (pdata) { 839 /* add in known devices to the bus */ 840 for (i = 0; i < pdata->num_devices; i++) 841 i2c_new_client_device(&i2c->adap, pdata->devices + i); 842 } 843 844 return 0; 845 846 err_clk_dis: 847 pm_runtime_set_suspended(&pdev->dev); 848 pm_runtime_disable(&pdev->dev); 849 clk_disable_unprepare(i2c->clk); 850 return ret; 851 } 852 853 static int xiic_i2c_remove(struct platform_device *pdev) 854 { 855 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 856 int ret; 857 858 /* remove adapter & data */ 859 i2c_del_adapter(&i2c->adap); 860 861 ret = pm_runtime_resume_and_get(i2c->dev); 862 if (ret < 0) 863 return ret; 864 865 xiic_deinit(i2c); 866 pm_runtime_put_sync(i2c->dev); 867 clk_disable_unprepare(i2c->clk); 868 pm_runtime_disable(&pdev->dev); 869 pm_runtime_set_suspended(&pdev->dev); 870 pm_runtime_dont_use_autosuspend(&pdev->dev); 871 872 return 0; 873 } 874 875 #if defined(CONFIG_OF) 876 static const struct of_device_id xiic_of_match[] = { 877 { .compatible = "xlnx,xps-iic-2.00.a", }, 878 {}, 879 }; 880 MODULE_DEVICE_TABLE(of, xiic_of_match); 881 #endif 882 883 static int __maybe_unused xiic_i2c_runtime_suspend(struct device *dev) 884 { 885 struct xiic_i2c *i2c = dev_get_drvdata(dev); 886 887 clk_disable(i2c->clk); 888 889 return 0; 890 } 891 892 static int __maybe_unused xiic_i2c_runtime_resume(struct device *dev) 893 { 894 struct xiic_i2c *i2c = dev_get_drvdata(dev); 895 int ret; 896 897 ret = clk_enable(i2c->clk); 898 if (ret) { 899 dev_err(dev, "Cannot enable clock.\n"); 900 return ret; 901 } 902 903 return 0; 904 } 905 906 static const struct dev_pm_ops xiic_dev_pm_ops = { 907 SET_RUNTIME_PM_OPS(xiic_i2c_runtime_suspend, 908 xiic_i2c_runtime_resume, NULL) 909 }; 910 911 static struct platform_driver xiic_i2c_driver = { 912 .probe = xiic_i2c_probe, 913 .remove = xiic_i2c_remove, 914 .driver = { 915 .name = DRIVER_NAME, 916 .of_match_table = of_match_ptr(xiic_of_match), 917 .pm = &xiic_dev_pm_ops, 918 }, 919 }; 920 921 module_platform_driver(xiic_i2c_driver); 922 923 MODULE_AUTHOR("info@mocean-labs.com"); 924 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 925 MODULE_LICENSE("GPL v2"); 926