1 /* 2 * i2c-xiic.c 3 * Copyright (c) 2002-2007 Xilinx Inc. 4 * Copyright (c) 2009-2010 Intel Corporation 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License version 2 as 8 * published by the Free Software Foundation. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * 16 * This code was implemented by Mocean Laboratories AB when porting linux 17 * to the automotive development board Russellville. The copyright holder 18 * as seen in the header is Intel corporation. 19 * Mocean Laboratories forked off the GNU/Linux platform work into a 20 * separate company called Pelagicore AB, which committed the code to the 21 * kernel. 22 */ 23 24 /* Supports: 25 * Xilinx IIC 26 */ 27 #include <linux/kernel.h> 28 #include <linux/module.h> 29 #include <linux/errno.h> 30 #include <linux/err.h> 31 #include <linux/delay.h> 32 #include <linux/platform_device.h> 33 #include <linux/i2c.h> 34 #include <linux/interrupt.h> 35 #include <linux/wait.h> 36 #include <linux/i2c-xiic.h> 37 #include <linux/io.h> 38 #include <linux/slab.h> 39 #include <linux/of.h> 40 41 #define DRIVER_NAME "xiic-i2c" 42 43 enum xilinx_i2c_state { 44 STATE_DONE, 45 STATE_ERROR, 46 STATE_START 47 }; 48 49 enum xiic_endian { 50 LITTLE, 51 BIG 52 }; 53 54 /** 55 * struct xiic_i2c - Internal representation of the XIIC I2C bus 56 * @base: Memory base of the HW registers 57 * @wait: Wait queue for callers 58 * @adap: Kernel adapter representation 59 * @tx_msg: Messages from above to be sent 60 * @lock: Mutual exclusion 61 * @tx_pos: Current pos in TX message 62 * @nmsgs: Number of messages in tx_msg 63 * @state: See STATE_ 64 * @rx_msg: Current RX message 65 * @rx_pos: Position within current RX message 66 * @endianness: big/little-endian byte order 67 */ 68 struct xiic_i2c { 69 void __iomem *base; 70 wait_queue_head_t wait; 71 struct i2c_adapter adap; 72 struct i2c_msg *tx_msg; 73 spinlock_t lock; 74 unsigned int tx_pos; 75 unsigned int nmsgs; 76 enum xilinx_i2c_state state; 77 struct i2c_msg *rx_msg; 78 int rx_pos; 79 enum xiic_endian endianness; 80 }; 81 82 83 #define XIIC_MSB_OFFSET 0 84 #define XIIC_REG_OFFSET (0x100+XIIC_MSB_OFFSET) 85 86 /* 87 * Register offsets in bytes from RegisterBase. Three is added to the 88 * base offset to access LSB (IBM style) of the word 89 */ 90 #define XIIC_CR_REG_OFFSET (0x00+XIIC_REG_OFFSET) /* Control Register */ 91 #define XIIC_SR_REG_OFFSET (0x04+XIIC_REG_OFFSET) /* Status Register */ 92 #define XIIC_DTR_REG_OFFSET (0x08+XIIC_REG_OFFSET) /* Data Tx Register */ 93 #define XIIC_DRR_REG_OFFSET (0x0C+XIIC_REG_OFFSET) /* Data Rx Register */ 94 #define XIIC_ADR_REG_OFFSET (0x10+XIIC_REG_OFFSET) /* Address Register */ 95 #define XIIC_TFO_REG_OFFSET (0x14+XIIC_REG_OFFSET) /* Tx FIFO Occupancy */ 96 #define XIIC_RFO_REG_OFFSET (0x18+XIIC_REG_OFFSET) /* Rx FIFO Occupancy */ 97 #define XIIC_TBA_REG_OFFSET (0x1C+XIIC_REG_OFFSET) /* 10 Bit Address reg */ 98 #define XIIC_RFD_REG_OFFSET (0x20+XIIC_REG_OFFSET) /* Rx FIFO Depth reg */ 99 #define XIIC_GPO_REG_OFFSET (0x24+XIIC_REG_OFFSET) /* Output Register */ 100 101 /* Control Register masks */ 102 #define XIIC_CR_ENABLE_DEVICE_MASK 0x01 /* Device enable = 1 */ 103 #define XIIC_CR_TX_FIFO_RESET_MASK 0x02 /* Transmit FIFO reset=1 */ 104 #define XIIC_CR_MSMS_MASK 0x04 /* Master starts Txing=1 */ 105 #define XIIC_CR_DIR_IS_TX_MASK 0x08 /* Dir of tx. Txing=1 */ 106 #define XIIC_CR_NO_ACK_MASK 0x10 /* Tx Ack. NO ack = 1 */ 107 #define XIIC_CR_REPEATED_START_MASK 0x20 /* Repeated start = 1 */ 108 #define XIIC_CR_GENERAL_CALL_MASK 0x40 /* Gen Call enabled = 1 */ 109 110 /* Status Register masks */ 111 #define XIIC_SR_GEN_CALL_MASK 0x01 /* 1=a mstr issued a GC */ 112 #define XIIC_SR_ADDR_AS_SLAVE_MASK 0x02 /* 1=when addr as slave */ 113 #define XIIC_SR_BUS_BUSY_MASK 0x04 /* 1 = bus is busy */ 114 #define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x08 /* 1=Dir: mstr <-- slave */ 115 #define XIIC_SR_TX_FIFO_FULL_MASK 0x10 /* 1 = Tx FIFO full */ 116 #define XIIC_SR_RX_FIFO_FULL_MASK 0x20 /* 1 = Rx FIFO full */ 117 #define XIIC_SR_RX_FIFO_EMPTY_MASK 0x40 /* 1 = Rx FIFO empty */ 118 #define XIIC_SR_TX_FIFO_EMPTY_MASK 0x80 /* 1 = Tx FIFO empty */ 119 120 /* Interrupt Status Register masks Interrupt occurs when... */ 121 #define XIIC_INTR_ARB_LOST_MASK 0x01 /* 1 = arbitration lost */ 122 #define XIIC_INTR_TX_ERROR_MASK 0x02 /* 1=Tx error/msg complete */ 123 #define XIIC_INTR_TX_EMPTY_MASK 0x04 /* 1 = Tx FIFO/reg empty */ 124 #define XIIC_INTR_RX_FULL_MASK 0x08 /* 1=Rx FIFO/reg=OCY level */ 125 #define XIIC_INTR_BNB_MASK 0x10 /* 1 = Bus not busy */ 126 #define XIIC_INTR_AAS_MASK 0x20 /* 1 = when addr as slave */ 127 #define XIIC_INTR_NAAS_MASK 0x40 /* 1 = not addr as slave */ 128 #define XIIC_INTR_TX_HALF_MASK 0x80 /* 1 = TX FIFO half empty */ 129 130 /* The following constants specify the depth of the FIFOs */ 131 #define IIC_RX_FIFO_DEPTH 16 /* Rx fifo capacity */ 132 #define IIC_TX_FIFO_DEPTH 16 /* Tx fifo capacity */ 133 134 /* The following constants specify groups of interrupts that are typically 135 * enabled or disables at the same time 136 */ 137 #define XIIC_TX_INTERRUPTS \ 138 (XIIC_INTR_TX_ERROR_MASK | XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK) 139 140 #define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) 141 142 /* The following constants are used with the following macros to specify the 143 * operation, a read or write operation. 144 */ 145 #define XIIC_READ_OPERATION 1 146 #define XIIC_WRITE_OPERATION 0 147 148 /* 149 * Tx Fifo upper bit masks. 150 */ 151 #define XIIC_TX_DYN_START_MASK 0x0100 /* 1 = Set dynamic start */ 152 #define XIIC_TX_DYN_STOP_MASK 0x0200 /* 1 = Set dynamic stop */ 153 154 /* 155 * The following constants define the register offsets for the Interrupt 156 * registers. There are some holes in the memory map for reserved addresses 157 * to allow other registers to be added and still match the memory map of the 158 * interrupt controller registers 159 */ 160 #define XIIC_DGIER_OFFSET 0x1C /* Device Global Interrupt Enable Register */ 161 #define XIIC_IISR_OFFSET 0x20 /* Interrupt Status Register */ 162 #define XIIC_IIER_OFFSET 0x28 /* Interrupt Enable Register */ 163 #define XIIC_RESETR_OFFSET 0x40 /* Reset Register */ 164 165 #define XIIC_RESET_MASK 0xAUL 166 167 /* 168 * The following constant is used for the device global interrupt enable 169 * register, to enable all interrupts for the device, this is the only bit 170 * in the register 171 */ 172 #define XIIC_GINTR_ENABLE_MASK 0x80000000UL 173 174 #define xiic_tx_space(i2c) ((i2c)->tx_msg->len - (i2c)->tx_pos) 175 #define xiic_rx_space(i2c) ((i2c)->rx_msg->len - (i2c)->rx_pos) 176 177 static void xiic_start_xfer(struct xiic_i2c *i2c); 178 static void __xiic_start_xfer(struct xiic_i2c *i2c); 179 180 /* 181 * For the register read and write functions, a little-endian and big-endian 182 * version are necessary. Endianness is detected during the probe function. 183 * Only the least significant byte [doublet] of the register are ever 184 * accessed. This requires an offset of 3 [2] from the base address for 185 * big-endian systems. 186 */ 187 188 static inline void xiic_setreg8(struct xiic_i2c *i2c, int reg, u8 value) 189 { 190 if (i2c->endianness == LITTLE) 191 iowrite8(value, i2c->base + reg); 192 else 193 iowrite8(value, i2c->base + reg + 3); 194 } 195 196 static inline u8 xiic_getreg8(struct xiic_i2c *i2c, int reg) 197 { 198 u8 ret; 199 200 if (i2c->endianness == LITTLE) 201 ret = ioread8(i2c->base + reg); 202 else 203 ret = ioread8(i2c->base + reg + 3); 204 return ret; 205 } 206 207 static inline void xiic_setreg16(struct xiic_i2c *i2c, int reg, u16 value) 208 { 209 if (i2c->endianness == LITTLE) 210 iowrite16(value, i2c->base + reg); 211 else 212 iowrite16be(value, i2c->base + reg + 2); 213 } 214 215 static inline void xiic_setreg32(struct xiic_i2c *i2c, int reg, int value) 216 { 217 if (i2c->endianness == LITTLE) 218 iowrite32(value, i2c->base + reg); 219 else 220 iowrite32be(value, i2c->base + reg); 221 } 222 223 static inline int xiic_getreg32(struct xiic_i2c *i2c, int reg) 224 { 225 u32 ret; 226 227 if (i2c->endianness == LITTLE) 228 ret = ioread32(i2c->base + reg); 229 else 230 ret = ioread32be(i2c->base + reg); 231 return ret; 232 } 233 234 static inline void xiic_irq_dis(struct xiic_i2c *i2c, u32 mask) 235 { 236 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 237 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier & ~mask); 238 } 239 240 static inline void xiic_irq_en(struct xiic_i2c *i2c, u32 mask) 241 { 242 u32 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 243 xiic_setreg32(i2c, XIIC_IIER_OFFSET, ier | mask); 244 } 245 246 static inline void xiic_irq_clr(struct xiic_i2c *i2c, u32 mask) 247 { 248 u32 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 249 xiic_setreg32(i2c, XIIC_IISR_OFFSET, isr & mask); 250 } 251 252 static inline void xiic_irq_clr_en(struct xiic_i2c *i2c, u32 mask) 253 { 254 xiic_irq_clr(i2c, mask); 255 xiic_irq_en(i2c, mask); 256 } 257 258 static void xiic_clear_rx_fifo(struct xiic_i2c *i2c) 259 { 260 u8 sr; 261 for (sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 262 !(sr & XIIC_SR_RX_FIFO_EMPTY_MASK); 263 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)) 264 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 265 } 266 267 static void xiic_reinit(struct xiic_i2c *i2c) 268 { 269 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 270 271 /* Set receive Fifo depth to maximum (zero based). */ 272 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, IIC_RX_FIFO_DEPTH - 1); 273 274 /* Reset Tx Fifo. */ 275 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 276 277 /* Enable IIC Device, remove Tx Fifo reset & disable general call. */ 278 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_ENABLE_DEVICE_MASK); 279 280 /* make sure RX fifo is empty */ 281 xiic_clear_rx_fifo(i2c); 282 283 /* Enable interrupts */ 284 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 285 286 xiic_irq_clr_en(i2c, XIIC_INTR_AAS_MASK | XIIC_INTR_ARB_LOST_MASK); 287 } 288 289 static void xiic_deinit(struct xiic_i2c *i2c) 290 { 291 u8 cr; 292 293 xiic_setreg32(i2c, XIIC_RESETR_OFFSET, XIIC_RESET_MASK); 294 295 /* Disable IIC Device. */ 296 cr = xiic_getreg8(i2c, XIIC_CR_REG_OFFSET); 297 xiic_setreg8(i2c, XIIC_CR_REG_OFFSET, cr & ~XIIC_CR_ENABLE_DEVICE_MASK); 298 } 299 300 static void xiic_read_rx(struct xiic_i2c *i2c) 301 { 302 u8 bytes_in_fifo; 303 int i; 304 305 bytes_in_fifo = xiic_getreg8(i2c, XIIC_RFO_REG_OFFSET) + 1; 306 307 dev_dbg(i2c->adap.dev.parent, 308 "%s entry, bytes in fifo: %d, msg: %d, SR: 0x%x, CR: 0x%x\n", 309 __func__, bytes_in_fifo, xiic_rx_space(i2c), 310 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 311 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 312 313 if (bytes_in_fifo > xiic_rx_space(i2c)) 314 bytes_in_fifo = xiic_rx_space(i2c); 315 316 for (i = 0; i < bytes_in_fifo; i++) 317 i2c->rx_msg->buf[i2c->rx_pos++] = 318 xiic_getreg8(i2c, XIIC_DRR_REG_OFFSET); 319 320 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, 321 (xiic_rx_space(i2c) > IIC_RX_FIFO_DEPTH) ? 322 IIC_RX_FIFO_DEPTH - 1 : xiic_rx_space(i2c) - 1); 323 } 324 325 static int xiic_tx_fifo_space(struct xiic_i2c *i2c) 326 { 327 /* return the actual space left in the FIFO */ 328 return IIC_TX_FIFO_DEPTH - xiic_getreg8(i2c, XIIC_TFO_REG_OFFSET) - 1; 329 } 330 331 static void xiic_fill_tx_fifo(struct xiic_i2c *i2c) 332 { 333 u8 fifo_space = xiic_tx_fifo_space(i2c); 334 int len = xiic_tx_space(i2c); 335 336 len = (len > fifo_space) ? fifo_space : len; 337 338 dev_dbg(i2c->adap.dev.parent, "%s entry, len: %d, fifo space: %d\n", 339 __func__, len, fifo_space); 340 341 while (len--) { 342 u16 data = i2c->tx_msg->buf[i2c->tx_pos++]; 343 if ((xiic_tx_space(i2c) == 0) && (i2c->nmsgs == 1)) { 344 /* last message in transfer -> STOP */ 345 data |= XIIC_TX_DYN_STOP_MASK; 346 dev_dbg(i2c->adap.dev.parent, "%s TX STOP\n", __func__); 347 } 348 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 349 } 350 } 351 352 static void xiic_wakeup(struct xiic_i2c *i2c, int code) 353 { 354 i2c->tx_msg = NULL; 355 i2c->rx_msg = NULL; 356 i2c->nmsgs = 0; 357 i2c->state = code; 358 wake_up(&i2c->wait); 359 } 360 361 static void xiic_process(struct xiic_i2c *i2c) 362 { 363 u32 pend, isr, ier; 364 u32 clr = 0; 365 366 /* Get the interrupt Status from the IPIF. There is no clearing of 367 * interrupts in the IPIF. Interrupts must be cleared at the source. 368 * To find which interrupts are pending; AND interrupts pending with 369 * interrupts masked. 370 */ 371 isr = xiic_getreg32(i2c, XIIC_IISR_OFFSET); 372 ier = xiic_getreg32(i2c, XIIC_IIER_OFFSET); 373 pend = isr & ier; 374 375 dev_dbg(i2c->adap.dev.parent, "%s: IER: 0x%x, ISR: 0x%x, pend: 0x%x\n", 376 __func__, ier, isr, pend); 377 dev_dbg(i2c->adap.dev.parent, "%s: SR: 0x%x, msg: %p, nmsgs: %d\n", 378 __func__, xiic_getreg8(i2c, XIIC_SR_REG_OFFSET), 379 i2c->tx_msg, i2c->nmsgs); 380 381 /* Do not processes a devices interrupts if the device has no 382 * interrupts pending 383 */ 384 if (!pend) 385 return; 386 387 /* Service requesting interrupt */ 388 if ((pend & XIIC_INTR_ARB_LOST_MASK) || 389 ((pend & XIIC_INTR_TX_ERROR_MASK) && 390 !(pend & XIIC_INTR_RX_FULL_MASK))) { 391 /* bus arbritration lost, or... 392 * Transmit error _OR_ RX completed 393 * if this happens when RX_FULL is not set 394 * this is probably a TX error 395 */ 396 397 dev_dbg(i2c->adap.dev.parent, "%s error\n", __func__); 398 399 /* dynamic mode seem to suffer from problems if we just flushes 400 * fifos and the next message is a TX with len 0 (only addr) 401 * reset the IP instead of just flush fifos 402 */ 403 xiic_reinit(i2c); 404 405 if (i2c->tx_msg) 406 xiic_wakeup(i2c, STATE_ERROR); 407 408 } else if (pend & XIIC_INTR_RX_FULL_MASK) { 409 /* Receive register/FIFO is full */ 410 411 clr = XIIC_INTR_RX_FULL_MASK; 412 if (!i2c->rx_msg) { 413 dev_dbg(i2c->adap.dev.parent, 414 "%s unexpexted RX IRQ\n", __func__); 415 xiic_clear_rx_fifo(i2c); 416 goto out; 417 } 418 419 xiic_read_rx(i2c); 420 if (xiic_rx_space(i2c) == 0) { 421 /* this is the last part of the message */ 422 i2c->rx_msg = NULL; 423 424 /* also clear TX error if there (RX complete) */ 425 clr |= (isr & XIIC_INTR_TX_ERROR_MASK); 426 427 dev_dbg(i2c->adap.dev.parent, 428 "%s end of message, nmsgs: %d\n", 429 __func__, i2c->nmsgs); 430 431 /* send next message if this wasn't the last, 432 * otherwise the transfer will be finialise when 433 * receiving the bus not busy interrupt 434 */ 435 if (i2c->nmsgs > 1) { 436 i2c->nmsgs--; 437 i2c->tx_msg++; 438 dev_dbg(i2c->adap.dev.parent, 439 "%s will start next...\n", __func__); 440 441 __xiic_start_xfer(i2c); 442 } 443 } 444 } else if (pend & XIIC_INTR_BNB_MASK) { 445 /* IIC bus has transitioned to not busy */ 446 clr = XIIC_INTR_BNB_MASK; 447 448 /* The bus is not busy, disable BusNotBusy interrupt */ 449 xiic_irq_dis(i2c, XIIC_INTR_BNB_MASK); 450 451 if (!i2c->tx_msg) 452 goto out; 453 454 if ((i2c->nmsgs == 1) && !i2c->rx_msg && 455 xiic_tx_space(i2c) == 0) 456 xiic_wakeup(i2c, STATE_DONE); 457 else 458 xiic_wakeup(i2c, STATE_ERROR); 459 460 } else if (pend & (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK)) { 461 /* Transmit register/FIFO is empty or ½ empty */ 462 463 clr = pend & 464 (XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_HALF_MASK); 465 466 if (!i2c->tx_msg) { 467 dev_dbg(i2c->adap.dev.parent, 468 "%s unexpexted TX IRQ\n", __func__); 469 goto out; 470 } 471 472 xiic_fill_tx_fifo(i2c); 473 474 /* current message sent and there is space in the fifo */ 475 if (!xiic_tx_space(i2c) && xiic_tx_fifo_space(i2c) >= 2) { 476 dev_dbg(i2c->adap.dev.parent, 477 "%s end of message sent, nmsgs: %d\n", 478 __func__, i2c->nmsgs); 479 if (i2c->nmsgs > 1) { 480 i2c->nmsgs--; 481 i2c->tx_msg++; 482 __xiic_start_xfer(i2c); 483 } else { 484 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 485 486 dev_dbg(i2c->adap.dev.parent, 487 "%s Got TX IRQ but no more to do...\n", 488 __func__); 489 } 490 } else if (!xiic_tx_space(i2c) && (i2c->nmsgs == 1)) 491 /* current frame is sent and is last, 492 * make sure to disable tx half 493 */ 494 xiic_irq_dis(i2c, XIIC_INTR_TX_HALF_MASK); 495 } else { 496 /* got IRQ which is not acked */ 497 dev_err(i2c->adap.dev.parent, "%s Got unexpected IRQ\n", 498 __func__); 499 clr = pend; 500 } 501 out: 502 dev_dbg(i2c->adap.dev.parent, "%s clr: 0x%x\n", __func__, clr); 503 504 xiic_setreg32(i2c, XIIC_IISR_OFFSET, clr); 505 } 506 507 static int xiic_bus_busy(struct xiic_i2c *i2c) 508 { 509 u8 sr = xiic_getreg8(i2c, XIIC_SR_REG_OFFSET); 510 511 return (sr & XIIC_SR_BUS_BUSY_MASK) ? -EBUSY : 0; 512 } 513 514 static int xiic_busy(struct xiic_i2c *i2c) 515 { 516 int tries = 3; 517 int err; 518 519 if (i2c->tx_msg) 520 return -EBUSY; 521 522 /* for instance if previous transfer was terminated due to TX error 523 * it might be that the bus is on it's way to become available 524 * give it at most 3 ms to wake 525 */ 526 err = xiic_bus_busy(i2c); 527 while (err && tries--) { 528 mdelay(1); 529 err = xiic_bus_busy(i2c); 530 } 531 532 return err; 533 } 534 535 static void xiic_start_recv(struct xiic_i2c *i2c) 536 { 537 u8 rx_watermark; 538 struct i2c_msg *msg = i2c->rx_msg = i2c->tx_msg; 539 540 /* Clear and enable Rx full interrupt. */ 541 xiic_irq_clr_en(i2c, XIIC_INTR_RX_FULL_MASK | XIIC_INTR_TX_ERROR_MASK); 542 543 /* we want to get all but last byte, because the TX_ERROR IRQ is used 544 * to inidicate error ACK on the address, and negative ack on the last 545 * received byte, so to not mix them receive all but last. 546 * In the case where there is only one byte to receive 547 * we can check if ERROR and RX full is set at the same time 548 */ 549 rx_watermark = msg->len; 550 if (rx_watermark > IIC_RX_FIFO_DEPTH) 551 rx_watermark = IIC_RX_FIFO_DEPTH; 552 xiic_setreg8(i2c, XIIC_RFD_REG_OFFSET, rx_watermark - 1); 553 554 if (!(msg->flags & I2C_M_NOSTART)) 555 /* write the address */ 556 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 557 (msg->addr << 1) | XIIC_READ_OPERATION | 558 XIIC_TX_DYN_START_MASK); 559 560 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 561 562 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, 563 msg->len | ((i2c->nmsgs == 1) ? XIIC_TX_DYN_STOP_MASK : 0)); 564 if (i2c->nmsgs == 1) 565 /* very last, enable bus not busy as well */ 566 xiic_irq_clr_en(i2c, XIIC_INTR_BNB_MASK); 567 568 /* the message is tx:ed */ 569 i2c->tx_pos = msg->len; 570 } 571 572 static void xiic_start_send(struct xiic_i2c *i2c) 573 { 574 struct i2c_msg *msg = i2c->tx_msg; 575 576 xiic_irq_clr(i2c, XIIC_INTR_TX_ERROR_MASK); 577 578 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, len: %d", 579 __func__, msg, msg->len); 580 dev_dbg(i2c->adap.dev.parent, "%s entry, ISR: 0x%x, CR: 0x%x\n", 581 __func__, xiic_getreg32(i2c, XIIC_IISR_OFFSET), 582 xiic_getreg8(i2c, XIIC_CR_REG_OFFSET)); 583 584 if (!(msg->flags & I2C_M_NOSTART)) { 585 /* write the address */ 586 u16 data = ((msg->addr << 1) & 0xfe) | XIIC_WRITE_OPERATION | 587 XIIC_TX_DYN_START_MASK; 588 if ((i2c->nmsgs == 1) && msg->len == 0) 589 /* no data and last message -> add STOP */ 590 data |= XIIC_TX_DYN_STOP_MASK; 591 592 xiic_setreg16(i2c, XIIC_DTR_REG_OFFSET, data); 593 } 594 595 xiic_fill_tx_fifo(i2c); 596 597 /* Clear any pending Tx empty, Tx Error and then enable them. */ 598 xiic_irq_clr_en(i2c, XIIC_INTR_TX_EMPTY_MASK | XIIC_INTR_TX_ERROR_MASK | 599 XIIC_INTR_BNB_MASK); 600 } 601 602 static irqreturn_t xiic_isr(int irq, void *dev_id) 603 { 604 struct xiic_i2c *i2c = dev_id; 605 606 spin_lock(&i2c->lock); 607 /* disable interrupts globally */ 608 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 609 610 dev_dbg(i2c->adap.dev.parent, "%s entry\n", __func__); 611 612 xiic_process(i2c); 613 614 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 615 spin_unlock(&i2c->lock); 616 617 return IRQ_HANDLED; 618 } 619 620 static void __xiic_start_xfer(struct xiic_i2c *i2c) 621 { 622 int first = 1; 623 int fifo_space = xiic_tx_fifo_space(i2c); 624 dev_dbg(i2c->adap.dev.parent, "%s entry, msg: %p, fifos space: %d\n", 625 __func__, i2c->tx_msg, fifo_space); 626 627 if (!i2c->tx_msg) 628 return; 629 630 i2c->rx_pos = 0; 631 i2c->tx_pos = 0; 632 i2c->state = STATE_START; 633 while ((fifo_space >= 2) && (first || (i2c->nmsgs > 1))) { 634 if (!first) { 635 i2c->nmsgs--; 636 i2c->tx_msg++; 637 i2c->tx_pos = 0; 638 } else 639 first = 0; 640 641 if (i2c->tx_msg->flags & I2C_M_RD) { 642 /* we dont date putting several reads in the FIFO */ 643 xiic_start_recv(i2c); 644 return; 645 } else { 646 xiic_start_send(i2c); 647 if (xiic_tx_space(i2c) != 0) { 648 /* the message could not be completely sent */ 649 break; 650 } 651 } 652 653 fifo_space = xiic_tx_fifo_space(i2c); 654 } 655 656 /* there are more messages or the current one could not be completely 657 * put into the FIFO, also enable the half empty interrupt 658 */ 659 if (i2c->nmsgs > 1 || xiic_tx_space(i2c)) 660 xiic_irq_clr_en(i2c, XIIC_INTR_TX_HALF_MASK); 661 662 } 663 664 static void xiic_start_xfer(struct xiic_i2c *i2c) 665 { 666 unsigned long flags; 667 668 spin_lock_irqsave(&i2c->lock, flags); 669 xiic_reinit(i2c); 670 /* disable interrupts globally */ 671 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, 0); 672 spin_unlock_irqrestore(&i2c->lock, flags); 673 674 __xiic_start_xfer(i2c); 675 xiic_setreg32(i2c, XIIC_DGIER_OFFSET, XIIC_GINTR_ENABLE_MASK); 676 } 677 678 static int xiic_xfer(struct i2c_adapter *adap, struct i2c_msg *msgs, int num) 679 { 680 struct xiic_i2c *i2c = i2c_get_adapdata(adap); 681 int err; 682 683 dev_dbg(adap->dev.parent, "%s entry SR: 0x%x\n", __func__, 684 xiic_getreg8(i2c, XIIC_SR_REG_OFFSET)); 685 686 err = xiic_busy(i2c); 687 if (err) 688 return err; 689 690 i2c->tx_msg = msgs; 691 i2c->nmsgs = num; 692 693 xiic_start_xfer(i2c); 694 695 if (wait_event_timeout(i2c->wait, (i2c->state == STATE_ERROR) || 696 (i2c->state == STATE_DONE), HZ)) 697 return (i2c->state == STATE_DONE) ? num : -EIO; 698 else { 699 i2c->tx_msg = NULL; 700 i2c->rx_msg = NULL; 701 i2c->nmsgs = 0; 702 return -ETIMEDOUT; 703 } 704 } 705 706 static u32 xiic_func(struct i2c_adapter *adap) 707 { 708 return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL; 709 } 710 711 static const struct i2c_algorithm xiic_algorithm = { 712 .master_xfer = xiic_xfer, 713 .functionality = xiic_func, 714 }; 715 716 static struct i2c_adapter xiic_adapter = { 717 .owner = THIS_MODULE, 718 .name = DRIVER_NAME, 719 .class = I2C_CLASS_DEPRECATED, 720 .algo = &xiic_algorithm, 721 }; 722 723 724 static int xiic_i2c_probe(struct platform_device *pdev) 725 { 726 struct xiic_i2c *i2c; 727 struct xiic_i2c_platform_data *pdata; 728 struct resource *res; 729 int ret, irq; 730 u8 i; 731 u32 sr; 732 733 i2c = devm_kzalloc(&pdev->dev, sizeof(*i2c), GFP_KERNEL); 734 if (!i2c) 735 return -ENOMEM; 736 737 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 738 i2c->base = devm_ioremap_resource(&pdev->dev, res); 739 if (IS_ERR(i2c->base)) 740 return PTR_ERR(i2c->base); 741 742 irq = platform_get_irq(pdev, 0); 743 if (irq < 0) 744 return irq; 745 746 pdata = dev_get_platdata(&pdev->dev); 747 748 /* hook up driver to tree */ 749 platform_set_drvdata(pdev, i2c); 750 i2c->adap = xiic_adapter; 751 i2c_set_adapdata(&i2c->adap, i2c); 752 i2c->adap.dev.parent = &pdev->dev; 753 i2c->adap.dev.of_node = pdev->dev.of_node; 754 755 spin_lock_init(&i2c->lock); 756 init_waitqueue_head(&i2c->wait); 757 758 ret = devm_request_irq(&pdev->dev, irq, xiic_isr, 0, pdev->name, i2c); 759 if (ret < 0) { 760 dev_err(&pdev->dev, "Cannot claim IRQ\n"); 761 return ret; 762 } 763 764 /* 765 * Detect endianness 766 * Try to reset the TX FIFO. Then check the EMPTY flag. If it is not 767 * set, assume that the endianness was wrong and swap. 768 */ 769 i2c->endianness = LITTLE; 770 xiic_setreg32(i2c, XIIC_CR_REG_OFFSET, XIIC_CR_TX_FIFO_RESET_MASK); 771 /* Reset is cleared in xiic_reinit */ 772 sr = xiic_getreg32(i2c, XIIC_SR_REG_OFFSET); 773 if (!(sr & XIIC_SR_TX_FIFO_EMPTY_MASK)) 774 i2c->endianness = BIG; 775 776 xiic_reinit(i2c); 777 778 /* add i2c adapter to i2c tree */ 779 ret = i2c_add_adapter(&i2c->adap); 780 if (ret) { 781 dev_err(&pdev->dev, "Failed to add adapter\n"); 782 xiic_deinit(i2c); 783 return ret; 784 } 785 786 if (pdata) { 787 /* add in known devices to the bus */ 788 for (i = 0; i < pdata->num_devices; i++) 789 i2c_new_device(&i2c->adap, pdata->devices + i); 790 } 791 792 return 0; 793 } 794 795 static int xiic_i2c_remove(struct platform_device *pdev) 796 { 797 struct xiic_i2c *i2c = platform_get_drvdata(pdev); 798 799 /* remove adapter & data */ 800 i2c_del_adapter(&i2c->adap); 801 802 xiic_deinit(i2c); 803 804 return 0; 805 } 806 807 #if defined(CONFIG_OF) 808 static const struct of_device_id xiic_of_match[] = { 809 { .compatible = "xlnx,xps-iic-2.00.a", }, 810 {}, 811 }; 812 MODULE_DEVICE_TABLE(of, xiic_of_match); 813 #endif 814 815 static struct platform_driver xiic_i2c_driver = { 816 .probe = xiic_i2c_probe, 817 .remove = xiic_i2c_remove, 818 .driver = { 819 .name = DRIVER_NAME, 820 .of_match_table = of_match_ptr(xiic_of_match), 821 }, 822 }; 823 824 module_platform_driver(xiic_i2c_driver); 825 826 MODULE_AUTHOR("info@mocean-labs.com"); 827 MODULE_DESCRIPTION("Xilinx I2C bus driver"); 828 MODULE_LICENSE("GPL v2"); 829 MODULE_ALIAS("platform:"DRIVER_NAME); 830