1 /* 2 Copyright (c) 1998 - 2002 Frodo Looijaard <frodol@dds.nl> and 3 Philip Edelbrock <phil@netroedge.com> 4 5 This program is free software; you can redistribute it and/or modify 6 it under the terms of the GNU General Public License as published by 7 the Free Software Foundation; either version 2 of the License, or 8 (at your option) any later version. 9 10 This program is distributed in the hope that it will be useful, 11 but WITHOUT ANY WARRANTY; without even the implied warranty of 12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 GNU General Public License for more details. 14 */ 15 16 /* 17 Supports: 18 Intel PIIX4, 440MX 19 Serverworks OSB4, CSB5, CSB6, HT-1000, HT-1100 20 ATI IXP200, IXP300, IXP400, SB600, SB700/SP5100, SB800 21 AMD Hudson-2, ML, CZ 22 SMSC Victory66 23 24 Note: we assume there can only be one device, with one or more 25 SMBus interfaces. 26 The device can register multiple i2c_adapters (up to PIIX4_MAX_ADAPTERS). 27 For devices supporting multiple ports the i2c_adapter should provide 28 an i2c_algorithm to access them. 29 */ 30 31 #include <linux/module.h> 32 #include <linux/moduleparam.h> 33 #include <linux/pci.h> 34 #include <linux/kernel.h> 35 #include <linux/delay.h> 36 #include <linux/stddef.h> 37 #include <linux/ioport.h> 38 #include <linux/i2c.h> 39 #include <linux/slab.h> 40 #include <linux/dmi.h> 41 #include <linux/acpi.h> 42 #include <linux/io.h> 43 #include <linux/mutex.h> 44 45 46 /* PIIX4 SMBus address offsets */ 47 #define SMBHSTSTS (0 + piix4_smba) 48 #define SMBHSLVSTS (1 + piix4_smba) 49 #define SMBHSTCNT (2 + piix4_smba) 50 #define SMBHSTCMD (3 + piix4_smba) 51 #define SMBHSTADD (4 + piix4_smba) 52 #define SMBHSTDAT0 (5 + piix4_smba) 53 #define SMBHSTDAT1 (6 + piix4_smba) 54 #define SMBBLKDAT (7 + piix4_smba) 55 #define SMBSLVCNT (8 + piix4_smba) 56 #define SMBSHDWCMD (9 + piix4_smba) 57 #define SMBSLVEVT (0xA + piix4_smba) 58 #define SMBSLVDAT (0xC + piix4_smba) 59 60 /* count for request_region */ 61 #define SMBIOSIZE 9 62 63 /* PCI Address Constants */ 64 #define SMBBA 0x090 65 #define SMBHSTCFG 0x0D2 66 #define SMBSLVC 0x0D3 67 #define SMBSHDW1 0x0D4 68 #define SMBSHDW2 0x0D5 69 #define SMBREV 0x0D6 70 71 /* Other settings */ 72 #define MAX_TIMEOUT 500 73 #define ENABLE_INT9 0 74 75 /* PIIX4 constants */ 76 #define PIIX4_QUICK 0x00 77 #define PIIX4_BYTE 0x04 78 #define PIIX4_BYTE_DATA 0x08 79 #define PIIX4_WORD_DATA 0x0C 80 #define PIIX4_BLOCK_DATA 0x14 81 82 /* Multi-port constants */ 83 #define PIIX4_MAX_ADAPTERS 4 84 85 /* SB800 constants */ 86 #define SB800_PIIX4_SMB_IDX 0xcd6 87 88 /* 89 * SB800 port is selected by bits 2:1 of the smb_en register (0x2c) 90 * or the smb_sel register (0x2e), depending on bit 0 of register 0x2f. 91 * Hudson-2/Bolton port is always selected by bits 2:1 of register 0x2f. 92 */ 93 #define SB800_PIIX4_PORT_IDX 0x2c 94 #define SB800_PIIX4_PORT_IDX_ALT 0x2e 95 #define SB800_PIIX4_PORT_IDX_SEL 0x2f 96 #define SB800_PIIX4_PORT_IDX_MASK 0x06 97 98 /* insmod parameters */ 99 100 /* If force is set to anything different from 0, we forcibly enable the 101 PIIX4. DANGEROUS! */ 102 static int force; 103 module_param (force, int, 0); 104 MODULE_PARM_DESC(force, "Forcibly enable the PIIX4. DANGEROUS!"); 105 106 /* If force_addr is set to anything different from 0, we forcibly enable 107 the PIIX4 at the given address. VERY DANGEROUS! */ 108 static int force_addr; 109 module_param_hw(force_addr, int, ioport, 0); 110 MODULE_PARM_DESC(force_addr, 111 "Forcibly enable the PIIX4 at the given address. " 112 "EXTREMELY DANGEROUS!"); 113 114 static int srvrworks_csb5_delay; 115 static struct pci_driver piix4_driver; 116 117 static const struct dmi_system_id piix4_dmi_blacklist[] = { 118 { 119 .ident = "Sapphire AM2RD790", 120 .matches = { 121 DMI_MATCH(DMI_BOARD_VENDOR, "SAPPHIRE Inc."), 122 DMI_MATCH(DMI_BOARD_NAME, "PC-AM2RD790"), 123 }, 124 }, 125 { 126 .ident = "DFI Lanparty UT 790FX", 127 .matches = { 128 DMI_MATCH(DMI_BOARD_VENDOR, "DFI Inc."), 129 DMI_MATCH(DMI_BOARD_NAME, "LP UT 790FX"), 130 }, 131 }, 132 { } 133 }; 134 135 /* The IBM entry is in a separate table because we only check it 136 on Intel-based systems */ 137 static const struct dmi_system_id piix4_dmi_ibm[] = { 138 { 139 .ident = "IBM", 140 .matches = { DMI_MATCH(DMI_SYS_VENDOR, "IBM"), }, 141 }, 142 { }, 143 }; 144 145 /* 146 * SB800 globals 147 * piix4_mutex_sb800 protects piix4_port_sel_sb800 and the pair 148 * of I/O ports at SB800_PIIX4_SMB_IDX. 149 */ 150 static DEFINE_MUTEX(piix4_mutex_sb800); 151 static u8 piix4_port_sel_sb800; 152 static const char *piix4_main_port_names_sb800[PIIX4_MAX_ADAPTERS] = { 153 " port 0", " port 2", " port 3", " port 4" 154 }; 155 static const char *piix4_aux_port_name_sb800 = " port 1"; 156 157 struct i2c_piix4_adapdata { 158 unsigned short smba; 159 160 /* SB800 */ 161 bool sb800_main; 162 u8 port; /* Port number, shifted */ 163 }; 164 165 static int piix4_setup(struct pci_dev *PIIX4_dev, 166 const struct pci_device_id *id) 167 { 168 unsigned char temp; 169 unsigned short piix4_smba; 170 171 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_SERVERWORKS) && 172 (PIIX4_dev->device == PCI_DEVICE_ID_SERVERWORKS_CSB5)) 173 srvrworks_csb5_delay = 1; 174 175 /* On some motherboards, it was reported that accessing the SMBus 176 caused severe hardware problems */ 177 if (dmi_check_system(piix4_dmi_blacklist)) { 178 dev_err(&PIIX4_dev->dev, 179 "Accessing the SMBus on this system is unsafe!\n"); 180 return -EPERM; 181 } 182 183 /* Don't access SMBus on IBM systems which get corrupted eeproms */ 184 if (dmi_check_system(piix4_dmi_ibm) && 185 PIIX4_dev->vendor == PCI_VENDOR_ID_INTEL) { 186 dev_err(&PIIX4_dev->dev, "IBM system detected; this module " 187 "may corrupt your serial eeprom! Refusing to load " 188 "module!\n"); 189 return -EPERM; 190 } 191 192 /* Determine the address of the SMBus areas */ 193 if (force_addr) { 194 piix4_smba = force_addr & 0xfff0; 195 force = 0; 196 } else { 197 pci_read_config_word(PIIX4_dev, SMBBA, &piix4_smba); 198 piix4_smba &= 0xfff0; 199 if(piix4_smba == 0) { 200 dev_err(&PIIX4_dev->dev, "SMBus base address " 201 "uninitialized - upgrade BIOS or use " 202 "force_addr=0xaddr\n"); 203 return -ENODEV; 204 } 205 } 206 207 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 208 return -ENODEV; 209 210 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 211 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 212 piix4_smba); 213 return -EBUSY; 214 } 215 216 pci_read_config_byte(PIIX4_dev, SMBHSTCFG, &temp); 217 218 /* If force_addr is set, we program the new address here. Just to make 219 sure, we disable the PIIX4 first. */ 220 if (force_addr) { 221 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp & 0xfe); 222 pci_write_config_word(PIIX4_dev, SMBBA, piix4_smba); 223 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, temp | 0x01); 224 dev_info(&PIIX4_dev->dev, "WARNING: SMBus interface set to " 225 "new address %04x!\n", piix4_smba); 226 } else if ((temp & 1) == 0) { 227 if (force) { 228 /* This should never need to be done, but has been 229 * noted that many Dell machines have the SMBus 230 * interface on the PIIX4 disabled!? NOTE: This assumes 231 * I/O space and other allocations WERE done by the 232 * Bios! Don't complain if your hardware does weird 233 * things after enabling this. :') Check for Bios 234 * updates before resorting to this. 235 */ 236 pci_write_config_byte(PIIX4_dev, SMBHSTCFG, 237 temp | 1); 238 dev_notice(&PIIX4_dev->dev, 239 "WARNING: SMBus interface has been FORCEFULLY ENABLED!\n"); 240 } else { 241 dev_err(&PIIX4_dev->dev, 242 "SMBus Host Controller not enabled!\n"); 243 release_region(piix4_smba, SMBIOSIZE); 244 return -ENODEV; 245 } 246 } 247 248 if (((temp & 0x0E) == 8) || ((temp & 0x0E) == 2)) 249 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 250 else if ((temp & 0x0E) == 0) 251 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 252 else 253 dev_err(&PIIX4_dev->dev, "Illegal Interrupt configuration " 254 "(or code out of date)!\n"); 255 256 pci_read_config_byte(PIIX4_dev, SMBREV, &temp); 257 dev_info(&PIIX4_dev->dev, 258 "SMBus Host Controller at 0x%x, revision %d\n", 259 piix4_smba, temp); 260 261 return piix4_smba; 262 } 263 264 static int piix4_setup_sb800(struct pci_dev *PIIX4_dev, 265 const struct pci_device_id *id, u8 aux) 266 { 267 unsigned short piix4_smba; 268 u8 smba_en_lo, smba_en_hi, smb_en, smb_en_status, port_sel; 269 u8 i2ccfg, i2ccfg_offset = 0x10; 270 271 /* SB800 and later SMBus does not support forcing address */ 272 if (force || force_addr) { 273 dev_err(&PIIX4_dev->dev, "SMBus does not support " 274 "forcing address!\n"); 275 return -EINVAL; 276 } 277 278 /* Determine the address of the SMBus areas */ 279 if ((PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 280 PIIX4_dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS && 281 PIIX4_dev->revision >= 0x41) || 282 (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD && 283 PIIX4_dev->device == PCI_DEVICE_ID_AMD_KERNCZ_SMBUS && 284 PIIX4_dev->revision >= 0x49)) 285 smb_en = 0x00; 286 else 287 smb_en = (aux) ? 0x28 : 0x2c; 288 289 mutex_lock(&piix4_mutex_sb800); 290 outb_p(smb_en, SB800_PIIX4_SMB_IDX); 291 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 292 outb_p(smb_en + 1, SB800_PIIX4_SMB_IDX); 293 smba_en_hi = inb_p(SB800_PIIX4_SMB_IDX + 1); 294 mutex_unlock(&piix4_mutex_sb800); 295 296 if (!smb_en) { 297 smb_en_status = smba_en_lo & 0x10; 298 piix4_smba = smba_en_hi << 8; 299 if (aux) 300 piix4_smba |= 0x20; 301 } else { 302 smb_en_status = smba_en_lo & 0x01; 303 piix4_smba = ((smba_en_hi << 8) | smba_en_lo) & 0xffe0; 304 } 305 306 if (!smb_en_status) { 307 dev_err(&PIIX4_dev->dev, 308 "SMBus Host Controller not enabled!\n"); 309 return -ENODEV; 310 } 311 312 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 313 return -ENODEV; 314 315 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 316 dev_err(&PIIX4_dev->dev, "SMBus region 0x%x already in use!\n", 317 piix4_smba); 318 return -EBUSY; 319 } 320 321 /* Aux SMBus does not support IRQ information */ 322 if (aux) { 323 dev_info(&PIIX4_dev->dev, 324 "Auxiliary SMBus Host Controller at 0x%x\n", 325 piix4_smba); 326 return piix4_smba; 327 } 328 329 /* Request the SMBus I2C bus config region */ 330 if (!request_region(piix4_smba + i2ccfg_offset, 1, "i2ccfg")) { 331 dev_err(&PIIX4_dev->dev, "SMBus I2C bus config region " 332 "0x%x already in use!\n", piix4_smba + i2ccfg_offset); 333 release_region(piix4_smba, SMBIOSIZE); 334 return -EBUSY; 335 } 336 i2ccfg = inb_p(piix4_smba + i2ccfg_offset); 337 release_region(piix4_smba + i2ccfg_offset, 1); 338 339 if (i2ccfg & 1) 340 dev_dbg(&PIIX4_dev->dev, "Using IRQ for SMBus\n"); 341 else 342 dev_dbg(&PIIX4_dev->dev, "Using SMI# for SMBus\n"); 343 344 dev_info(&PIIX4_dev->dev, 345 "SMBus Host Controller at 0x%x, revision %d\n", 346 piix4_smba, i2ccfg >> 4); 347 348 /* Find which register is used for port selection */ 349 if (PIIX4_dev->vendor == PCI_VENDOR_ID_AMD) { 350 piix4_port_sel_sb800 = SB800_PIIX4_PORT_IDX_ALT; 351 } else { 352 mutex_lock(&piix4_mutex_sb800); 353 outb_p(SB800_PIIX4_PORT_IDX_SEL, SB800_PIIX4_SMB_IDX); 354 port_sel = inb_p(SB800_PIIX4_SMB_IDX + 1); 355 piix4_port_sel_sb800 = (port_sel & 0x01) ? 356 SB800_PIIX4_PORT_IDX_ALT : 357 SB800_PIIX4_PORT_IDX; 358 mutex_unlock(&piix4_mutex_sb800); 359 } 360 361 dev_info(&PIIX4_dev->dev, 362 "Using register 0x%02x for SMBus port selection\n", 363 (unsigned int)piix4_port_sel_sb800); 364 365 return piix4_smba; 366 } 367 368 static int piix4_setup_aux(struct pci_dev *PIIX4_dev, 369 const struct pci_device_id *id, 370 unsigned short base_reg_addr) 371 { 372 /* Set up auxiliary SMBus controllers found on some 373 * AMD chipsets e.g. SP5100 (SB700 derivative) */ 374 375 unsigned short piix4_smba; 376 377 /* Read address of auxiliary SMBus controller */ 378 pci_read_config_word(PIIX4_dev, base_reg_addr, &piix4_smba); 379 if ((piix4_smba & 1) == 0) { 380 dev_dbg(&PIIX4_dev->dev, 381 "Auxiliary SMBus controller not enabled\n"); 382 return -ENODEV; 383 } 384 385 piix4_smba &= 0xfff0; 386 if (piix4_smba == 0) { 387 dev_dbg(&PIIX4_dev->dev, 388 "Auxiliary SMBus base address uninitialized\n"); 389 return -ENODEV; 390 } 391 392 if (acpi_check_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) 393 return -ENODEV; 394 395 if (!request_region(piix4_smba, SMBIOSIZE, piix4_driver.name)) { 396 dev_err(&PIIX4_dev->dev, "Auxiliary SMBus region 0x%x " 397 "already in use!\n", piix4_smba); 398 return -EBUSY; 399 } 400 401 dev_info(&PIIX4_dev->dev, 402 "Auxiliary SMBus Host Controller at 0x%x\n", 403 piix4_smba); 404 405 return piix4_smba; 406 } 407 408 static int piix4_transaction(struct i2c_adapter *piix4_adapter) 409 { 410 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(piix4_adapter); 411 unsigned short piix4_smba = adapdata->smba; 412 int temp; 413 int result = 0; 414 int timeout = 0; 415 416 dev_dbg(&piix4_adapter->dev, "Transaction (pre): CNT=%02x, CMD=%02x, " 417 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 418 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 419 inb_p(SMBHSTDAT1)); 420 421 /* Make sure the SMBus host is ready to start transmitting */ 422 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 423 dev_dbg(&piix4_adapter->dev, "SMBus busy (%02x). " 424 "Resetting...\n", temp); 425 outb_p(temp, SMBHSTSTS); 426 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 427 dev_err(&piix4_adapter->dev, "Failed! (%02x)\n", temp); 428 return -EBUSY; 429 } else { 430 dev_dbg(&piix4_adapter->dev, "Successful!\n"); 431 } 432 } 433 434 /* start the transaction by setting bit 6 */ 435 outb_p(inb(SMBHSTCNT) | 0x040, SMBHSTCNT); 436 437 /* We will always wait for a fraction of a second! (See PIIX4 docs errata) */ 438 if (srvrworks_csb5_delay) /* Extra delay for SERVERWORKS_CSB5 */ 439 msleep(2); 440 else 441 msleep(1); 442 443 while ((++timeout < MAX_TIMEOUT) && 444 ((temp = inb_p(SMBHSTSTS)) & 0x01)) 445 msleep(1); 446 447 /* If the SMBus is still busy, we give up */ 448 if (timeout == MAX_TIMEOUT) { 449 dev_err(&piix4_adapter->dev, "SMBus Timeout!\n"); 450 result = -ETIMEDOUT; 451 } 452 453 if (temp & 0x10) { 454 result = -EIO; 455 dev_err(&piix4_adapter->dev, "Error: Failed bus transaction\n"); 456 } 457 458 if (temp & 0x08) { 459 result = -EIO; 460 dev_dbg(&piix4_adapter->dev, "Bus collision! SMBus may be " 461 "locked until next hard reset. (sorry!)\n"); 462 /* Clock stops and slave is stuck in mid-transmission */ 463 } 464 465 if (temp & 0x04) { 466 result = -ENXIO; 467 dev_dbg(&piix4_adapter->dev, "Error: no response!\n"); 468 } 469 470 if (inb_p(SMBHSTSTS) != 0x00) 471 outb_p(inb(SMBHSTSTS), SMBHSTSTS); 472 473 if ((temp = inb_p(SMBHSTSTS)) != 0x00) { 474 dev_err(&piix4_adapter->dev, "Failed reset at end of " 475 "transaction (%02x)\n", temp); 476 } 477 dev_dbg(&piix4_adapter->dev, "Transaction (post): CNT=%02x, CMD=%02x, " 478 "ADD=%02x, DAT0=%02x, DAT1=%02x\n", inb_p(SMBHSTCNT), 479 inb_p(SMBHSTCMD), inb_p(SMBHSTADD), inb_p(SMBHSTDAT0), 480 inb_p(SMBHSTDAT1)); 481 return result; 482 } 483 484 /* Return negative errno on error. */ 485 static s32 piix4_access(struct i2c_adapter * adap, u16 addr, 486 unsigned short flags, char read_write, 487 u8 command, int size, union i2c_smbus_data * data) 488 { 489 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 490 unsigned short piix4_smba = adapdata->smba; 491 int i, len; 492 int status; 493 494 switch (size) { 495 case I2C_SMBUS_QUICK: 496 outb_p((addr << 1) | read_write, 497 SMBHSTADD); 498 size = PIIX4_QUICK; 499 break; 500 case I2C_SMBUS_BYTE: 501 outb_p((addr << 1) | read_write, 502 SMBHSTADD); 503 if (read_write == I2C_SMBUS_WRITE) 504 outb_p(command, SMBHSTCMD); 505 size = PIIX4_BYTE; 506 break; 507 case I2C_SMBUS_BYTE_DATA: 508 outb_p((addr << 1) | read_write, 509 SMBHSTADD); 510 outb_p(command, SMBHSTCMD); 511 if (read_write == I2C_SMBUS_WRITE) 512 outb_p(data->byte, SMBHSTDAT0); 513 size = PIIX4_BYTE_DATA; 514 break; 515 case I2C_SMBUS_WORD_DATA: 516 outb_p((addr << 1) | read_write, 517 SMBHSTADD); 518 outb_p(command, SMBHSTCMD); 519 if (read_write == I2C_SMBUS_WRITE) { 520 outb_p(data->word & 0xff, SMBHSTDAT0); 521 outb_p((data->word & 0xff00) >> 8, SMBHSTDAT1); 522 } 523 size = PIIX4_WORD_DATA; 524 break; 525 case I2C_SMBUS_BLOCK_DATA: 526 outb_p((addr << 1) | read_write, 527 SMBHSTADD); 528 outb_p(command, SMBHSTCMD); 529 if (read_write == I2C_SMBUS_WRITE) { 530 len = data->block[0]; 531 if (len == 0 || len > I2C_SMBUS_BLOCK_MAX) 532 return -EINVAL; 533 outb_p(len, SMBHSTDAT0); 534 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 535 for (i = 1; i <= len; i++) 536 outb_p(data->block[i], SMBBLKDAT); 537 } 538 size = PIIX4_BLOCK_DATA; 539 break; 540 default: 541 dev_warn(&adap->dev, "Unsupported transaction %d\n", size); 542 return -EOPNOTSUPP; 543 } 544 545 outb_p((size & 0x1C) + (ENABLE_INT9 & 1), SMBHSTCNT); 546 547 status = piix4_transaction(adap); 548 if (status) 549 return status; 550 551 if ((read_write == I2C_SMBUS_WRITE) || (size == PIIX4_QUICK)) 552 return 0; 553 554 555 switch (size) { 556 case PIIX4_BYTE: 557 case PIIX4_BYTE_DATA: 558 data->byte = inb_p(SMBHSTDAT0); 559 break; 560 case PIIX4_WORD_DATA: 561 data->word = inb_p(SMBHSTDAT0) + (inb_p(SMBHSTDAT1) << 8); 562 break; 563 case PIIX4_BLOCK_DATA: 564 data->block[0] = inb_p(SMBHSTDAT0); 565 if (data->block[0] == 0 || data->block[0] > I2C_SMBUS_BLOCK_MAX) 566 return -EPROTO; 567 inb_p(SMBHSTCNT); /* Reset SMBBLKDAT */ 568 for (i = 1; i <= data->block[0]; i++) 569 data->block[i] = inb_p(SMBBLKDAT); 570 break; 571 } 572 return 0; 573 } 574 575 /* 576 * Handles access to multiple SMBus ports on the SB800. 577 * The port is selected by bits 2:1 of the smb_en register (0x2c). 578 * Returns negative errno on error. 579 * 580 * Note: The selected port must be returned to the initial selection to avoid 581 * problems on certain systems. 582 */ 583 static s32 piix4_access_sb800(struct i2c_adapter *adap, u16 addr, 584 unsigned short flags, char read_write, 585 u8 command, int size, union i2c_smbus_data *data) 586 { 587 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 588 unsigned short piix4_smba = adapdata->smba; 589 int retries = MAX_TIMEOUT; 590 int smbslvcnt; 591 u8 smba_en_lo; 592 u8 port; 593 int retval; 594 595 mutex_lock(&piix4_mutex_sb800); 596 597 /* Request the SMBUS semaphore, avoid conflicts with the IMC */ 598 smbslvcnt = inb_p(SMBSLVCNT); 599 do { 600 outb_p(smbslvcnt | 0x10, SMBSLVCNT); 601 602 /* Check the semaphore status */ 603 smbslvcnt = inb_p(SMBSLVCNT); 604 if (smbslvcnt & 0x10) 605 break; 606 607 usleep_range(1000, 2000); 608 } while (--retries); 609 /* SMBus is still owned by the IMC, we give up */ 610 if (!retries) { 611 mutex_unlock(&piix4_mutex_sb800); 612 return -EBUSY; 613 } 614 615 outb_p(piix4_port_sel_sb800, SB800_PIIX4_SMB_IDX); 616 smba_en_lo = inb_p(SB800_PIIX4_SMB_IDX + 1); 617 618 port = adapdata->port; 619 if ((smba_en_lo & SB800_PIIX4_PORT_IDX_MASK) != port) 620 outb_p((smba_en_lo & ~SB800_PIIX4_PORT_IDX_MASK) | port, 621 SB800_PIIX4_SMB_IDX + 1); 622 623 retval = piix4_access(adap, addr, flags, read_write, 624 command, size, data); 625 626 outb_p(smba_en_lo, SB800_PIIX4_SMB_IDX + 1); 627 628 /* Release the semaphore */ 629 outb_p(smbslvcnt | 0x20, SMBSLVCNT); 630 631 mutex_unlock(&piix4_mutex_sb800); 632 633 return retval; 634 } 635 636 static u32 piix4_func(struct i2c_adapter *adapter) 637 { 638 return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE | 639 I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA | 640 I2C_FUNC_SMBUS_BLOCK_DATA; 641 } 642 643 static const struct i2c_algorithm smbus_algorithm = { 644 .smbus_xfer = piix4_access, 645 .functionality = piix4_func, 646 }; 647 648 static const struct i2c_algorithm piix4_smbus_algorithm_sb800 = { 649 .smbus_xfer = piix4_access_sb800, 650 .functionality = piix4_func, 651 }; 652 653 static const struct pci_device_id piix4_ids[] = { 654 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371AB_3) }, 655 { PCI_DEVICE(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443MX_3) }, 656 { PCI_DEVICE(PCI_VENDOR_ID_EFAR, PCI_DEVICE_ID_EFAR_SLC90E66_3) }, 657 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP200_SMBUS) }, 658 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP300_SMBUS) }, 659 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_IXP400_SMBUS) }, 660 { PCI_DEVICE(PCI_VENDOR_ID_ATI, PCI_DEVICE_ID_ATI_SBX00_SMBUS) }, 661 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) }, 662 { PCI_DEVICE(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_KERNCZ_SMBUS) }, 663 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 664 PCI_DEVICE_ID_SERVERWORKS_OSB4) }, 665 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 666 PCI_DEVICE_ID_SERVERWORKS_CSB5) }, 667 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 668 PCI_DEVICE_ID_SERVERWORKS_CSB6) }, 669 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 670 PCI_DEVICE_ID_SERVERWORKS_HT1000SB) }, 671 { PCI_DEVICE(PCI_VENDOR_ID_SERVERWORKS, 672 PCI_DEVICE_ID_SERVERWORKS_HT1100LD) }, 673 { 0, } 674 }; 675 676 MODULE_DEVICE_TABLE (pci, piix4_ids); 677 678 static struct i2c_adapter *piix4_main_adapters[PIIX4_MAX_ADAPTERS]; 679 static struct i2c_adapter *piix4_aux_adapter; 680 681 static int piix4_add_adapter(struct pci_dev *dev, unsigned short smba, 682 bool sb800_main, u8 port, 683 const char *name, struct i2c_adapter **padap) 684 { 685 struct i2c_adapter *adap; 686 struct i2c_piix4_adapdata *adapdata; 687 int retval; 688 689 adap = kzalloc(sizeof(*adap), GFP_KERNEL); 690 if (adap == NULL) { 691 release_region(smba, SMBIOSIZE); 692 return -ENOMEM; 693 } 694 695 adap->owner = THIS_MODULE; 696 adap->class = I2C_CLASS_HWMON | I2C_CLASS_SPD; 697 adap->algo = sb800_main ? &piix4_smbus_algorithm_sb800 698 : &smbus_algorithm; 699 700 adapdata = kzalloc(sizeof(*adapdata), GFP_KERNEL); 701 if (adapdata == NULL) { 702 kfree(adap); 703 release_region(smba, SMBIOSIZE); 704 return -ENOMEM; 705 } 706 707 adapdata->smba = smba; 708 adapdata->sb800_main = sb800_main; 709 adapdata->port = port << 1; 710 711 /* set up the sysfs linkage to our parent device */ 712 adap->dev.parent = &dev->dev; 713 714 snprintf(adap->name, sizeof(adap->name), 715 "SMBus PIIX4 adapter%s at %04x", name, smba); 716 717 i2c_set_adapdata(adap, adapdata); 718 719 retval = i2c_add_adapter(adap); 720 if (retval) { 721 kfree(adapdata); 722 kfree(adap); 723 release_region(smba, SMBIOSIZE); 724 return retval; 725 } 726 727 *padap = adap; 728 return 0; 729 } 730 731 static int piix4_add_adapters_sb800(struct pci_dev *dev, unsigned short smba) 732 { 733 struct i2c_piix4_adapdata *adapdata; 734 int port; 735 int retval; 736 737 for (port = 0; port < PIIX4_MAX_ADAPTERS; port++) { 738 retval = piix4_add_adapter(dev, smba, true, port, 739 piix4_main_port_names_sb800[port], 740 &piix4_main_adapters[port]); 741 if (retval < 0) 742 goto error; 743 } 744 745 return retval; 746 747 error: 748 dev_err(&dev->dev, 749 "Error setting up SB800 adapters. Unregistering!\n"); 750 while (--port >= 0) { 751 adapdata = i2c_get_adapdata(piix4_main_adapters[port]); 752 if (adapdata->smba) { 753 i2c_del_adapter(piix4_main_adapters[port]); 754 kfree(adapdata); 755 kfree(piix4_main_adapters[port]); 756 piix4_main_adapters[port] = NULL; 757 } 758 } 759 760 return retval; 761 } 762 763 static int piix4_probe(struct pci_dev *dev, const struct pci_device_id *id) 764 { 765 int retval; 766 bool is_sb800 = false; 767 768 if ((dev->vendor == PCI_VENDOR_ID_ATI && 769 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS && 770 dev->revision >= 0x40) || 771 dev->vendor == PCI_VENDOR_ID_AMD) { 772 is_sb800 = true; 773 774 if (!request_region(SB800_PIIX4_SMB_IDX, 2, "smba_idx")) { 775 dev_err(&dev->dev, 776 "SMBus base address index region 0x%x already in use!\n", 777 SB800_PIIX4_SMB_IDX); 778 return -EBUSY; 779 } 780 781 /* base address location etc changed in SB800 */ 782 retval = piix4_setup_sb800(dev, id, 0); 783 if (retval < 0) { 784 release_region(SB800_PIIX4_SMB_IDX, 2); 785 return retval; 786 } 787 788 /* 789 * Try to register multiplexed main SMBus adapter, 790 * give up if we can't 791 */ 792 retval = piix4_add_adapters_sb800(dev, retval); 793 if (retval < 0) { 794 release_region(SB800_PIIX4_SMB_IDX, 2); 795 return retval; 796 } 797 } else { 798 retval = piix4_setup(dev, id); 799 if (retval < 0) 800 return retval; 801 802 /* Try to register main SMBus adapter, give up if we can't */ 803 retval = piix4_add_adapter(dev, retval, false, 0, "", 804 &piix4_main_adapters[0]); 805 if (retval < 0) 806 return retval; 807 } 808 809 /* Check for auxiliary SMBus on some AMD chipsets */ 810 retval = -ENODEV; 811 812 if (dev->vendor == PCI_VENDOR_ID_ATI && 813 dev->device == PCI_DEVICE_ID_ATI_SBX00_SMBUS) { 814 if (dev->revision < 0x40) { 815 retval = piix4_setup_aux(dev, id, 0x58); 816 } else { 817 /* SB800 added aux bus too */ 818 retval = piix4_setup_sb800(dev, id, 1); 819 } 820 } 821 822 if (dev->vendor == PCI_VENDOR_ID_AMD && 823 dev->device == PCI_DEVICE_ID_AMD_HUDSON2_SMBUS) { 824 retval = piix4_setup_sb800(dev, id, 1); 825 } 826 827 if (retval > 0) { 828 /* Try to add the aux adapter if it exists, 829 * piix4_add_adapter will clean up if this fails */ 830 piix4_add_adapter(dev, retval, false, 0, 831 is_sb800 ? piix4_aux_port_name_sb800 : "", 832 &piix4_aux_adapter); 833 } 834 835 return 0; 836 } 837 838 static void piix4_adap_remove(struct i2c_adapter *adap) 839 { 840 struct i2c_piix4_adapdata *adapdata = i2c_get_adapdata(adap); 841 842 if (adapdata->smba) { 843 i2c_del_adapter(adap); 844 if (adapdata->port == (0 << 1)) { 845 release_region(adapdata->smba, SMBIOSIZE); 846 if (adapdata->sb800_main) 847 release_region(SB800_PIIX4_SMB_IDX, 2); 848 } 849 kfree(adapdata); 850 kfree(adap); 851 } 852 } 853 854 static void piix4_remove(struct pci_dev *dev) 855 { 856 int port = PIIX4_MAX_ADAPTERS; 857 858 while (--port >= 0) { 859 if (piix4_main_adapters[port]) { 860 piix4_adap_remove(piix4_main_adapters[port]); 861 piix4_main_adapters[port] = NULL; 862 } 863 } 864 865 if (piix4_aux_adapter) { 866 piix4_adap_remove(piix4_aux_adapter); 867 piix4_aux_adapter = NULL; 868 } 869 } 870 871 static struct pci_driver piix4_driver = { 872 .name = "piix4_smbus", 873 .id_table = piix4_ids, 874 .probe = piix4_probe, 875 .remove = piix4_remove, 876 }; 877 878 module_pci_driver(piix4_driver); 879 880 MODULE_AUTHOR("Frodo Looijaard <frodol@dds.nl> and " 881 "Philip Edelbrock <phil@netroedge.com>"); 882 MODULE_DESCRIPTION("PIIX4 SMBus driver"); 883 MODULE_LICENSE("GPL"); 884