1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for MPS MPQ8646 step-down converter. 4 * 5 * Copyright (c) 2026 Free Mobile - Vincent Jardin <vjardin@free.fr> 6 */ 7 8 #include <linux/bitops.h> 9 #include <linux/debugfs.h> 10 #include <linux/delay.h> 11 #include <linux/i2c.h> 12 #include <linux/module.h> 13 #include <linux/mutex.h> 14 #include <linux/nvmem-provider.h> 15 #include <linux/of_device.h> 16 #include <linux/pmbus.h> 17 #include <linux/property.h> 18 #include <linux/regulator/driver.h> 19 #include <linux/seq_file.h> 20 #include <linux/workqueue.h> 21 #include "pmbus.h" 22 23 /* Default cadence for the in-driver alarm-poll fallback (ms) */ 24 #define MPQ8646_ALARM_POLL_MS_DEFAULT 1000 25 26 /* MPS vendor-extended command codes (NOT in PMBus 1.3 Part II) */ 27 #define MPS_CLEAR_LAST_FAULT 0x08 28 #define MPS_MFR_CFG_EXT 0xF5 29 #define MPS_MFR_CFG_EXT_CLR_LAST_EN BIT(6) 30 #define MPS_PROTECTION_LAST 0xFB 31 32 /* 33 * PMBus 1.3 NVM commit / revert commands. MPS equivalent of 34 * STORE_ALL (15h) and RESTORE_ALL (16h). 35 */ 36 #define PMBUS_STORE_USER_ALL 0x15 37 #define PMBUS_RESTORE_USER_ALL 0x16 38 39 /* PMBus 1.3 timing / UVLO command codes */ 40 #define PMBUS_VIN_ON 0x35 41 #define PMBUS_VIN_OFF 0x36 42 #define PMBUS_TON_DELAY 0x60 43 #define PMBUS_TON_RISE 0x61 44 #define PMBUS_TOFF_DELAY 0x64 45 #define PMBUS_TOFF_FALL 0x65 46 47 /* MPS vendor-extended observability / identity registers */ 48 #define MPS_MFR_CONFIG_ID 0xC0 49 #define MPS_MFR_CONFIG_CODE_REV 0xC1 50 #define MPS_MFR_PRODUCT_REV_USER 0xC2 51 #define MPS_MFR_SILICON_REV 0xC3 52 #define MPS_MFR_RETRY_TIMES 0xF4 53 #define MPS_MFR_VBOOT_CFG 0xFC 54 55 /* 56 * MPS_MFR_PMBUS_LOCK (EEh): 16-bit WORD whose low two bits gate 57 * subsequent PMBus writes 58 * bits[1:0] = 00 -- unlocked (POR default) 59 * 01 -- lock all writes EXCEPT VOUT_COMMAND (0x21) 60 * so the operator can still DVFS the rail 61 * 11 -- lock all writes 62 * A negative-going PG edge resets these bits to 00, the lock 63 * is operationally reversible without a full chip POR. 64 */ 65 #define MPS_MFR_PMBUS_LOCK 0xEE 66 67 /* 68 * Retry parameters for the MFR_CFG_EXT gate-close write after 69 * CLEAR_LAST_FAULT. Bench-observed NVM-busy NACK window on this 70 * silicon is about 1 ms; the datasheet does not have information. 71 */ 72 #define MPQ8646_NVM_RETRY_MAX 5 73 #define MPQ8646_NVM_RETRY_DELAY_US_MIN 2000 74 #define MPQ8646_NVM_RETRY_DELAY_US_MAX 4000 75 76 #define MPQ8646_DEBUG(client, fmt, ...) \ 77 dev_dbg(&(client)->dev, fmt, ##__VA_ARGS__) 78 79 /* 80 * Maximum legal value for VOUT_SCALE_LOOP (0x29) on the MPQ8646 silicon 81 * The chip uses an 11-bit VOUT feedback-divider scale register. 82 */ 83 #define MPQ8646_VOUT_SCALE_LOOP_MAX GENMASK(10, 0) 84 85 /* Forward declaration */ 86 struct mpq8646_dbg_reg_ctx; 87 88 /* Per-instance state */ 89 struct mpq8646_priv { 90 struct pmbus_driver_info info; /* must be first, container_of target */ 91 struct i2c_client *client; 92 93 /* Serialises CLEAR_LAST_FAULT sequences and PROTECTION_LAST reads */ 94 struct mutex mps_lock; 95 96 /* Set alarm_poll_interval_ms = 0 to disable. */ 97 struct delayed_work alarm_poll_work; 98 u32 alarm_poll_interval_ms; 99 100 #ifdef CONFIG_DEBUG_FS 101 /* the only debugfs file that can re-arm the poll worker */ 102 struct dentry *dbg_poll; 103 struct mpq8646_dbg_reg_ctx *dbg_reg_ctx; 104 #endif 105 }; 106 107 static inline struct mpq8646_priv *mpq8646_priv_from_client(struct i2c_client *client) 108 { 109 const struct pmbus_driver_info *info = pmbus_get_driver_info(client); 110 111 return container_of(info, struct mpq8646_priv, info); 112 } 113 114 /* 115 * VID-mode m/b/R coefficients, same values as the mpq8785 driver for 116 * the MPS VID encoding. Per the PMBus Direct formula used by 117 * pmbus_core, X = (Y * 10^-R - b) / m, so m=64 / b=0 / R=1 yields 118 * 1.5625 mV per LSB. 119 */ 120 #define MPQ8646_VID_M 64 121 #define MPQ8646_VID_B 0 122 #define MPQ8646_VID_R 1 123 124 static int mpq8646_identify(struct i2c_client *client, 125 struct pmbus_driver_info *info) 126 { 127 int vout_mode; 128 129 vout_mode = pmbus_read_byte_data(client, 0, PMBUS_VOUT_MODE); 130 if (vout_mode < 0) 131 return vout_mode; 132 133 switch (vout_mode & PB_VOUT_MODE_MODE_MASK) { 134 case PB_VOUT_MODE_LINEAR: 135 info->format[PSC_VOLTAGE_OUT] = linear; 136 break; 137 case PB_VOUT_MODE_VID: 138 case PB_VOUT_MODE_DIRECT: 139 info->format[PSC_VOLTAGE_OUT] = direct; 140 info->m[PSC_VOLTAGE_OUT] = MPQ8646_VID_M; 141 info->b[PSC_VOLTAGE_OUT] = MPQ8646_VID_B; 142 info->R[PSC_VOLTAGE_OUT] = MPQ8646_VID_R; 143 break; 144 default: 145 return -ENODEV; 146 } 147 148 return 0; 149 }; 150 151 static int mpq8646_read_byte_data(struct i2c_client *client, int page, int reg) 152 { 153 int ret; 154 155 MPQ8646_DEBUG(client, "read_byte_data page=%d reg=0x%02x\n", page, reg); 156 157 switch (reg) { 158 case PMBUS_VOUT_MODE: 159 ret = pmbus_read_byte_data(client, page, reg); 160 MPQ8646_DEBUG(client, " VOUT_MODE raw=0x%02x ret=%d\n", ret, ret); 161 if (ret < 0) 162 return ret; 163 164 if ((ret & PB_VOUT_MODE_MODE_MASK) == PB_VOUT_MODE_VID) 165 return PB_VOUT_MODE_DIRECT; 166 167 return ret; 168 case PMBUS_STATUS_BYTE: 169 case PMBUS_STATUS_CML: 170 case PMBUS_STATUS_OTHER: 171 case PMBUS_STATUS_MFR_SPECIFIC: 172 case PMBUS_STATUS_FAN_12: 173 case PMBUS_STATUS_FAN_34: 174 return -ENXIO; 175 case PMBUS_MFR_LOCATION: 176 case PMBUS_MFR_DATE: 177 case PMBUS_MFR_SERIAL: 178 case PMBUS_IC_DEVICE_ID: 179 case PMBUS_IC_DEVICE_REV: 180 MPQ8646_DEBUG(client, " unsupported mfr-info reg 0x%02x -> ENXIO\n", reg); 181 return -ENXIO; 182 default: 183 return -ENODATA; 184 } 185 } 186 187 /* 188 * Reference: ltc2978.c::ltc2978_write_word_data which uses the 189 * same virtual-register channel for its real chip-side peak reset. 190 */ 191 static int mpq8646_write_word_data(struct i2c_client *client, int page, 192 int reg, u16 word) 193 { 194 struct mpq8646_priv *priv = mpq8646_priv_from_client(client); 195 int rc; 196 197 switch (reg) { 198 case PMBUS_VIRT_RESET_VIN_HISTORY: 199 case PMBUS_VIRT_RESET_VOUT_HISTORY: 200 case PMBUS_VIRT_RESET_IOUT_HISTORY: 201 case PMBUS_VIRT_RESET_TEMP_HISTORY: 202 MPQ8646_DEBUG(client, "reset_history virt reg=0x%04x -> CLEAR_FAULTS\n", 203 reg); 204 rc = i2c_smbus_write_byte(priv->client, PMBUS_CLEAR_FAULTS); 205 if (rc < 0) 206 MPQ8646_DEBUG(client, " CLEAR_FAULTS rc=%d\n", rc); 207 return rc < 0 ? rc : 0; 208 default: 209 return -ENODATA; /* let pmbus_core do the direct write */ 210 } 211 } 212 213 static int mpq8646_read_word_data(struct i2c_client *client, int page, 214 int phase, int reg) 215 { 216 int rc; 217 218 MPQ8646_DEBUG(client, "read_word_data page=%d phase=%d reg=0x%02x\n", 219 page, phase, reg); 220 221 switch (reg) { 222 case PMBUS_READ_VIN: 223 case PMBUS_READ_VOUT: 224 case PMBUS_READ_IOUT: 225 case PMBUS_READ_TEMPERATURE_1: 226 case PMBUS_STATUS_WORD: 227 case PMBUS_VOUT_OV_FAULT_LIMIT: 228 case PMBUS_VOUT_OV_WARN_LIMIT: 229 case PMBUS_VOUT_UV_WARN_LIMIT: 230 case PMBUS_VOUT_UV_FAULT_LIMIT: 231 case PMBUS_IOUT_OC_FAULT_LIMIT: 232 case PMBUS_IOUT_OC_WARN_LIMIT: 233 case PMBUS_OT_FAULT_LIMIT: 234 case PMBUS_OT_WARN_LIMIT: 235 case PMBUS_VIN_OV_FAULT_LIMIT: 236 case PMBUS_VIN_OV_WARN_LIMIT: 237 case PMBUS_VIN_UV_WARN_LIMIT: 238 case PMBUS_VIN_UV_FAULT_LIMIT: 239 case PMBUS_MFR_VIN_MAX: 240 case PMBUS_MFR_VOUT_MAX: 241 case PMBUS_MFR_IOUT_MAX: 242 case PMBUS_MFR_MAX_TEMP_1: 243 break; 244 case PMBUS_VIRT_RESET_VIN_HISTORY: 245 case PMBUS_VIRT_RESET_VOUT_HISTORY: 246 case PMBUS_VIRT_RESET_IOUT_HISTORY: 247 case PMBUS_VIRT_RESET_TEMP_HISTORY: 248 return 0; 249 default: 250 return -ENODATA; 251 } 252 253 rc = i2c_smbus_read_word_data(client, reg); 254 255 MPQ8646_DEBUG(client, " reg=0x%02x rc=%d\n", reg, rc); 256 return rc; 257 } 258 259 static struct pmbus_driver_info mpq8646_info = { 260 .pages = 1, 261 .format[PSC_VOLTAGE_IN] = direct, 262 .format[PSC_CURRENT_OUT] = direct, 263 .format[PSC_TEMPERATURE] = direct, 264 .m[PSC_VOLTAGE_IN] = 4, 265 .b[PSC_VOLTAGE_IN] = 0, 266 .R[PSC_VOLTAGE_IN] = 1, 267 .m[PSC_CURRENT_OUT] = 16, 268 .b[PSC_CURRENT_OUT] = 0, 269 .R[PSC_CURRENT_OUT] = 0, 270 .m[PSC_TEMPERATURE] = 1, 271 .b[PSC_TEMPERATURE] = 0, 272 .R[PSC_TEMPERATURE] = 0, 273 .func[0] = PMBUS_HAVE_VIN | PMBUS_HAVE_VOUT | 274 PMBUS_HAVE_IOUT | PMBUS_HAVE_TEMP | 275 PMBUS_HAVE_STATUS_INPUT | PMBUS_HAVE_STATUS_VOUT | 276 PMBUS_HAVE_STATUS_IOUT | PMBUS_HAVE_STATUS_TEMP, 277 }; 278 279 #if IS_ENABLED(CONFIG_REGULATOR) 280 static const struct regulator_desc mpq8646_reg_desc[] = { 281 PMBUS_REGULATOR("vout", 0), 282 }; 283 #endif /* CONFIG_REGULATOR */ 284 285 #if IS_ENABLED(CONFIG_NVMEM) 286 /* 287 * Expose using 288 * /sys/bus/nvmem/devices/<i2c-name>/nvmem 289 * 290 * Layout (16 bytes): 291 * offset 0..1 PROTECTION_LAST (0xFB) word, LE -- NVM 292 * offset 2..3 MFR_RETRY_TIMES (0xF4) word, LE -- NVM 293 * offset 4..5 MFR_CONFIG_ID (0xC0) word, LE -- NVM 294 * offset 6..7 MFR_VBOOT_CFG (0xFC) word, LE -- NVM 295 * offset 8 MFR_SILICON_REV (0xC3) byte -- NVM 296 * offset 9..15 reserved (zero-fill, leaves room for additions) 297 */ 298 #define MPQ8646_NVMEM_SIZE 16 299 300 struct mpq8646_nvmem_entry { 301 unsigned int off; 302 u8 reg; 303 bool is_word; 304 }; 305 306 static const struct mpq8646_nvmem_entry mpq8646_nvmem_map[] = { 307 { 0, MPS_PROTECTION_LAST, true }, 308 { 2, MPS_MFR_RETRY_TIMES, true }, 309 { 4, MPS_MFR_CONFIG_ID, true }, 310 { 6, MPS_MFR_VBOOT_CFG, true }, 311 { 8, MPS_MFR_SILICON_REV, false }, 312 }; 313 314 static int mpq8646_nvmem_read(void *data, unsigned int offset, void *val, 315 size_t bytes) 316 { 317 struct mpq8646_priv *priv = data; 318 u8 *out = val; 319 size_t i; 320 321 if (offset >= MPQ8646_NVMEM_SIZE) 322 return -EINVAL; 323 if (offset + bytes > MPQ8646_NVMEM_SIZE) 324 bytes = MPQ8646_NVMEM_SIZE - offset; 325 326 memset(out, 0, bytes); 327 328 guard(mutex)(&priv->mps_lock); 329 for (i = 0; i < ARRAY_SIZE(mpq8646_nvmem_map); i++) { 330 const struct mpq8646_nvmem_entry *e = &mpq8646_nvmem_map[i]; 331 unsigned int e_start = e->off; 332 unsigned int e_end = e_start + (e->is_word ? 2 : 1); 333 u8 raw[2]; 334 int rc; 335 unsigned int j; 336 337 if (e_end <= offset || e_start >= offset + bytes) 338 continue; /* outside requested slice */ 339 340 if (e->is_word) 341 rc = i2c_smbus_read_word_data(priv->client, e->reg); 342 else 343 rc = i2c_smbus_read_byte_data(priv->client, e->reg); 344 if (rc < 0) 345 continue; /* leave the zero-fill in place */ 346 347 raw[0] = rc & 0xff; 348 raw[1] = (rc >> 8) & 0xff; 349 350 for (j = 0; j < e_end - e_start; j++) { 351 unsigned int abs = e_start + j; 352 353 if (abs >= offset && abs < offset + bytes) 354 out[abs - offset] = raw[j]; 355 } 356 } 357 return 0; 358 } 359 #endif /* CONFIG_NVMEM */ 360 361 static const struct i2c_device_id mpq8646_id[] = { 362 { .name = "mpq8646" }, 363 { }, 364 }; 365 MODULE_DEVICE_TABLE(i2c, mpq8646_id); 366 367 static const struct of_device_id __maybe_unused mpq8646_of_match[] = { 368 { .compatible = "mps,mpq8646" }, 369 {} 370 }; 371 MODULE_DEVICE_TABLE(of, mpq8646_of_match); 372 373 static struct pmbus_platform_data mpq8646_no_pec_pdata = { 374 .flags = PMBUS_NO_CAPABILITY, 375 }; 376 377 #ifdef CONFIG_DEBUG_FS 378 /* 379 * Read-only decode cases in the client's pmbus debugfs directory: 380 * the MPS-specific STATUS_WORD and PROTECTION_LAST bit decode plus the 381 * identity/timing registers. 382 */ 383 384 struct mpq_status_bit { 385 u16 mask; 386 const char *name; 387 }; 388 389 static const struct mpq_status_bit mpq8646_status_word_bits[] = { 390 { PB_STATUS_VOUT, "VOUT" }, 391 { PB_STATUS_IOUT_POUT, "IOUT_POUT" }, 392 { PB_STATUS_INPUT, "INPUT" }, 393 { PB_STATUS_WORD_MFR, "NVM_SUMMARY" }, 394 { PB_STATUS_POWER_GOOD_N, "POWER_GOOD#" }, 395 { PB_STATUS_FANS, "FANS" }, 396 { PB_STATUS_OTHER, "OTHER" }, 397 { PB_STATUS_UNKNOWN, "WATCH_DOG" }, 398 { PB_STATUS_BUSY, "BUSY" }, 399 { PB_STATUS_OFF, "OFF" }, 400 { PB_STATUS_VOUT_OV, "VOUT_OV_FAULT" }, 401 { PB_STATUS_IOUT_OC, "IOUT_OC_FAULT" }, 402 { PB_STATUS_VIN_UV, "VIN_UV_FAULT" }, 403 { PB_STATUS_TEMPERATURE, "TEMP" }, 404 { PB_STATUS_CML, "CML" }, 405 { PB_STATUS_NONE_ABOVE, "DRMOS_FAULT" }, 406 { /* sentinel */ } 407 }; 408 409 /* PROTECTION_LAST (0xFB) bit names, it survives chip POR */ 410 static const struct mpq_status_bit mpq8646_protection_last_bits[] = { 411 { BIT(15), "INIT_FAULT" }, 412 { BIT(14), "NVM_CRC_ERROR" }, 413 { BIT(13), "NVM_FAULT" }, 414 { BIT(12), "OC_PHASE_FAULT" }, 415 { BIT(11), "OTP_SELF_FAULT" }, 416 { BIT(9), "SWITCH_PRD_FAULT" }, 417 { BIT(8), "VIN_OV_FAULT" }, 418 { BIT(7), "VOUT_OV_FAULT" }, 419 { BIT(6), "VOUT_UV_FAULT" }, 420 { BIT(5), "OC_TOT_FAULT" }, 421 { BIT(4), "VIN_UVLO_FAULT" }, 422 { BIT(3), "DRMOS_OTP" }, 423 { /* sentinel */ } 424 }; 425 426 static void mpq8646_print_bits(struct seq_file *s, u16 v, 427 const struct mpq_status_bit *tab) 428 { 429 const struct mpq_status_bit *t; 430 bool first = true; 431 432 seq_printf(s, "0x%04x", v); 433 if (!v) { 434 seq_puts(s, " [clean]\n"); 435 return; 436 } 437 seq_puts(s, " ["); 438 for (t = tab; t->mask; t++) { 439 if (v & t->mask) { 440 if (!first) 441 seq_putc(s, ' '); 442 seq_puts(s, t->name); 443 first = false; 444 } 445 } 446 seq_puts(s, "]\n"); 447 } 448 449 static int mpq8646_dbg_status_decoded_show(struct seq_file *s, void *unused) 450 { 451 struct mpq8646_priv *priv = s->private; 452 int rc; 453 454 scoped_guard(pmbus_lock, priv->client) 455 rc = i2c_smbus_read_word_data(priv->client, PMBUS_STATUS_WORD); 456 if (rc < 0) { 457 seq_printf(s, "ERROR: STATUS_WORD read failed (%d)\n", rc); 458 return 0; 459 } 460 seq_puts(s, "STATUS_WORD: "); 461 mpq8646_print_bits(s, (u16)rc, mpq8646_status_word_bits); 462 seq_puts(s, "(MPS extensions: bit12=NVM_SUMMARY, bit8=WATCH_DOG, bit0=DRMOS_FAULT)\n"); 463 return 0; 464 } 465 DEFINE_SHOW_ATTRIBUTE(mpq8646_dbg_status_decoded); 466 467 static int mpq8646_dbg_protection_last_show(struct seq_file *s, void *unused) 468 { 469 struct mpq8646_priv *priv = s->private; 470 int rc; 471 472 guard(pmbus_lock)(priv->client); 473 scoped_guard(mutex, &priv->mps_lock) 474 rc = i2c_smbus_read_word_data(priv->client, MPS_PROTECTION_LAST); 475 476 if (rc < 0) { 477 seq_printf(s, "ERROR: PROTECTION_LAST read failed (%d)\n", rc); 478 return 0; 479 } 480 seq_puts(s, "PROTECTION_LAST: "); 481 mpq8646_print_bits(s, (u16)rc, mpq8646_protection_last_bits); 482 seq_puts(s, "(NVM-backed, survives chip POR)\n"); 483 return 0; 484 } 485 DEFINE_SHOW_ATTRIBUTE(mpq8646_dbg_protection_last); 486 487 struct mpq8646_dbg_reg { 488 u8 reg; 489 bool is_word; 490 const char *name; 491 }; 492 493 static const struct mpq8646_dbg_reg mpq8646_dbg_regs[] = { 494 /* MPS vendor extensions (read-only identity / observability) */ 495 { MPS_MFR_CONFIG_ID, true, "mfr_config_id" }, 496 { MPS_MFR_CONFIG_CODE_REV, true, "mfr_config_code_rev" }, 497 { MPS_MFR_SILICON_REV, false, "mfr_silicon_rev" }, 498 { MPS_MFR_RETRY_TIMES, true, "mfr_retry_times" }, 499 { MPS_MFR_VBOOT_CFG, true, "mfr_vboot_cfg" }, 500 /* PMBus 1.3 standard timing / UVLO (read-only introspection) */ 501 { PMBUS_VIN_ON, true, "vin_on" }, 502 { PMBUS_VIN_OFF, true, "vin_off" }, 503 { PMBUS_TON_DELAY, true, "ton_delay" }, 504 { PMBUS_TON_RISE, true, "ton_rise" }, 505 { PMBUS_TOFF_DELAY, true, "toff_delay" }, 506 { PMBUS_TOFF_FALL, true, "toff_fall" }, 507 }; 508 509 struct mpq8646_dbg_reg_ctx { 510 struct mpq8646_priv *priv; 511 const struct mpq8646_dbg_reg *desc; 512 }; 513 514 static int mpq8646_dbg_reg_show(struct seq_file *s, void *unused) 515 { 516 struct mpq8646_dbg_reg_ctx *ctx = s->private; 517 int rc; 518 519 guard(pmbus_lock)(ctx->priv->client); 520 if (ctx->desc->is_word) 521 rc = i2c_smbus_read_word_data(ctx->priv->client, 522 ctx->desc->reg); 523 else 524 rc = i2c_smbus_read_byte_data(ctx->priv->client, 525 ctx->desc->reg); 526 527 if (rc < 0) { 528 seq_printf(s, "ERROR: reg 0x%02x (%s) read failed (%d)\n", 529 ctx->desc->reg, ctx->desc->name, rc); 530 return 0; 531 } 532 seq_printf(s, "0x%0*x\n", ctx->desc->is_word ? 4 : 2, rc); 533 return 0; 534 } 535 DEFINE_SHOW_ATTRIBUTE(mpq8646_dbg_reg); 536 537 #ifdef CONFIG_SENSORS_MPQ8646_DEBUG_UNSAFE 538 /* 539 * Write/provisioning data, disabled by default: NVM commit and 540 * revert, the CLEAR_LAST_FAULT sequences and a small set of named 541 * writable registers. 542 */ 543 544 static void mpq8646_unsafe_banner(struct mpq8646_priv *priv) 545 { 546 dev_warn(&priv->client->dev, 547 "**********************************************************\n" 548 "** WARNING WARNING WARNING WARNING WARNING WARNING **\n" 549 "** **\n" 550 "** The MPQ8646 provisioning debugfs writes are enabled. **\n" 551 "** Wrong register writes can and likely will physically **\n" 552 "** damage or destroy the chip and/or the board. **\n" 553 "** **\n" 554 "** If you see this message and you are not debugging **\n" 555 "** the kernel, report this immediately to your system **\n" 556 "** administrator! **\n" 557 "** **\n" 558 "** WARNING WARNING WARNING WARNING WARNING WARNING **\n" 559 "**********************************************************\n"); 560 } 561 562 static int mpq8646_dbg_clear_protection_last(void *data, u64 val) 563 { 564 struct mpq8646_priv *priv = data; 565 int rc; 566 567 if (!val) 568 return 0; 569 570 guard(pmbus_lock)(priv->client); 571 scoped_guard(mutex, &priv->mps_lock) 572 rc = i2c_smbus_write_byte(priv->client, MPS_CLEAR_LAST_FAULT); 573 if (rc < 0) 574 dev_warn(&priv->client->dev, 575 "clear_protection_last: CLEAR_LAST_FAULT write failed (%d)\n", 576 rc); 577 return rc; 578 } 579 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_clear_protection_last_fops, 580 NULL, mpq8646_dbg_clear_protection_last, "%llu\n"); 581 582 static int mpq8646_dbg_clear_protection_last_force(void *data, u64 val) 583 { 584 struct mpq8646_priv *priv = data; 585 int rc, ret; 586 int wp_orig, cfg_orig; 587 588 if (!val) 589 return 0; 590 591 guard(pmbus_lock)(priv->client); 592 guard(mutex)(&priv->mps_lock); 593 594 wp_orig = i2c_smbus_read_byte_data(priv->client, PMBUS_WRITE_PROTECT); 595 if (wp_orig < 0) { 596 dev_warn(&priv->client->dev, 597 "clear_protection_last_force: WRITE_PROTECT read failed (%d), aborting\n", 598 wp_orig); 599 return wp_orig; 600 } 601 cfg_orig = i2c_smbus_read_word_data(priv->client, MPS_MFR_CFG_EXT); 602 if (cfg_orig < 0) { 603 dev_warn(&priv->client->dev, 604 "clear_protection_last_force: MFR_CFG_EXT read failed (%d), aborting\n", 605 cfg_orig); 606 return cfg_orig; 607 } 608 609 if (wp_orig != 0) { 610 rc = i2c_smbus_write_byte_data(priv->client, 611 PMBUS_WRITE_PROTECT, 0); 612 if (rc < 0) { 613 dev_warn(&priv->client->dev, 614 "clear_protection_last_force: WP clear failed (%d), aborting\n", 615 rc); 616 return rc; 617 } 618 } 619 620 ret = i2c_smbus_write_word_data(priv->client, MPS_MFR_CFG_EXT, 621 (u16)cfg_orig | MPS_MFR_CFG_EXT_CLR_LAST_EN); 622 if (ret < 0) { 623 dev_warn(&priv->client->dev, 624 "clear_protection_last_force: gate open failed (%d)\n", 625 ret); 626 } else { 627 ret = i2c_smbus_write_byte(priv->client, MPS_CLEAR_LAST_FAULT); 628 if (ret < 0) 629 dev_warn(&priv->client->dev, 630 "clear_protection_last_force: CLEAR_LAST_FAULT failed (%d) even with gate open\n", 631 ret); 632 633 for (int attempt = 0; attempt < MPQ8646_NVM_RETRY_MAX; attempt++) { 634 rc = i2c_smbus_write_word_data(priv->client, 635 MPS_MFR_CFG_EXT, 636 (u16)cfg_orig); 637 if (rc >= 0) 638 break; 639 usleep_range(MPQ8646_NVM_RETRY_DELAY_US_MIN, 640 MPQ8646_NVM_RETRY_DELAY_US_MAX); 641 } 642 if (rc < 0) { 643 dev_warn(&priv->client->dev, 644 "clear_protection_last_force: MFR_CFG_EXT restore failed after retries (%d): gate may stay open until POR\n", 645 rc); 646 if (ret == 0) 647 ret = rc; 648 } 649 } 650 651 if (wp_orig != 0) { 652 rc = i2c_smbus_write_byte_data(priv->client, 653 PMBUS_WRITE_PROTECT, 654 (u8)wp_orig); 655 if (rc < 0) { 656 dev_warn(&priv->client->dev, 657 "clear_protection_last_force: WP restore failed (%d)\n", 658 rc); 659 if (ret == 0) 660 ret = rc; 661 } 662 } 663 return ret; 664 } 665 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_clear_protection_last_force_fops, 666 NULL, mpq8646_dbg_clear_protection_last_force, "%llu\n"); 667 668 static int mpq8646_dbg_store_all(void *data, u64 val) 669 { 670 struct mpq8646_priv *priv = data; 671 int rc; 672 673 if (!val) 674 return 0; 675 676 guard(pmbus_lock)(priv->client); 677 scoped_guard(mutex, &priv->mps_lock) 678 rc = i2c_smbus_write_byte(priv->client, PMBUS_STORE_USER_ALL); 679 if (rc < 0) 680 dev_warn(&priv->client->dev, 681 "store_all: STORE_USER_ALL (0x15) write failed (%d)\n", 682 rc); 683 return rc; 684 } 685 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_store_all_fops, 686 NULL, mpq8646_dbg_store_all, "%llu\n"); 687 688 static int mpq8646_dbg_restore_all(void *data, u64 val) 689 { 690 struct mpq8646_priv *priv = data; 691 int rc; 692 693 if (!val) 694 return 0; 695 696 guard(pmbus_lock)(priv->client); 697 scoped_guard(mutex, &priv->mps_lock) 698 rc = i2c_smbus_write_byte(priv->client, PMBUS_RESTORE_USER_ALL); 699 if (rc < 0) 700 dev_warn(&priv->client->dev, 701 "restore_all: RESTORE_USER_ALL (0x16) write failed (%d)\n", 702 rc); 703 return rc; 704 } 705 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_restore_all_fops, 706 NULL, mpq8646_dbg_restore_all, "%llu\n"); 707 708 static const struct mpq8646_dbg_reg mpq8646_dbg_regs_unsafe[] = { 709 /* PMBus 1.3 control / margin */ 710 { PMBUS_ON_OFF_CONFIG, false, "on_off_config" }, 711 { PMBUS_VOUT_MARGIN_HIGH, true, "vout_margin_high" }, 712 { PMBUS_VOUT_MARGIN_LOW, true, "vout_margin_low" }, 713 /* MPS PMBus-level write-protect */ 714 { MPS_MFR_PMBUS_LOCK, true, "mfr_pmbus_lock" }, 715 /* MPS user-writable product revision */ 716 { MPS_MFR_PRODUCT_REV_USER, true, "mfr_product_rev_user" }, 717 }; 718 719 static int mpq8646_dbg_reg_get(void *data, u64 *val) 720 { 721 struct mpq8646_dbg_reg_ctx *ctx = data; 722 int rc; 723 724 guard(pmbus_lock)(ctx->priv->client); 725 if (ctx->desc->is_word) 726 rc = i2c_smbus_read_word_data(ctx->priv->client, 727 ctx->desc->reg); 728 else 729 rc = i2c_smbus_read_byte_data(ctx->priv->client, 730 ctx->desc->reg); 731 if (rc < 0) 732 return rc; 733 *val = rc; 734 return 0; 735 } 736 737 static int mpq8646_dbg_reg_set(void *data, u64 val) 738 { 739 struct mpq8646_dbg_reg_ctx *ctx = data; 740 int rc; 741 742 guard(pmbus_lock)(ctx->priv->client); 743 if (ctx->desc->is_word) 744 rc = i2c_smbus_write_word_data(ctx->priv->client, 745 ctx->desc->reg, (u16)val); 746 else 747 rc = i2c_smbus_write_byte_data(ctx->priv->client, 748 ctx->desc->reg, (u8)val); 749 return rc < 0 ? rc : 0; 750 } 751 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_reg_rw_fops, 752 mpq8646_dbg_reg_get, mpq8646_dbg_reg_set, "0x%llx\n"); 753 754 static void mpq8646_debugfs_register_unsafe(struct mpq8646_priv *priv, 755 struct dentry *root) 756 { 757 struct mpq8646_dbg_reg_ctx *ctx; 758 size_t i; 759 760 mpq8646_unsafe_banner(priv); 761 762 debugfs_create_file_unsafe("clear_protection_last", 0200, root, priv, 763 &mpq8646_dbg_clear_protection_last_fops); 764 debugfs_create_file_unsafe("clear_protection_last_force", 0200, root, 765 priv, 766 &mpq8646_dbg_clear_protection_last_force_fops); 767 debugfs_create_file_unsafe("store_all", 0200, root, priv, 768 &mpq8646_dbg_store_all_fops); 769 debugfs_create_file_unsafe("restore_all", 0200, root, priv, 770 &mpq8646_dbg_restore_all_fops); 771 772 ctx = devm_kcalloc(&priv->client->dev, 773 ARRAY_SIZE(mpq8646_dbg_regs_unsafe), 774 sizeof(*ctx), GFP_KERNEL); 775 if (!ctx) 776 return; 777 for (i = 0; i < ARRAY_SIZE(mpq8646_dbg_regs_unsafe); i++) { 778 ctx[i].priv = priv; 779 ctx[i].desc = &mpq8646_dbg_regs_unsafe[i]; 780 debugfs_create_file_unsafe(mpq8646_dbg_regs_unsafe[i].name, 781 0600, root, &ctx[i], 782 &mpq8646_dbg_reg_rw_fops); 783 } 784 } 785 #else 786 static inline void mpq8646_debugfs_register_unsafe(struct mpq8646_priv *priv, 787 struct dentry *root) {} 788 #endif /* CONFIG_SENSORS_MPQ8646_DEBUG_UNSAFE */ 789 790 static int mpq8646_dbg_poll_interval_get(void *data, u64 *val) 791 { 792 struct mpq8646_priv *priv = data; 793 794 *val = priv->alarm_poll_interval_ms; 795 return 0; 796 } 797 798 static int mpq8646_dbg_poll_interval_set(void *data, u64 val) 799 { 800 struct mpq8646_priv *priv = data; 801 bool was_off = !priv->alarm_poll_interval_ms; 802 803 priv->alarm_poll_interval_ms = (u32)val; 804 805 if (val && was_off && !priv->client->irq) 806 schedule_delayed_work(&priv->alarm_poll_work, 807 msecs_to_jiffies((u32)val)); 808 return 0; 809 } 810 DEFINE_DEBUGFS_ATTRIBUTE(mpq8646_dbg_poll_interval_fops, 811 mpq8646_dbg_poll_interval_get, 812 mpq8646_dbg_poll_interval_set, "%llu\n"); 813 814 static void mpq8646_debugfs_register(struct mpq8646_priv *priv) 815 { 816 struct dentry *root; 817 size_t i; 818 819 root = pmbus_get_debugfs_dir(priv->client); 820 if (!root) 821 return; 822 823 /* MPS extensions: status decode + NVM-backed PROTECTION_LAST */ 824 debugfs_create_file("status_decoded", 0400, root, priv, 825 &mpq8646_dbg_status_decoded_fops); 826 debugfs_create_file("protection_last", 0400, root, priv, 827 &mpq8646_dbg_protection_last_fops); 828 priv->dbg_poll = 829 debugfs_create_file_unsafe("alarm_poll_interval_ms", 0600, 830 root, priv, 831 &mpq8646_dbg_poll_interval_fops); 832 833 priv->dbg_reg_ctx = devm_kcalloc(&priv->client->dev, 834 ARRAY_SIZE(mpq8646_dbg_regs), 835 sizeof(*priv->dbg_reg_ctx), 836 GFP_KERNEL); 837 if (!priv->dbg_reg_ctx) 838 return; 839 for (i = 0; i < ARRAY_SIZE(mpq8646_dbg_regs); i++) { 840 priv->dbg_reg_ctx[i].priv = priv; 841 priv->dbg_reg_ctx[i].desc = &mpq8646_dbg_regs[i]; 842 debugfs_create_file(mpq8646_dbg_regs[i].name, 0400, 843 root, &priv->dbg_reg_ctx[i], 844 &mpq8646_dbg_reg_fops); 845 } 846 847 mpq8646_debugfs_register_unsafe(priv, root); 848 } 849 850 static void mpq8646_debugfs_unregister(struct mpq8646_priv *priv) 851 { 852 debugfs_remove(priv->dbg_poll); 853 } 854 #else 855 static inline void mpq8646_debugfs_register(struct mpq8646_priv *priv) {} 856 static inline void mpq8646_debugfs_unregister(struct mpq8646_priv *priv) {} 857 #endif /* CONFIG_DEBUG_FS */ 858 859 static void mpq8646_alarm_poll_work(struct work_struct *work) 860 { 861 struct mpq8646_priv *priv = container_of(to_delayed_work(work), 862 struct mpq8646_priv, 863 alarm_poll_work); 864 865 if (priv->client->irq) 866 return; /* SMBALERT# wired; polling not needed */ 867 868 if (!priv->alarm_poll_interval_ms) 869 return; /* polling disabled; don't re-arm */ 870 871 pmbus_check_and_notify_faults(priv->client); 872 873 schedule_delayed_work(&priv->alarm_poll_work, 874 msecs_to_jiffies(priv->alarm_poll_interval_ms)); 875 } 876 877 static int mpq8646_probe(struct i2c_client *client) 878 { 879 struct device *dev = &client->dev; 880 struct pmbus_driver_info *info; 881 struct mpq8646_priv *priv; 882 u32 voltage_scale; 883 int ret; 884 885 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 886 if (!priv) 887 return -ENOMEM; 888 priv->client = client; 889 mutex_init(&priv->mps_lock); 890 memcpy(&priv->info, &mpq8646_info, sizeof(priv->info)); 891 info = &priv->info; 892 893 info->identify = mpq8646_identify; 894 info->read_byte_data = mpq8646_read_byte_data; 895 info->read_word_data = mpq8646_read_word_data; 896 info->write_word_data = mpq8646_write_word_data; 897 dev->platform_data = &mpq8646_no_pec_pdata; 898 899 #if IS_ENABLED(CONFIG_REGULATOR) 900 info->reg_desc = mpq8646_reg_desc; 901 info->num_regulators = ARRAY_SIZE(mpq8646_reg_desc); 902 #endif 903 904 INIT_DELAYED_WORK(&priv->alarm_poll_work, mpq8646_alarm_poll_work); 905 priv->alarm_poll_interval_ms = MPQ8646_ALARM_POLL_MS_DEFAULT; 906 907 if (!device_property_read_u32(dev, "mps,vout-fb-divider-ratio-permille", 908 &voltage_scale)) { 909 if (voltage_scale > MPQ8646_VOUT_SCALE_LOOP_MAX) 910 return -EINVAL; 911 912 ret = i2c_smbus_write_word_data(client, PMBUS_VOUT_SCALE_LOOP, 913 voltage_scale); 914 if (ret) 915 return ret; 916 } 917 918 ret = pmbus_do_probe(client, info); 919 if (ret) 920 return ret; 921 922 mpq8646_debugfs_register(priv); 923 924 if (!client->irq) 925 schedule_delayed_work(&priv->alarm_poll_work, 926 msecs_to_jiffies(priv->alarm_poll_interval_ms)); 927 928 #if IS_ENABLED(CONFIG_NVMEM) 929 { 930 struct nvmem_config cfg = { 931 .dev = &client->dev, 932 .name = dev_name(&client->dev), 933 .owner = THIS_MODULE, 934 .read_only = true, 935 .root_only = true, 936 .word_size = 1, 937 .stride = 1, 938 .size = MPQ8646_NVMEM_SIZE, 939 .reg_read = mpq8646_nvmem_read, 940 .priv = priv, 941 }; 942 struct nvmem_device *nv = devm_nvmem_register(&client->dev, &cfg); 943 944 if (IS_ERR(nv)) 945 dev_warn(&client->dev, 946 "nvmem snapshot register failed (%pe)\n", 947 nv); 948 } 949 #endif 950 return 0; 951 }; 952 953 static void mpq8646_remove(struct i2c_client *client) 954 { 955 struct mpq8646_priv *priv = mpq8646_priv_from_client(client); 956 957 mpq8646_debugfs_unregister(priv); 958 cancel_delayed_work_sync(&priv->alarm_poll_work); 959 } 960 961 static struct i2c_driver mpq8646_driver = { 962 .driver = { 963 .name = "mpq8646", 964 .of_match_table = of_match_ptr(mpq8646_of_match), 965 }, 966 .probe = mpq8646_probe, 967 .remove = mpq8646_remove, 968 .id_table = mpq8646_id, 969 }; 970 971 module_i2c_driver(mpq8646_driver); 972 973 MODULE_AUTHOR("Vincent Jardin <vjardin@free.fr>"); 974 MODULE_DESCRIPTION("PMBus driver for MPS MPQ8646 (extended observability)"); 975 MODULE_LICENSE("GPL"); 976 MODULE_IMPORT_NS("PMBUS"); 977