1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * HWMON driver for MCP998X/33 and MCP998XD/33D Multichannel Automotive 4 * Temperature Monitor Family 5 * 6 * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries 7 * 8 * Author: Victor Duicu <victor.duicu@microchip.com> 9 * 10 * Datasheet can be found here: 11 * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP998X-Family-Data-Sheet-DS20006827.pdf 12 */ 13 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bitops.h> 17 #include <linux/bits.h> 18 #include <linux/byteorder/generic.h> 19 #include <linux/delay.h> 20 #include <linux/device/devres.h> 21 #include <linux/device.h> 22 #include <linux/dev_printk.h> 23 #include <linux/err.h> 24 #include <linux/hwmon.h> 25 #include <linux/i2c.h> 26 #include <linux/math.h> 27 #include <linux/minmax.h> 28 #include <linux/property.h> 29 #include <linux/regmap.h> 30 #include <linux/time64.h> 31 #include <linux/util_macros.h> 32 33 /* MCP9982 Registers */ 34 #define MCP9982_HIGH_BYTE_ADDR(index) (2 * (index)) 35 #define MCP9982_ONE_SHOT_ADDR 0x0A 36 #define MCP9982_INTERNAL_HIGH_LIMIT_ADDR 0x0B 37 #define MCP9982_INTERNAL_LOW_LIMIT_ADDR 0x0C 38 #define MCP9982_EXT_HIGH_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0D) 39 #define MCP9982_EXT_LOW_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0F) 40 #define MCP9982_THERM_LIMIT_ADDR(index) ((index) + 0x1D) 41 #define MCP9982_CFG_ADDR 0x22 42 #define MCP9982_CONV_ADDR 0x24 43 #define MCP9982_HYS_ADDR 0x25 44 #define MCP9982_CONSEC_ALRT_ADDR 0x26 45 #define MCP9982_ALRT_CFG_ADDR 0x27 46 #define MCP9982_RUNNING_AVG_ADDR 0x28 47 #define MCP9982_HOTTEST_CFG_ADDR 0x29 48 #define MCP9982_STATUS_ADDR 0x2A 49 #define MCP9982_EXT_FAULT_STATUS_ADDR 0x2B 50 #define MCP9982_HIGH_LIMIT_STATUS_ADDR 0x2C 51 #define MCP9982_LOW_LIMIT_STATUS_ADDR 0x2D 52 #define MCP9982_THERM_LIMIT_STATUS_ADDR 0x2E 53 #define MCP9982_HOTTEST_HIGH_BYTE_ADDR 0x2F 54 #define MCP9982_HOTTEST_LOW_BYTE_ADDR 0x30 55 #define MCP9982_HOTTEST_STATUS_ADDR 0x31 56 #define MCP9982_THERM_SHTDWN_CFG_ADDR 0x32 57 #define MCP9982_HRDW_THERM_SHTDWN_LIMIT_ADDR 0x33 58 #define MCP9982_EXT_BETA_CFG_ADDR(index) ((index) + 0x33) 59 #define MCP9982_EXT_IDEAL_ADDR(index) ((index) + 0x35) 60 61 /* MCP9982 Bits */ 62 #define MCP9982_CFG_MSKAL BIT(7) 63 #define MCP9982_CFG_RS BIT(6) 64 #define MCP9982_CFG_ATTHM BIT(5) 65 #define MCP9982_CFG_RECD12 BIT(4) 66 #define MCP9982_CFG_RECD34 BIT(3) 67 #define MCP9982_CFG_RANGE BIT(2) 68 #define MCP9982_CFG_DA_ENA BIT(1) 69 #define MCP9982_CFG_APDD BIT(0) 70 71 #define MCP9982_STATUS_BUSY BIT(5) 72 73 /* Constants and default values */ 74 #define MCP9982_MAX_NUM_CHANNELS 5 75 #define MCP9982_BETA_AUTODETECT 16 76 #define MCP9982_IDEALITY_DEFAULT 18 77 #define MCP9982_OFFSET 64 78 #define MCP9982_DEFAULT_CONSEC_ALRT_VAL 112 79 #define MCP9982_DEFAULT_HYS_VAL 10 80 #define MCP9982_DEFAULT_CONV_VAL 6 81 #define MCP9982_WAKE_UP_TIME_US 125000 82 #define MCP9982_WAKE_UP_TIME_MAX_US 130000 83 #define MCP9982_HIGH_LIMIT_DEFAULT 85000 84 #define MCP9982_LOW_LIMIT_DEFAULT 0 85 86 static const struct hwmon_channel_info * const mcp9985_info[] = { 87 HWMON_CHANNEL_INFO(temp, 88 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 89 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 90 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 91 HWMON_T_CRIT_HYST, 92 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 93 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 94 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 95 HWMON_T_CRIT_HYST | HWMON_T_FAULT, 96 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 97 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 98 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 99 HWMON_T_CRIT_HYST | HWMON_T_FAULT, 100 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 101 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 102 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 103 HWMON_T_CRIT_HYST | HWMON_T_FAULT, 104 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 105 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 106 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 107 HWMON_T_CRIT_HYST | HWMON_T_FAULT), 108 HWMON_CHANNEL_INFO(chip, 109 HWMON_C_UPDATE_INTERVAL), 110 NULL 111 }; 112 113 /** 114 * struct mcp9982_features - features of a mcp9982 instance 115 * @name: chip's name 116 * @phys_channels: number of physical channels supported by the chip 117 * @hw_thermal_shutdown: presence of hardware thermal shutdown circuitry 118 * @allow_apdd: whether the chip supports enabling APDD 119 * @has_recd34: whether the chip has the channels that are affected by recd34 120 */ 121 struct mcp9982_features { 122 const char *name; 123 u8 phys_channels; 124 bool hw_thermal_shutdown; 125 bool allow_apdd; 126 bool has_recd34; 127 }; 128 129 static const struct mcp9982_features mcp9933_chip_config = { 130 .name = "mcp9933", 131 .phys_channels = 3, 132 .hw_thermal_shutdown = false, 133 .allow_apdd = true, 134 .has_recd34 = false, 135 }; 136 137 static const struct mcp9982_features mcp9933d_chip_config = { 138 .name = "mcp9933d", 139 .phys_channels = 3, 140 .hw_thermal_shutdown = true, 141 .allow_apdd = true, 142 .has_recd34 = false, 143 }; 144 145 static const struct mcp9982_features mcp9982_chip_config = { 146 .name = "mcp9982", 147 .phys_channels = 2, 148 .hw_thermal_shutdown = false, 149 .allow_apdd = false, 150 .has_recd34 = false, 151 }; 152 153 static const struct mcp9982_features mcp9982d_chip_config = { 154 .name = "mcp9982d", 155 .phys_channels = 2, 156 .hw_thermal_shutdown = true, 157 .allow_apdd = false, 158 .has_recd34 = false, 159 }; 160 161 static const struct mcp9982_features mcp9983_chip_config = { 162 .name = "mcp9983", 163 .phys_channels = 3, 164 .hw_thermal_shutdown = false, 165 .allow_apdd = false, 166 .has_recd34 = true, 167 }; 168 169 static const struct mcp9982_features mcp9983d_chip_config = { 170 .name = "mcp9983d", 171 .phys_channels = 3, 172 .hw_thermal_shutdown = true, 173 .allow_apdd = false, 174 .has_recd34 = true, 175 }; 176 177 static const struct mcp9982_features mcp9984_chip_config = { 178 .name = "mcp9984", 179 .phys_channels = 4, 180 .hw_thermal_shutdown = false, 181 .allow_apdd = true, 182 .has_recd34 = true, 183 }; 184 185 static const struct mcp9982_features mcp9984d_chip_config = { 186 .name = "mcp9984d", 187 .phys_channels = 4, 188 .hw_thermal_shutdown = true, 189 .allow_apdd = true, 190 .has_recd34 = true, 191 }; 192 193 static const struct mcp9982_features mcp9985_chip_config = { 194 .name = "mcp9985", 195 .phys_channels = 5, 196 .hw_thermal_shutdown = false, 197 .allow_apdd = true, 198 .has_recd34 = true, 199 }; 200 201 static const struct mcp9982_features mcp9985d_chip_config = { 202 .name = "mcp9985d", 203 .phys_channels = 5, 204 .hw_thermal_shutdown = true, 205 .allow_apdd = true, 206 .has_recd34 = true, 207 }; 208 209 static const unsigned int mcp9982_update_interval[11] = { 210 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 64, 32, 16 211 }; 212 213 /* MCP9982 regmap configuration */ 214 static const struct regmap_range mcp9982_regmap_wr_ranges[] = { 215 regmap_reg_range(MCP9982_ONE_SHOT_ADDR, MCP9982_CFG_ADDR), 216 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_HOTTEST_CFG_ADDR), 217 regmap_reg_range(MCP9982_THERM_SHTDWN_CFG_ADDR, MCP9982_THERM_SHTDWN_CFG_ADDR), 218 regmap_reg_range(MCP9982_EXT_BETA_CFG_ADDR(1), MCP9982_EXT_IDEAL_ADDR(4)), 219 }; 220 221 static const struct regmap_access_table mcp9982_regmap_wr_table = { 222 .yes_ranges = mcp9982_regmap_wr_ranges, 223 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_wr_ranges), 224 }; 225 226 static const struct regmap_range mcp9982_regmap_rd_ranges[] = { 227 regmap_reg_range(MCP9982_HIGH_BYTE_ADDR(0), MCP9982_CFG_ADDR), 228 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_EXT_IDEAL_ADDR(4)), 229 }; 230 231 static const struct regmap_access_table mcp9982_regmap_rd_table = { 232 .yes_ranges = mcp9982_regmap_rd_ranges, 233 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_rd_ranges), 234 }; 235 236 static bool mcp9982_is_volatile_reg(struct device *dev, unsigned int reg) 237 { 238 switch (reg) { 239 case MCP9982_ONE_SHOT_ADDR: 240 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 241 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 242 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 243 case MCP9982_EXT_LOW_LIMIT_ADDR(1) + 1: 244 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 245 case MCP9982_EXT_LOW_LIMIT_ADDR(2) + 1: 246 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 247 case MCP9982_EXT_LOW_LIMIT_ADDR(3) + 1: 248 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 249 case MCP9982_EXT_LOW_LIMIT_ADDR(4) + 1: 250 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 251 case MCP9982_EXT_HIGH_LIMIT_ADDR(1) + 1: 252 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 253 case MCP9982_EXT_HIGH_LIMIT_ADDR(2) + 1: 254 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 255 case MCP9982_EXT_HIGH_LIMIT_ADDR(3) + 1: 256 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 257 case MCP9982_EXT_HIGH_LIMIT_ADDR(4) + 1: 258 case MCP9982_THERM_LIMIT_ADDR(0): 259 case MCP9982_THERM_LIMIT_ADDR(1): 260 case MCP9982_THERM_LIMIT_ADDR(2): 261 case MCP9982_THERM_LIMIT_ADDR(3): 262 case MCP9982_THERM_LIMIT_ADDR(4): 263 case MCP9982_CFG_ADDR: 264 case MCP9982_CONV_ADDR: 265 case MCP9982_HYS_ADDR: 266 case MCP9982_CONSEC_ALRT_ADDR: 267 case MCP9982_ALRT_CFG_ADDR: 268 case MCP9982_RUNNING_AVG_ADDR: 269 case MCP9982_HOTTEST_CFG_ADDR: 270 case MCP9982_THERM_SHTDWN_CFG_ADDR: 271 return false; 272 default: 273 return true; 274 } 275 } 276 277 static const struct regmap_config mcp9982_regmap_config = { 278 .reg_bits = 8, 279 .val_bits = 8, 280 .rd_table = &mcp9982_regmap_rd_table, 281 .wr_table = &mcp9982_regmap_wr_table, 282 .volatile_reg = mcp9982_is_volatile_reg, 283 .max_register = MCP9982_EXT_IDEAL_ADDR(4), 284 .cache_type = REGCACHE_MAPLE, 285 }; 286 287 /** 288 * struct mcp9982_priv - information about chip parameters 289 * @regmap: device register map 290 * @chip: pointer to structure holding chip features 291 * @labels: labels of the channels 292 * @interval_idx: index representing the current update interval 293 * @enabled_channel_mask: mask containing which channels should be enabled 294 * @num_channels: number of active physical channels 295 * @recd34_enable: state of Resistance Error Correction(REC) on channels 3 and 4 296 * @recd12_enable: state of Resistance Error Correction(REC) on channels 1 and 2 297 * @apdd_enable: state of anti-parallel diode mode 298 * @run_state: chip is in Run state, otherwise is in Standby state 299 */ 300 struct mcp9982_priv { 301 struct regmap *regmap; 302 const struct mcp9982_features *chip; 303 const char *labels[MCP9982_MAX_NUM_CHANNELS]; 304 unsigned int interval_idx; 305 unsigned long enabled_channel_mask; 306 u8 num_channels; 307 bool recd34_enable; 308 bool recd12_enable; 309 bool apdd_enable; 310 bool run_state; 311 }; 312 313 static int mcp9982_read_limit(struct mcp9982_priv *priv, u8 address, long *val) 314 { 315 unsigned int limit, reg_high, reg_low; 316 int ret; 317 318 switch (address) { 319 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 320 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 321 case MCP9982_THERM_LIMIT_ADDR(0): 322 case MCP9982_THERM_LIMIT_ADDR(1): 323 case MCP9982_THERM_LIMIT_ADDR(2): 324 case MCP9982_THERM_LIMIT_ADDR(3): 325 case MCP9982_THERM_LIMIT_ADDR(4): 326 ret = regmap_read(priv->regmap, address, &limit); 327 if (ret) 328 return ret; 329 330 *val = ((int)limit - MCP9982_OFFSET) * 1000; 331 332 return 0; 333 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 334 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 335 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 336 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 337 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 338 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 339 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 340 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 341 /* 342 * In order to keep consistency with reading temperature memory region we will use 343 * single byte I2C read. 344 */ 345 ret = regmap_read(priv->regmap, address, ®_high); 346 if (ret) 347 return ret; 348 349 ret = regmap_read(priv->regmap, address + 1, ®_low); 350 if (ret) 351 return ret; 352 353 *val = ((reg_high << 8) + reg_low) >> 5; 354 *val = (*val - (MCP9982_OFFSET << 3)) * 125; 355 356 return 0; 357 default: 358 return -EINVAL; 359 } 360 } 361 362 static int mcp9982_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, 363 long *val) 364 { 365 struct mcp9982_priv *priv = dev_get_drvdata(dev); 366 unsigned int reg_high, reg_low, hyst, reg_status; 367 int ret; 368 u8 addr; 369 370 /* 371 * In Standby State the conversion cycle must be initated manually in 372 * order to read fresh temperature values, the status of the alarms and 373 * fault information. 374 */ 375 if (!priv->run_state) { 376 switch (type) { 377 case hwmon_temp: 378 switch (attr) { 379 case hwmon_temp_input: 380 case hwmon_temp_max_alarm: 381 case hwmon_temp_min_alarm: 382 case hwmon_temp_crit_alarm: 383 case hwmon_temp_fault: 384 ret = regmap_write(priv->regmap, MCP9982_ONE_SHOT_ADDR, 1); 385 if (ret) 386 return ret; 387 /* 388 * When the device is in Standby mode, 125 ms need 389 * to pass from writing in One Shot register before 390 * the conversion cycle begins. 391 */ 392 usleep_range(MCP9982_WAKE_UP_TIME_US, MCP9982_WAKE_UP_TIME_MAX_US); 393 ret = regmap_read_poll_timeout 394 (priv->regmap, MCP9982_STATUS_ADDR, 395 reg_status, !(reg_status & MCP9982_STATUS_BUSY), 396 MCP9982_WAKE_UP_TIME_US, 397 MCP9982_WAKE_UP_TIME_US * 10); 398 break; 399 } 400 break; 401 default: 402 break; 403 } 404 } 405 406 switch (type) { 407 /* 408 * Because the ALERT/THERM pin is set in Therm(Comparator) mode, 409 * the external diode fault status, high limit status and low 410 * limit status registers do not clear the bits after reading. 411 */ 412 case hwmon_temp: 413 switch (attr) { 414 case hwmon_temp_input: 415 /* 416 * The only areas of memory that support SMBus block read are 80h->89h 417 * (temperature memory block) and 90h->97h(status memory block). 418 * In this context the read operation uses SMBus protocol and the first 419 * value returned will be the number of addresses that can be read. 420 * Temperature memory block is 10 bytes long and status memory block is 8 421 * bytes long. 422 * 423 * Depending on the read instruction used, the chip behaves differently: 424 * - regmap_bulk_read() when applied to the temperature memory block 425 * (80h->89h), the chip replies with SMBus block read, including count, 426 * additionally to the high and the low bytes. This function cannot be 427 * applied on the memory region 00h->09h(memory area which does not support 428 * block reads, returns wrong data) unless use_single_read is set in 429 * regmap_config. 430 * 431 * - regmap_multi_reg_read() when applied to the 00h->09h area uses I2C 432 * and returns only the high and low temperature bytes. When applied to 433 * the temperature memory block (80h->89h) returns the count till the end of 434 * the temperature memory block(aka SMBus count). 435 * 436 * - i2c_smbus_read_block_data() is not supported by all drivers. 437 * 438 * In order to keep consistency with reading limit memory region we will 439 * use single byte I2C read. 440 * 441 * Low register is latched when high temperature register is read. 442 */ 443 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel), ®_high); 444 if (ret) 445 return ret; 446 447 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel) + 1, 448 ®_low); 449 if (ret) 450 return ret; 451 452 *val = ((reg_high << 8) + reg_low) >> 5; 453 *val = (*val - (MCP9982_OFFSET << 3)) * 125; 454 455 return 0; 456 case hwmon_temp_max: 457 if (channel) 458 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 459 else 460 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 461 462 return mcp9982_read_limit(priv, addr, val); 463 case hwmon_temp_max_alarm: 464 *val = regmap_test_bits(priv->regmap, MCP9982_HIGH_LIMIT_STATUS_ADDR, 465 BIT(channel)); 466 if (*val < 0) 467 return *val; 468 469 return 0; 470 case hwmon_temp_max_hyst: 471 if (channel) 472 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 473 else 474 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 475 ret = mcp9982_read_limit(priv, addr, val); 476 if (ret) 477 return ret; 478 479 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst); 480 if (ret) 481 return ret; 482 483 *val -= hyst * 1000; 484 485 return 0; 486 case hwmon_temp_min: 487 if (channel) 488 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel); 489 else 490 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR; 491 492 return mcp9982_read_limit(priv, addr, val); 493 case hwmon_temp_min_alarm: 494 *val = regmap_test_bits(priv->regmap, MCP9982_LOW_LIMIT_STATUS_ADDR, 495 BIT(channel)); 496 if (*val < 0) 497 return *val; 498 499 return 0; 500 case hwmon_temp_crit: 501 return mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 502 case hwmon_temp_crit_alarm: 503 *val = regmap_test_bits(priv->regmap, MCP9982_THERM_LIMIT_STATUS_ADDR, 504 BIT(channel)); 505 if (*val < 0) 506 return *val; 507 508 return 0; 509 case hwmon_temp_crit_hyst: 510 ret = mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 511 if (ret) 512 return ret; 513 514 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst); 515 if (ret) 516 return ret; 517 518 *val -= hyst * 1000; 519 520 return 0; 521 case hwmon_temp_fault: 522 *val = regmap_test_bits(priv->regmap, MCP9982_EXT_FAULT_STATUS_ADDR, 523 BIT(channel)); 524 if (*val < 0) 525 return *val; 526 527 return 0; 528 default: 529 return -EINVAL; 530 } 531 case hwmon_chip: 532 switch (attr) { 533 case hwmon_chip_update_interval: 534 *val = mcp9982_update_interval[priv->interval_idx]; 535 return 0; 536 default: 537 return -EINVAL; 538 } 539 default: 540 return -EINVAL; 541 } 542 } 543 544 static int mcp9982_read_label(struct device *dev, enum hwmon_sensor_types type, u32 attr, 545 int channel, const char **str) 546 { 547 struct mcp9982_priv *priv = dev_get_drvdata(dev); 548 549 switch (type) { 550 case hwmon_temp: 551 switch (attr) { 552 case hwmon_temp_label: 553 *str = priv->labels[channel]; 554 return 0; 555 default: 556 return -EOPNOTSUPP; 557 } 558 default: 559 return -EOPNOTSUPP; 560 } 561 } 562 563 static int mcp9982_write_limit(struct mcp9982_priv *priv, u8 address, long val) 564 { 565 int ret; 566 unsigned int regh, regl; 567 568 switch (address) { 569 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 570 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 571 case MCP9982_THERM_LIMIT_ADDR(0): 572 case MCP9982_THERM_LIMIT_ADDR(1): 573 case MCP9982_THERM_LIMIT_ADDR(2): 574 case MCP9982_THERM_LIMIT_ADDR(3): 575 case MCP9982_THERM_LIMIT_ADDR(4): 576 regh = DIV_ROUND_CLOSEST(val, 1000); 577 regh = clamp_val(regh, 0, 255); 578 579 return regmap_write(priv->regmap, address, regh); 580 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 581 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 582 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 583 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 584 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 585 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 586 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 587 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 588 val = DIV_ROUND_CLOSEST(val, 125); 589 regh = (val >> 3) & 0xff; 590 regl = (val & 0x07) << 5; 591 /* Block writing is not supported by the chip. */ 592 ret = regmap_write(priv->regmap, address, regh); 593 if (ret) 594 return ret; 595 596 return regmap_write(priv->regmap, address + 1, regl); 597 default: 598 return -EINVAL; 599 } 600 } 601 602 static int mcp9982_write_hyst(struct mcp9982_priv *priv, int channel, long val) 603 { 604 int hyst, ret; 605 int limit; 606 607 val = DIV_ROUND_CLOSEST(val, 1000); 608 val = clamp_val(val, 0, 255); 609 610 /* Therm register is 8 bits and so it keeps only the integer part of the temperature. */ 611 ret = regmap_read(priv->regmap, MCP9982_THERM_LIMIT_ADDR(channel), &limit); 612 if (ret) 613 return ret; 614 615 hyst = clamp_val(limit - val, 0, 255); 616 617 return regmap_write(priv->regmap, MCP9982_HYS_ADDR, hyst); 618 } 619 620 static int mcp9982_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, 621 long val) 622 { 623 struct mcp9982_priv *priv = dev_get_drvdata(dev); 624 unsigned int idx; 625 u8 addr; 626 627 switch (type) { 628 case hwmon_chip: 629 switch (attr) { 630 case hwmon_chip_update_interval: 631 632 /* 633 * For MCP998XD and MCP9933D update interval 634 * can't be longer than 1 second. 635 */ 636 if (priv->chip->hw_thermal_shutdown) 637 val = clamp_val(val, 0, 1000); 638 639 idx = find_closest_descending(val, mcp9982_update_interval, 640 ARRAY_SIZE(mcp9982_update_interval)); 641 priv->interval_idx = idx; 642 643 return regmap_write(priv->regmap, MCP9982_CONV_ADDR, idx); 644 default: 645 return -EINVAL; 646 } 647 case hwmon_temp: 648 val = clamp_val(val, -64000, 191875); 649 val = val + (MCP9982_OFFSET * 1000); 650 switch (attr) { 651 case hwmon_temp_max: 652 if (channel) 653 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 654 else 655 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 656 657 return mcp9982_write_limit(priv, addr, val); 658 case hwmon_temp_min: 659 if (channel) 660 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel); 661 else 662 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR; 663 664 return mcp9982_write_limit(priv, addr, val); 665 case hwmon_temp_crit: 666 return mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 667 case hwmon_temp_crit_hyst: 668 return mcp9982_write_hyst(priv, channel, val); 669 default: 670 return -EINVAL; 671 } 672 default: 673 return -EINVAL; 674 } 675 } 676 677 static umode_t mcp9982_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr, 678 int channel) 679 { 680 const struct mcp9982_priv *priv = _data; 681 682 if (!test_bit(channel, &priv->enabled_channel_mask)) 683 return 0; 684 685 switch (type) { 686 case hwmon_temp: 687 switch (attr) { 688 case hwmon_temp_label: 689 if (priv->labels[channel]) 690 return 0444; 691 else 692 return 0; 693 case hwmon_temp_input: 694 case hwmon_temp_min_alarm: 695 case hwmon_temp_max_alarm: 696 case hwmon_temp_max_hyst: 697 case hwmon_temp_crit_alarm: 698 case hwmon_temp_fault: 699 return 0444; 700 case hwmon_temp_min: 701 case hwmon_temp_max: 702 case hwmon_temp_crit: 703 case hwmon_temp_crit_hyst: 704 return 0644; 705 default: 706 return 0; 707 } 708 case hwmon_chip: 709 switch (attr) { 710 case hwmon_chip_update_interval: 711 return 0644; 712 default: 713 return 0; 714 } 715 default: 716 return 0; 717 } 718 } 719 720 static const struct hwmon_ops mcp9982_hwmon_ops = { 721 .is_visible = mcp9982_is_visible, 722 .read = mcp9982_read, 723 .read_string = mcp9982_read_label, 724 .write = mcp9982_write, 725 }; 726 727 static int mcp9982_init(struct device *dev, struct mcp9982_priv *priv) 728 { 729 long high_limit, low_limit; 730 unsigned int i; 731 int ret; 732 u8 val; 733 734 /* Chips 82/83 and 82D/83D do not support anti-parallel diode mode. */ 735 if (!priv->chip->allow_apdd && priv->apdd_enable == 1) 736 return dev_err_probe(dev, -EINVAL, "Incorrect setting of APDD.\n"); 737 738 /* Chips with "D" work only in Run state. */ 739 if (priv->chip->hw_thermal_shutdown && !priv->run_state) 740 return dev_err_probe(dev, -EINVAL, "Incorrect setting of Power State.\n"); 741 742 /* All chips with "D" in the name must have RECD12 enabled. */ 743 if (priv->chip->hw_thermal_shutdown && !priv->recd12_enable) 744 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD12.\n"); 745 /* Chips 83D/84D/85D must have RECD34 enabled. */ 746 if (priv->chip->hw_thermal_shutdown) 747 if ((priv->chip->has_recd34 && !priv->recd34_enable)) 748 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD34.\n"); 749 750 /* 751 * Set default values in registers. 752 * APDD, RECD12 and RECD34 are active on 0. 753 */ 754 val = FIELD_PREP(MCP9982_CFG_MSKAL, 1) | 755 FIELD_PREP(MCP9982_CFG_RS, !priv->run_state) | 756 FIELD_PREP(MCP9982_CFG_ATTHM, 1) | 757 FIELD_PREP(MCP9982_CFG_RECD12, !priv->recd12_enable) | 758 FIELD_PREP(MCP9982_CFG_RECD34, !priv->recd34_enable) | 759 FIELD_PREP(MCP9982_CFG_RANGE, 1) | FIELD_PREP(MCP9982_CFG_DA_ENA, 0) | 760 FIELD_PREP(MCP9982_CFG_APDD, !priv->apdd_enable); 761 762 ret = regmap_write(priv->regmap, MCP9982_CFG_ADDR, val); 763 if (ret) 764 return ret; 765 766 /* 767 * Read initial value from register. 768 * The convert register utilises only 4 out of 8 bits. 769 * Numerical values 0->10 set their respective update intervals, 770 * while numerical values 11->15 default to 1 second. 771 */ 772 ret = regmap_read(priv->regmap, MCP9982_CONV_ADDR, &priv->interval_idx); 773 if (ret) 774 return ret; 775 if (priv->interval_idx >= 11) 776 priv->interval_idx = 4; 777 778 ret = regmap_write(priv->regmap, MCP9982_HYS_ADDR, MCP9982_DEFAULT_HYS_VAL); 779 if (ret) 780 return ret; 781 782 ret = regmap_write(priv->regmap, MCP9982_CONSEC_ALRT_ADDR, MCP9982_DEFAULT_CONSEC_ALRT_VAL); 783 if (ret) 784 return ret; 785 786 ret = regmap_write(priv->regmap, MCP9982_ALRT_CFG_ADDR, 0); 787 if (ret) 788 return ret; 789 790 ret = regmap_write(priv->regmap, MCP9982_RUNNING_AVG_ADDR, 0); 791 if (ret) 792 return ret; 793 794 ret = regmap_write(priv->regmap, MCP9982_HOTTEST_CFG_ADDR, 0); 795 if (ret) 796 return ret; 797 798 /* 799 * Only external channels 1 and 2 support beta compensation. 800 * Set beta auto-detection. 801 */ 802 for (i = 1; i < 3; i++) 803 if (test_bit(i, &priv->enabled_channel_mask)) { 804 ret = regmap_write(priv->regmap, MCP9982_EXT_BETA_CFG_ADDR(i), 805 MCP9982_BETA_AUTODETECT); 806 if (ret) 807 return ret; 808 } 809 810 high_limit = MCP9982_HIGH_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000); 811 low_limit = MCP9982_LOW_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000); 812 813 /* Set default values for internal channel limits. */ 814 if (test_bit(0, &priv->enabled_channel_mask)) { 815 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_HIGH_LIMIT_ADDR, high_limit); 816 if (ret) 817 return ret; 818 819 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_LOW_LIMIT_ADDR, low_limit); 820 if (ret) 821 return ret; 822 823 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(0), high_limit); 824 if (ret) 825 return ret; 826 } 827 828 /* Set ideality factor and limits to default for external channels. */ 829 for (i = 1; i < MCP9982_MAX_NUM_CHANNELS; i++) 830 if (test_bit(i, &priv->enabled_channel_mask)) { 831 ret = regmap_write(priv->regmap, MCP9982_EXT_IDEAL_ADDR(i), 832 MCP9982_IDEALITY_DEFAULT); 833 if (ret) 834 return ret; 835 836 ret = mcp9982_write_limit(priv, MCP9982_EXT_HIGH_LIMIT_ADDR(i), high_limit); 837 if (ret) 838 return ret; 839 840 ret = mcp9982_write_limit(priv, MCP9982_EXT_LOW_LIMIT_ADDR(i), low_limit); 841 if (ret) 842 return ret; 843 844 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(i), high_limit); 845 if (ret) 846 return ret; 847 } 848 849 return 0; 850 } 851 852 static int mcp9982_parse_fw_config(struct device *dev, int device_nr_channels) 853 { 854 struct mcp9982_priv *priv = dev_get_drvdata(dev); 855 unsigned int reg_nr; 856 int ret; 857 858 /* Initialise internal channel( which is always present ). */ 859 priv->labels[0] = "internal diode"; 860 priv->enabled_channel_mask = 1; 861 862 /* Default values to work on systems without devicetree or firmware nodes. */ 863 if (!dev_fwnode(dev)) { 864 priv->num_channels = device_nr_channels; 865 priv->enabled_channel_mask = BIT(priv->num_channels) - 1; 866 priv->apdd_enable = false; 867 priv->recd12_enable = true; 868 priv->recd34_enable = true; 869 priv->run_state = true; 870 return 0; 871 } 872 873 priv->apdd_enable = 874 device_property_read_bool(dev, "microchip,enable-anti-parallel"); 875 876 priv->recd12_enable = 877 device_property_read_bool(dev, "microchip,parasitic-res-on-channel1-2"); 878 879 priv->recd34_enable = 880 device_property_read_bool(dev, "microchip,parasitic-res-on-channel3-4"); 881 882 priv->run_state = 883 device_property_read_bool(dev, "microchip,power-state"); 884 885 priv->num_channels = device_get_child_node_count(dev) + 1; 886 887 if (priv->num_channels > device_nr_channels) 888 return dev_err_probe(dev, -EINVAL, 889 "More channels than the chip supports.\n"); 890 891 /* Read information about the external channels. */ 892 device_for_each_named_child_node_scoped(dev, child, "channel") { 893 reg_nr = 0; 894 ret = fwnode_property_read_u32(child, "reg", ®_nr); 895 if (ret || !reg_nr || reg_nr >= device_nr_channels) 896 return dev_err_probe(dev, -EINVAL, 897 "Channel reg is incorrectly set.\n"); 898 899 fwnode_property_read_string(child, "label", &priv->labels[reg_nr]); 900 set_bit(reg_nr, &priv->enabled_channel_mask); 901 } 902 903 return 0; 904 } 905 906 static const struct hwmon_chip_info mcp998x_chip_info = { 907 .ops = &mcp9982_hwmon_ops, 908 .info = mcp9985_info, 909 }; 910 911 static int mcp9982_probe(struct i2c_client *client) 912 { 913 const struct mcp9982_features *chip; 914 struct device *dev = &client->dev; 915 struct mcp9982_priv *priv; 916 struct device *hwmon_dev; 917 int ret; 918 919 priv = devm_kzalloc(dev, sizeof(struct mcp9982_priv), GFP_KERNEL); 920 if (!priv) 921 return -ENOMEM; 922 923 priv->regmap = devm_regmap_init_i2c(client, &mcp9982_regmap_config); 924 925 if (IS_ERR(priv->regmap)) 926 return dev_err_probe(dev, PTR_ERR(priv->regmap), 927 "Cannot initialize register map.\n"); 928 929 dev_set_drvdata(dev, priv); 930 931 chip = i2c_get_match_data(client); 932 if (!chip) 933 return -EINVAL; 934 priv->chip = chip; 935 936 ret = mcp9982_parse_fw_config(dev, chip->phys_channels); 937 if (ret) 938 return ret; 939 940 ret = mcp9982_init(dev, priv); 941 if (ret) 942 return ret; 943 944 hwmon_dev = devm_hwmon_device_register_with_info(dev, chip->name, priv, 945 &mcp998x_chip_info, NULL); 946 947 return PTR_ERR_OR_ZERO(hwmon_dev); 948 } 949 950 static const struct i2c_device_id mcp9982_id[] = { 951 { .name = "mcp9933", .driver_data = (kernel_ulong_t)&mcp9933_chip_config }, 952 { .name = "mcp9933d", .driver_data = (kernel_ulong_t)&mcp9933d_chip_config }, 953 { .name = "mcp9982", .driver_data = (kernel_ulong_t)&mcp9982_chip_config }, 954 { .name = "mcp9982d", .driver_data = (kernel_ulong_t)&mcp9982d_chip_config }, 955 { .name = "mcp9983", .driver_data = (kernel_ulong_t)&mcp9983_chip_config }, 956 { .name = "mcp9983d", .driver_data = (kernel_ulong_t)&mcp9983d_chip_config }, 957 { .name = "mcp9984", .driver_data = (kernel_ulong_t)&mcp9984_chip_config }, 958 { .name = "mcp9984d", .driver_data = (kernel_ulong_t)&mcp9984d_chip_config }, 959 { .name = "mcp9985", .driver_data = (kernel_ulong_t)&mcp9985_chip_config }, 960 { .name = "mcp9985d", .driver_data = (kernel_ulong_t)&mcp9985d_chip_config }, 961 { } 962 }; 963 MODULE_DEVICE_TABLE(i2c, mcp9982_id); 964 965 static const struct of_device_id mcp9982_of_match[] = { 966 { 967 .compatible = "microchip,mcp9933", 968 .data = &mcp9933_chip_config, 969 }, { 970 .compatible = "microchip,mcp9933d", 971 .data = &mcp9933d_chip_config, 972 }, { 973 .compatible = "microchip,mcp9982", 974 .data = &mcp9982_chip_config, 975 }, { 976 .compatible = "microchip,mcp9982d", 977 .data = &mcp9982d_chip_config, 978 }, { 979 .compatible = "microchip,mcp9983", 980 .data = &mcp9983_chip_config, 981 }, { 982 .compatible = "microchip,mcp9983d", 983 .data = &mcp9983d_chip_config, 984 }, { 985 .compatible = "microchip,mcp9984", 986 .data = &mcp9984_chip_config, 987 }, { 988 .compatible = "microchip,mcp9984d", 989 .data = &mcp9984d_chip_config, 990 }, { 991 .compatible = "microchip,mcp9985", 992 .data = &mcp9985_chip_config, 993 }, { 994 .compatible = "microchip,mcp9985d", 995 .data = &mcp9985d_chip_config, 996 }, 997 { } 998 }; 999 MODULE_DEVICE_TABLE(of, mcp9982_of_match); 1000 1001 static struct i2c_driver mcp9982_driver = { 1002 .driver = { 1003 .name = "mcp9982", 1004 .of_match_table = mcp9982_of_match, 1005 }, 1006 .probe = mcp9982_probe, 1007 .id_table = mcp9982_id, 1008 }; 1009 module_i2c_driver(mcp9982_driver); 1010 1011 MODULE_AUTHOR("Victor Duicu <victor.duicu@microchip.com>"); 1012 MODULE_DESCRIPTION("MCP998X/33 and MCP998XD/33D Multichannel Automotive Temperature Monitor Driver"); 1013 MODULE_LICENSE("GPL"); 1014