1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * HWMON driver for MCP998X/33 and MCP998XD/33D Multichannel Automotive 4 * Temperature Monitor Family 5 * 6 * Copyright (C) 2026 Microchip Technology Inc. and its subsidiaries 7 * 8 * Author: Victor Duicu <victor.duicu@microchip.com> 9 * 10 * Datasheet can be found here: 11 * https://ww1.microchip.com/downloads/aemDocuments/documents/MSLD/ProductDocuments/DataSheets/MCP998X-Family-Data-Sheet-DS20006827.pdf 12 */ 13 14 #include <linux/array_size.h> 15 #include <linux/bitfield.h> 16 #include <linux/bitops.h> 17 #include <linux/bits.h> 18 #include <linux/byteorder/generic.h> 19 #include <linux/delay.h> 20 #include <linux/device/devres.h> 21 #include <linux/device.h> 22 #include <linux/dev_printk.h> 23 #include <linux/err.h> 24 #include <linux/hwmon.h> 25 #include <linux/i2c.h> 26 #include <linux/math.h> 27 #include <linux/minmax.h> 28 #include <linux/property.h> 29 #include <linux/regmap.h> 30 #include <linux/time64.h> 31 #include <linux/util_macros.h> 32 33 /* MCP9982 Registers */ 34 #define MCP9982_HIGH_BYTE_ADDR(index) (2 * (index)) 35 #define MCP9982_ONE_SHOT_ADDR 0x0A 36 #define MCP9982_INTERNAL_HIGH_LIMIT_ADDR 0x0B 37 #define MCP9982_INTERNAL_LOW_LIMIT_ADDR 0x0C 38 #define MCP9982_EXT_HIGH_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0D) 39 #define MCP9982_EXT_LOW_LIMIT_ADDR(index) (4 * ((index) - 1) + 0x0F) 40 #define MCP9982_THERM_LIMIT_ADDR(index) ((index) + 0x1D) 41 #define MCP9982_CFG_ADDR 0x22 42 #define MCP9982_CONV_ADDR 0x24 43 #define MCP9982_HYS_ADDR 0x25 44 #define MCP9982_CONSEC_ALRT_ADDR 0x26 45 #define MCP9982_ALRT_CFG_ADDR 0x27 46 #define MCP9982_RUNNING_AVG_ADDR 0x28 47 #define MCP9982_HOTTEST_CFG_ADDR 0x29 48 #define MCP9982_STATUS_ADDR 0x2A 49 #define MCP9982_EXT_FAULT_STATUS_ADDR 0x2B 50 #define MCP9982_HIGH_LIMIT_STATUS_ADDR 0x2C 51 #define MCP9982_LOW_LIMIT_STATUS_ADDR 0x2D 52 #define MCP9982_THERM_LIMIT_STATUS_ADDR 0x2E 53 #define MCP9982_HOTTEST_HIGH_BYTE_ADDR 0x2F 54 #define MCP9982_HOTTEST_LOW_BYTE_ADDR 0x30 55 #define MCP9982_HOTTEST_STATUS_ADDR 0x31 56 #define MCP9982_THERM_SHTDWN_CFG_ADDR 0x32 57 #define MCP9982_HRDW_THERM_SHTDWN_LIMIT_ADDR 0x33 58 #define MCP9982_EXT_BETA_CFG_ADDR(index) ((index) + 0x33) 59 #define MCP9982_EXT_IDEAL_ADDR(index) ((index) + 0x35) 60 61 /* MCP9982 Bits */ 62 #define MCP9982_CFG_MSKAL BIT(7) 63 #define MCP9982_CFG_RS BIT(6) 64 #define MCP9982_CFG_ATTHM BIT(5) 65 #define MCP9982_CFG_RECD12 BIT(4) 66 #define MCP9982_CFG_RECD34 BIT(3) 67 #define MCP9982_CFG_RANGE BIT(2) 68 #define MCP9982_CFG_DA_ENA BIT(1) 69 #define MCP9982_CFG_APDD BIT(0) 70 71 #define MCP9982_STATUS_BUSY BIT(5) 72 73 /* Constants and default values */ 74 #define MCP9982_MAX_NUM_CHANNELS 5 75 #define MCP9982_BETA_AUTODETECT 16 76 #define MCP9982_IDEALITY_DEFAULT 18 77 #define MCP9982_OFFSET 64 78 #define MCP9982_DEFAULT_CONSEC_ALRT_VAL 112 79 #define MCP9982_DEFAULT_HYS_VAL 10 80 #define MCP9982_DEFAULT_CONV_VAL 6 81 #define MCP9982_WAKE_UP_TIME_US 125000 82 #define MCP9982_WAKE_UP_TIME_MAX_US 130000 83 #define MCP9982_HIGH_LIMIT_DEFAULT 85000 84 #define MCP9982_LOW_LIMIT_DEFAULT 0 85 86 static const struct hwmon_channel_info * const mcp9985_info[] = { 87 HWMON_CHANNEL_INFO(temp, 88 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 89 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 90 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 91 HWMON_T_CRIT_HYST, 92 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 93 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 94 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 95 HWMON_T_CRIT_HYST, 96 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 97 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 98 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 99 HWMON_T_CRIT_HYST, 100 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 101 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 102 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 103 HWMON_T_CRIT_HYST, 104 HWMON_T_INPUT | HWMON_T_LABEL | HWMON_T_MIN | 105 HWMON_T_MIN_ALARM | HWMON_T_MAX | HWMON_T_MAX_ALARM | 106 HWMON_T_MAX_HYST | HWMON_T_CRIT | HWMON_T_CRIT_ALARM | 107 HWMON_T_CRIT_HYST), 108 HWMON_CHANNEL_INFO(chip, 109 HWMON_C_UPDATE_INTERVAL), 110 NULL 111 }; 112 113 /** 114 * struct mcp9982_features - features of a mcp9982 instance 115 * @name: chip's name 116 * @phys_channels: number of physical channels supported by the chip 117 * @hw_thermal_shutdown: presence of hardware thermal shutdown circuitry 118 * @allow_apdd: whether the chip supports enabling APDD 119 * @has_recd34: whether the chip has the channels that are affected by recd34 120 */ 121 struct mcp9982_features { 122 const char *name; 123 u8 phys_channels; 124 bool hw_thermal_shutdown; 125 bool allow_apdd; 126 bool has_recd34; 127 }; 128 129 static const struct mcp9982_features mcp9933_chip_config = { 130 .name = "mcp9933", 131 .phys_channels = 3, 132 .hw_thermal_shutdown = false, 133 .allow_apdd = true, 134 .has_recd34 = false, 135 }; 136 137 static const struct mcp9982_features mcp9933d_chip_config = { 138 .name = "mcp9933d", 139 .phys_channels = 3, 140 .hw_thermal_shutdown = true, 141 .allow_apdd = true, 142 .has_recd34 = false, 143 }; 144 145 static const struct mcp9982_features mcp9982_chip_config = { 146 .name = "mcp9982", 147 .phys_channels = 2, 148 .hw_thermal_shutdown = false, 149 .allow_apdd = false, 150 .has_recd34 = false, 151 }; 152 153 static const struct mcp9982_features mcp9982d_chip_config = { 154 .name = "mcp9982d", 155 .phys_channels = 2, 156 .hw_thermal_shutdown = true, 157 .allow_apdd = false, 158 .has_recd34 = false, 159 }; 160 161 static const struct mcp9982_features mcp9983_chip_config = { 162 .name = "mcp9983", 163 .phys_channels = 3, 164 .hw_thermal_shutdown = false, 165 .allow_apdd = false, 166 .has_recd34 = true, 167 }; 168 169 static const struct mcp9982_features mcp9983d_chip_config = { 170 .name = "mcp9983d", 171 .phys_channels = 3, 172 .hw_thermal_shutdown = true, 173 .allow_apdd = false, 174 .has_recd34 = true, 175 }; 176 177 static const struct mcp9982_features mcp9984_chip_config = { 178 .name = "mcp9984", 179 .phys_channels = 4, 180 .hw_thermal_shutdown = false, 181 .allow_apdd = true, 182 .has_recd34 = true, 183 }; 184 185 static const struct mcp9982_features mcp9984d_chip_config = { 186 .name = "mcp9984d", 187 .phys_channels = 4, 188 .hw_thermal_shutdown = true, 189 .allow_apdd = true, 190 .has_recd34 = true, 191 }; 192 193 static const struct mcp9982_features mcp9985_chip_config = { 194 .name = "mcp9985", 195 .phys_channels = 5, 196 .hw_thermal_shutdown = false, 197 .allow_apdd = true, 198 .has_recd34 = true, 199 }; 200 201 static const struct mcp9982_features mcp9985d_chip_config = { 202 .name = "mcp9985d", 203 .phys_channels = 5, 204 .hw_thermal_shutdown = true, 205 .allow_apdd = true, 206 .has_recd34 = true, 207 }; 208 209 static const unsigned int mcp9982_update_interval[11] = { 210 16000, 8000, 4000, 2000, 1000, 500, 250, 125, 64, 32, 16 211 }; 212 213 /* MCP9982 regmap configuration */ 214 static const struct regmap_range mcp9982_regmap_wr_ranges[] = { 215 regmap_reg_range(MCP9982_ONE_SHOT_ADDR, MCP9982_CFG_ADDR), 216 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_HOTTEST_CFG_ADDR), 217 regmap_reg_range(MCP9982_THERM_SHTDWN_CFG_ADDR, MCP9982_THERM_SHTDWN_CFG_ADDR), 218 regmap_reg_range(MCP9982_EXT_BETA_CFG_ADDR(1), MCP9982_EXT_IDEAL_ADDR(4)), 219 }; 220 221 static const struct regmap_access_table mcp9982_regmap_wr_table = { 222 .yes_ranges = mcp9982_regmap_wr_ranges, 223 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_wr_ranges), 224 }; 225 226 static const struct regmap_range mcp9982_regmap_rd_ranges[] = { 227 regmap_reg_range(MCP9982_HIGH_BYTE_ADDR(0), MCP9982_CFG_ADDR), 228 regmap_reg_range(MCP9982_CONV_ADDR, MCP9982_EXT_IDEAL_ADDR(4)), 229 }; 230 231 static const struct regmap_access_table mcp9982_regmap_rd_table = { 232 .yes_ranges = mcp9982_regmap_rd_ranges, 233 .n_yes_ranges = ARRAY_SIZE(mcp9982_regmap_rd_ranges), 234 }; 235 236 static bool mcp9982_is_volatile_reg(struct device *dev, unsigned int reg) 237 { 238 switch (reg) { 239 case MCP9982_ONE_SHOT_ADDR: 240 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 241 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 242 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 243 case MCP9982_EXT_LOW_LIMIT_ADDR(1) + 1: 244 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 245 case MCP9982_EXT_LOW_LIMIT_ADDR(2) + 1: 246 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 247 case MCP9982_EXT_LOW_LIMIT_ADDR(3) + 1: 248 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 249 case MCP9982_EXT_LOW_LIMIT_ADDR(4) + 1: 250 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 251 case MCP9982_EXT_HIGH_LIMIT_ADDR(1) + 1: 252 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 253 case MCP9982_EXT_HIGH_LIMIT_ADDR(2) + 1: 254 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 255 case MCP9982_EXT_HIGH_LIMIT_ADDR(3) + 1: 256 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 257 case MCP9982_EXT_HIGH_LIMIT_ADDR(4) + 1: 258 case MCP9982_THERM_LIMIT_ADDR(0): 259 case MCP9982_THERM_LIMIT_ADDR(1): 260 case MCP9982_THERM_LIMIT_ADDR(2): 261 case MCP9982_THERM_LIMIT_ADDR(3): 262 case MCP9982_THERM_LIMIT_ADDR(4): 263 case MCP9982_CFG_ADDR: 264 case MCP9982_CONV_ADDR: 265 case MCP9982_HYS_ADDR: 266 case MCP9982_CONSEC_ALRT_ADDR: 267 case MCP9982_ALRT_CFG_ADDR: 268 case MCP9982_RUNNING_AVG_ADDR: 269 case MCP9982_HOTTEST_CFG_ADDR: 270 case MCP9982_THERM_SHTDWN_CFG_ADDR: 271 return false; 272 default: 273 return true; 274 } 275 } 276 277 static const struct regmap_config mcp9982_regmap_config = { 278 .reg_bits = 8, 279 .val_bits = 8, 280 .rd_table = &mcp9982_regmap_rd_table, 281 .wr_table = &mcp9982_regmap_wr_table, 282 .volatile_reg = mcp9982_is_volatile_reg, 283 .max_register = MCP9982_EXT_IDEAL_ADDR(4), 284 .cache_type = REGCACHE_MAPLE, 285 }; 286 287 /** 288 * struct mcp9982_priv - information about chip parameters 289 * @regmap: device register map 290 * @chip: pointer to structure holding chip features 291 * @labels: labels of the channels 292 * @interval_idx: index representing the current update interval 293 * @enabled_channel_mask: mask containing which channels should be enabled 294 * @num_channels: number of active physical channels 295 * @recd34_enable: state of Resistance Error Correction(REC) on channels 3 and 4 296 * @recd12_enable: state of Resistance Error Correction(REC) on channels 1 and 2 297 * @apdd_enable: state of anti-parallel diode mode 298 * @run_state: chip is in Run state, otherwise is in Standby state 299 */ 300 struct mcp9982_priv { 301 struct regmap *regmap; 302 const struct mcp9982_features *chip; 303 const char *labels[MCP9982_MAX_NUM_CHANNELS]; 304 unsigned int interval_idx; 305 unsigned long enabled_channel_mask; 306 u8 num_channels; 307 bool recd34_enable; 308 bool recd12_enable; 309 bool apdd_enable; 310 bool run_state; 311 }; 312 313 static int mcp9982_read_limit(struct mcp9982_priv *priv, u8 address, long *val) 314 { 315 unsigned int limit, reg_high, reg_low; 316 int ret; 317 318 switch (address) { 319 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 320 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 321 case MCP9982_THERM_LIMIT_ADDR(0): 322 case MCP9982_THERM_LIMIT_ADDR(1): 323 case MCP9982_THERM_LIMIT_ADDR(2): 324 case MCP9982_THERM_LIMIT_ADDR(3): 325 case MCP9982_THERM_LIMIT_ADDR(4): 326 ret = regmap_read(priv->regmap, address, &limit); 327 if (ret) 328 return ret; 329 330 *val = ((int)limit - MCP9982_OFFSET) * 1000; 331 332 return 0; 333 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 334 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 335 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 336 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 337 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 338 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 339 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 340 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 341 /* 342 * In order to keep consistency with reading temperature memory region we will use 343 * single byte I2C read. 344 */ 345 ret = regmap_read(priv->regmap, address, ®_high); 346 if (ret) 347 return ret; 348 349 ret = regmap_read(priv->regmap, address + 1, ®_low); 350 if (ret) 351 return ret; 352 353 *val = ((reg_high << 8) + reg_low) >> 5; 354 *val = (*val - (MCP9982_OFFSET << 3)) * 125; 355 356 return 0; 357 default: 358 return -EINVAL; 359 } 360 } 361 362 static int mcp9982_read(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, 363 long *val) 364 { 365 struct mcp9982_priv *priv = dev_get_drvdata(dev); 366 unsigned int reg_high, reg_low, hyst, reg_status; 367 int ret; 368 u8 addr; 369 370 /* 371 * In Standby State the conversion cycle must be initated manually in 372 * order to read fresh temperature values and the status of the alarms. 373 */ 374 if (!priv->run_state) { 375 switch (type) { 376 case hwmon_temp: 377 switch (attr) { 378 case hwmon_temp_input: 379 case hwmon_temp_max_alarm: 380 case hwmon_temp_min_alarm: 381 case hwmon_temp_crit_alarm: 382 ret = regmap_write(priv->regmap, MCP9982_ONE_SHOT_ADDR, 1); 383 if (ret) 384 return ret; 385 /* 386 * When the device is in Standby mode, 125 ms need 387 * to pass from writing in One Shot register before 388 * the conversion cycle begins. 389 */ 390 usleep_range(MCP9982_WAKE_UP_TIME_US, MCP9982_WAKE_UP_TIME_MAX_US); 391 ret = regmap_read_poll_timeout 392 (priv->regmap, MCP9982_STATUS_ADDR, 393 reg_status, !(reg_status & MCP9982_STATUS_BUSY), 394 MCP9982_WAKE_UP_TIME_US, 395 MCP9982_WAKE_UP_TIME_US * 10); 396 break; 397 } 398 break; 399 default: 400 break; 401 } 402 } 403 404 switch (type) { 405 case hwmon_temp: 406 switch (attr) { 407 case hwmon_temp_input: 408 /* 409 * The only areas of memory that support SMBus block read are 80h->89h 410 * (temperature memory block) and 90h->97h(status memory block). 411 * In this context the read operation uses SMBus protocol and the first 412 * value returned will be the number of addresses that can be read. 413 * Temperature memory block is 10 bytes long and status memory block is 8 414 * bytes long. 415 * 416 * Depending on the read instruction used, the chip behaves differently: 417 * - regmap_bulk_read() when applied to the temperature memory block 418 * (80h->89h), the chip replies with SMBus block read, including count, 419 * additionally to the high and the low bytes. This function cannot be 420 * applied on the memory region 00h->09h(memory area which does not support 421 * block reads, returns wrong data) unless use_single_read is set in 422 * regmap_config. 423 * 424 * - regmap_multi_reg_read() when applied to the 00h->09h area uses I2C 425 * and returns only the high and low temperature bytes. When applied to 426 * the temperature memory block (80h->89h) returns the count till the end of 427 * the temperature memory block(aka SMBus count). 428 * 429 * - i2c_smbus_read_block_data() is not supported by all drivers. 430 * 431 * In order to keep consistency with reading limit memory region we will 432 * use single byte I2C read. 433 * 434 * Low register is latched when high temperature register is read. 435 */ 436 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel), ®_high); 437 if (ret) 438 return ret; 439 440 ret = regmap_read(priv->regmap, MCP9982_HIGH_BYTE_ADDR(channel) + 1, 441 ®_low); 442 if (ret) 443 return ret; 444 445 *val = ((reg_high << 8) + reg_low) >> 5; 446 *val = (*val - (MCP9982_OFFSET << 3)) * 125; 447 448 return 0; 449 case hwmon_temp_max: 450 if (channel) 451 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 452 else 453 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 454 455 return mcp9982_read_limit(priv, addr, val); 456 case hwmon_temp_max_alarm: 457 *val = regmap_test_bits(priv->regmap, MCP9982_HIGH_LIMIT_STATUS_ADDR, 458 BIT(channel)); 459 if (*val < 0) 460 return *val; 461 462 return 0; 463 case hwmon_temp_max_hyst: 464 if (channel) 465 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 466 else 467 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 468 ret = mcp9982_read_limit(priv, addr, val); 469 if (ret) 470 return ret; 471 472 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst); 473 if (ret) 474 return ret; 475 476 *val -= hyst * 1000; 477 478 return 0; 479 case hwmon_temp_min: 480 if (channel) 481 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel); 482 else 483 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR; 484 485 return mcp9982_read_limit(priv, addr, val); 486 case hwmon_temp_min_alarm: 487 *val = regmap_test_bits(priv->regmap, MCP9982_LOW_LIMIT_STATUS_ADDR, 488 BIT(channel)); 489 if (*val < 0) 490 return *val; 491 492 return 0; 493 case hwmon_temp_crit: 494 return mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 495 case hwmon_temp_crit_alarm: 496 *val = regmap_test_bits(priv->regmap, MCP9982_THERM_LIMIT_STATUS_ADDR, 497 BIT(channel)); 498 if (*val < 0) 499 return *val; 500 501 return 0; 502 case hwmon_temp_crit_hyst: 503 ret = mcp9982_read_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 504 if (ret) 505 return ret; 506 507 ret = regmap_read(priv->regmap, MCP9982_HYS_ADDR, &hyst); 508 if (ret) 509 return ret; 510 511 *val -= hyst * 1000; 512 513 return 0; 514 default: 515 return -EINVAL; 516 } 517 case hwmon_chip: 518 switch (attr) { 519 case hwmon_chip_update_interval: 520 *val = mcp9982_update_interval[priv->interval_idx]; 521 return 0; 522 default: 523 return -EINVAL; 524 } 525 default: 526 return -EINVAL; 527 } 528 } 529 530 static int mcp9982_read_label(struct device *dev, enum hwmon_sensor_types type, u32 attr, 531 int channel, const char **str) 532 { 533 struct mcp9982_priv *priv = dev_get_drvdata(dev); 534 535 switch (type) { 536 case hwmon_temp: 537 switch (attr) { 538 case hwmon_temp_label: 539 *str = priv->labels[channel]; 540 return 0; 541 default: 542 return -EOPNOTSUPP; 543 } 544 default: 545 return -EOPNOTSUPP; 546 } 547 } 548 549 static int mcp9982_write_limit(struct mcp9982_priv *priv, u8 address, long val) 550 { 551 int ret; 552 unsigned int regh, regl; 553 554 switch (address) { 555 case MCP9982_INTERNAL_HIGH_LIMIT_ADDR: 556 case MCP9982_INTERNAL_LOW_LIMIT_ADDR: 557 case MCP9982_THERM_LIMIT_ADDR(0): 558 case MCP9982_THERM_LIMIT_ADDR(1): 559 case MCP9982_THERM_LIMIT_ADDR(2): 560 case MCP9982_THERM_LIMIT_ADDR(3): 561 case MCP9982_THERM_LIMIT_ADDR(4): 562 regh = DIV_ROUND_CLOSEST(val, 1000); 563 regh = clamp_val(regh, 0, 255); 564 565 return regmap_write(priv->regmap, address, regh); 566 case MCP9982_EXT_HIGH_LIMIT_ADDR(1): 567 case MCP9982_EXT_HIGH_LIMIT_ADDR(2): 568 case MCP9982_EXT_HIGH_LIMIT_ADDR(3): 569 case MCP9982_EXT_HIGH_LIMIT_ADDR(4): 570 case MCP9982_EXT_LOW_LIMIT_ADDR(1): 571 case MCP9982_EXT_LOW_LIMIT_ADDR(2): 572 case MCP9982_EXT_LOW_LIMIT_ADDR(3): 573 case MCP9982_EXT_LOW_LIMIT_ADDR(4): 574 val = DIV_ROUND_CLOSEST(val, 125); 575 regh = (val >> 3) & 0xff; 576 regl = (val & 0x07) << 5; 577 /* Block writing is not supported by the chip. */ 578 ret = regmap_write(priv->regmap, address, regh); 579 if (ret) 580 return ret; 581 582 return regmap_write(priv->regmap, address + 1, regl); 583 default: 584 return -EINVAL; 585 } 586 } 587 588 static int mcp9982_write_hyst(struct mcp9982_priv *priv, int channel, long val) 589 { 590 int hyst, ret; 591 int limit; 592 593 val = DIV_ROUND_CLOSEST(val, 1000); 594 val = clamp_val(val, 0, 255); 595 596 /* Therm register is 8 bits and so it keeps only the integer part of the temperature. */ 597 ret = regmap_read(priv->regmap, MCP9982_THERM_LIMIT_ADDR(channel), &limit); 598 if (ret) 599 return ret; 600 601 hyst = clamp_val(limit - val, 0, 255); 602 603 return regmap_write(priv->regmap, MCP9982_HYS_ADDR, hyst); 604 } 605 606 static int mcp9982_write(struct device *dev, enum hwmon_sensor_types type, u32 attr, int channel, 607 long val) 608 { 609 struct mcp9982_priv *priv = dev_get_drvdata(dev); 610 unsigned int idx; 611 u8 addr; 612 613 switch (type) { 614 case hwmon_chip: 615 switch (attr) { 616 case hwmon_chip_update_interval: 617 618 /* 619 * For MCP998XD and MCP9933D update interval 620 * can't be longer than 1 second. 621 */ 622 if (priv->chip->hw_thermal_shutdown) 623 val = clamp_val(val, 0, 1000); 624 625 idx = find_closest_descending(val, mcp9982_update_interval, 626 ARRAY_SIZE(mcp9982_update_interval)); 627 priv->interval_idx = idx; 628 629 return regmap_write(priv->regmap, MCP9982_CONV_ADDR, idx); 630 default: 631 return -EINVAL; 632 } 633 case hwmon_temp: 634 val = clamp_val(val, -64000, 191875); 635 val = val + (MCP9982_OFFSET * 1000); 636 switch (attr) { 637 case hwmon_temp_max: 638 if (channel) 639 addr = MCP9982_EXT_HIGH_LIMIT_ADDR(channel); 640 else 641 addr = MCP9982_INTERNAL_HIGH_LIMIT_ADDR; 642 643 return mcp9982_write_limit(priv, addr, val); 644 case hwmon_temp_min: 645 if (channel) 646 addr = MCP9982_EXT_LOW_LIMIT_ADDR(channel); 647 else 648 addr = MCP9982_INTERNAL_LOW_LIMIT_ADDR; 649 650 return mcp9982_write_limit(priv, addr, val); 651 case hwmon_temp_crit: 652 return mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(channel), val); 653 case hwmon_temp_crit_hyst: 654 return mcp9982_write_hyst(priv, channel, val); 655 default: 656 return -EINVAL; 657 } 658 default: 659 return -EINVAL; 660 } 661 } 662 663 static umode_t mcp9982_is_visible(const void *_data, enum hwmon_sensor_types type, u32 attr, 664 int channel) 665 { 666 const struct mcp9982_priv *priv = _data; 667 668 if (!test_bit(channel, &priv->enabled_channel_mask)) 669 return 0; 670 671 switch (type) { 672 case hwmon_temp: 673 switch (attr) { 674 case hwmon_temp_label: 675 if (priv->labels[channel]) 676 return 0444; 677 else 678 return 0; 679 case hwmon_temp_input: 680 case hwmon_temp_min_alarm: 681 case hwmon_temp_max_alarm: 682 case hwmon_temp_max_hyst: 683 case hwmon_temp_crit_alarm: 684 return 0444; 685 case hwmon_temp_min: 686 case hwmon_temp_max: 687 case hwmon_temp_crit: 688 case hwmon_temp_crit_hyst: 689 return 0644; 690 default: 691 return 0; 692 } 693 case hwmon_chip: 694 switch (attr) { 695 case hwmon_chip_update_interval: 696 return 0644; 697 default: 698 return 0; 699 } 700 default: 701 return 0; 702 } 703 } 704 705 static const struct hwmon_ops mcp9982_hwmon_ops = { 706 .is_visible = mcp9982_is_visible, 707 .read = mcp9982_read, 708 .read_string = mcp9982_read_label, 709 .write = mcp9982_write, 710 }; 711 712 static int mcp9982_init(struct device *dev, struct mcp9982_priv *priv) 713 { 714 long high_limit, low_limit; 715 unsigned int i; 716 int ret; 717 u8 val; 718 719 /* Chips 82/83 and 82D/83D do not support anti-parallel diode mode. */ 720 if (!priv->chip->allow_apdd && priv->apdd_enable == 1) 721 return dev_err_probe(dev, -EINVAL, "Incorrect setting of APDD.\n"); 722 723 /* Chips with "D" work only in Run state. */ 724 if (priv->chip->hw_thermal_shutdown && !priv->run_state) 725 return dev_err_probe(dev, -EINVAL, "Incorrect setting of Power State.\n"); 726 727 /* All chips with "D" in the name must have RECD12 enabled. */ 728 if (priv->chip->hw_thermal_shutdown && !priv->recd12_enable) 729 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD12.\n"); 730 /* Chips 83D/84D/85D must have RECD34 enabled. */ 731 if (priv->chip->hw_thermal_shutdown) 732 if ((priv->chip->has_recd34 && !priv->recd34_enable)) 733 return dev_err_probe(dev, -EINVAL, "Incorrect setting of RECD34.\n"); 734 735 /* 736 * Set default values in registers. 737 * APDD, RECD12 and RECD34 are active on 0. 738 */ 739 val = FIELD_PREP(MCP9982_CFG_MSKAL, 1) | 740 FIELD_PREP(MCP9982_CFG_RS, !priv->run_state) | 741 FIELD_PREP(MCP9982_CFG_ATTHM, 1) | 742 FIELD_PREP(MCP9982_CFG_RECD12, !priv->recd12_enable) | 743 FIELD_PREP(MCP9982_CFG_RECD34, !priv->recd34_enable) | 744 FIELD_PREP(MCP9982_CFG_RANGE, 1) | FIELD_PREP(MCP9982_CFG_DA_ENA, 0) | 745 FIELD_PREP(MCP9982_CFG_APDD, !priv->apdd_enable); 746 747 ret = regmap_write(priv->regmap, MCP9982_CFG_ADDR, val); 748 if (ret) 749 return ret; 750 751 /* 752 * Read initial value from register. 753 * The convert register utilises only 4 out of 8 bits. 754 * Numerical values 0->10 set their respective update intervals, 755 * while numerical values 11->15 default to 1 second. 756 */ 757 ret = regmap_read(priv->regmap, MCP9982_CONV_ADDR, &priv->interval_idx); 758 if (ret) 759 return ret; 760 if (priv->interval_idx >= 11) 761 priv->interval_idx = 4; 762 763 ret = regmap_write(priv->regmap, MCP9982_HYS_ADDR, MCP9982_DEFAULT_HYS_VAL); 764 if (ret) 765 return ret; 766 767 ret = regmap_write(priv->regmap, MCP9982_CONSEC_ALRT_ADDR, MCP9982_DEFAULT_CONSEC_ALRT_VAL); 768 if (ret) 769 return ret; 770 771 ret = regmap_write(priv->regmap, MCP9982_ALRT_CFG_ADDR, 0); 772 if (ret) 773 return ret; 774 775 ret = regmap_write(priv->regmap, MCP9982_RUNNING_AVG_ADDR, 0); 776 if (ret) 777 return ret; 778 779 ret = regmap_write(priv->regmap, MCP9982_HOTTEST_CFG_ADDR, 0); 780 if (ret) 781 return ret; 782 783 /* 784 * Only external channels 1 and 2 support beta compensation. 785 * Set beta auto-detection. 786 */ 787 for (i = 1; i < 3; i++) 788 if (test_bit(i, &priv->enabled_channel_mask)) { 789 ret = regmap_write(priv->regmap, MCP9982_EXT_BETA_CFG_ADDR(i), 790 MCP9982_BETA_AUTODETECT); 791 if (ret) 792 return ret; 793 } 794 795 high_limit = MCP9982_HIGH_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000); 796 low_limit = MCP9982_LOW_LIMIT_DEFAULT + (MCP9982_OFFSET * 1000); 797 798 /* Set default values for internal channel limits. */ 799 if (test_bit(0, &priv->enabled_channel_mask)) { 800 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_HIGH_LIMIT_ADDR, high_limit); 801 if (ret) 802 return ret; 803 804 ret = mcp9982_write_limit(priv, MCP9982_INTERNAL_LOW_LIMIT_ADDR, low_limit); 805 if (ret) 806 return ret; 807 808 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(0), high_limit); 809 if (ret) 810 return ret; 811 } 812 813 /* Set ideality factor and limits to default for external channels. */ 814 for (i = 1; i < MCP9982_MAX_NUM_CHANNELS; i++) 815 if (test_bit(i, &priv->enabled_channel_mask)) { 816 ret = regmap_write(priv->regmap, MCP9982_EXT_IDEAL_ADDR(i), 817 MCP9982_IDEALITY_DEFAULT); 818 if (ret) 819 return ret; 820 821 ret = mcp9982_write_limit(priv, MCP9982_EXT_HIGH_LIMIT_ADDR(i), high_limit); 822 if (ret) 823 return ret; 824 825 ret = mcp9982_write_limit(priv, MCP9982_EXT_LOW_LIMIT_ADDR(i), low_limit); 826 if (ret) 827 return ret; 828 829 ret = mcp9982_write_limit(priv, MCP9982_THERM_LIMIT_ADDR(i), high_limit); 830 if (ret) 831 return ret; 832 } 833 834 return 0; 835 } 836 837 static int mcp9982_parse_fw_config(struct device *dev, int device_nr_channels) 838 { 839 struct mcp9982_priv *priv = dev_get_drvdata(dev); 840 unsigned int reg_nr; 841 int ret; 842 843 /* Initialise internal channel( which is always present ). */ 844 priv->labels[0] = "internal diode"; 845 priv->enabled_channel_mask = 1; 846 847 /* Default values to work on systems without devicetree or firmware nodes. */ 848 if (!dev_fwnode(dev)) { 849 priv->num_channels = device_nr_channels; 850 priv->enabled_channel_mask = BIT(priv->num_channels) - 1; 851 priv->apdd_enable = false; 852 priv->recd12_enable = true; 853 priv->recd34_enable = true; 854 priv->run_state = true; 855 return 0; 856 } 857 858 priv->apdd_enable = 859 device_property_read_bool(dev, "microchip,enable-anti-parallel"); 860 861 priv->recd12_enable = 862 device_property_read_bool(dev, "microchip,parasitic-res-on-channel1-2"); 863 864 priv->recd34_enable = 865 device_property_read_bool(dev, "microchip,parasitic-res-on-channel3-4"); 866 867 priv->run_state = 868 device_property_read_bool(dev, "microchip,power-state"); 869 870 priv->num_channels = device_get_child_node_count(dev) + 1; 871 872 if (priv->num_channels > device_nr_channels) 873 return dev_err_probe(dev, -EINVAL, 874 "More channels than the chip supports.\n"); 875 876 /* Read information about the external channels. */ 877 device_for_each_named_child_node_scoped(dev, child, "channel") { 878 reg_nr = 0; 879 ret = fwnode_property_read_u32(child, "reg", ®_nr); 880 if (ret || !reg_nr || reg_nr >= device_nr_channels) 881 return dev_err_probe(dev, -EINVAL, 882 "Channel reg is incorrectly set.\n"); 883 884 fwnode_property_read_string(child, "label", &priv->labels[reg_nr]); 885 set_bit(reg_nr, &priv->enabled_channel_mask); 886 } 887 888 return 0; 889 } 890 891 static const struct hwmon_chip_info mcp998x_chip_info = { 892 .ops = &mcp9982_hwmon_ops, 893 .info = mcp9985_info, 894 }; 895 896 static int mcp9982_probe(struct i2c_client *client) 897 { 898 const struct mcp9982_features *chip; 899 struct device *dev = &client->dev; 900 struct mcp9982_priv *priv; 901 struct device *hwmon_dev; 902 int ret; 903 904 priv = devm_kzalloc(dev, sizeof(struct mcp9982_priv), GFP_KERNEL); 905 if (!priv) 906 return -ENOMEM; 907 908 priv->regmap = devm_regmap_init_i2c(client, &mcp9982_regmap_config); 909 910 if (IS_ERR(priv->regmap)) 911 return dev_err_probe(dev, PTR_ERR(priv->regmap), 912 "Cannot initialize register map.\n"); 913 914 dev_set_drvdata(dev, priv); 915 916 chip = i2c_get_match_data(client); 917 if (!chip) 918 return -EINVAL; 919 priv->chip = chip; 920 921 ret = mcp9982_parse_fw_config(dev, chip->phys_channels); 922 if (ret) 923 return ret; 924 925 ret = mcp9982_init(dev, priv); 926 if (ret) 927 return ret; 928 929 hwmon_dev = devm_hwmon_device_register_with_info(dev, chip->name, priv, 930 &mcp998x_chip_info, NULL); 931 932 return PTR_ERR_OR_ZERO(hwmon_dev); 933 } 934 935 static const struct i2c_device_id mcp9982_id[] = { 936 { .name = "mcp9933", .driver_data = (kernel_ulong_t)&mcp9933_chip_config }, 937 { .name = "mcp9933d", .driver_data = (kernel_ulong_t)&mcp9933d_chip_config }, 938 { .name = "mcp9982", .driver_data = (kernel_ulong_t)&mcp9982_chip_config }, 939 { .name = "mcp9982d", .driver_data = (kernel_ulong_t)&mcp9982d_chip_config }, 940 { .name = "mcp9983", .driver_data = (kernel_ulong_t)&mcp9983_chip_config }, 941 { .name = "mcp9983d", .driver_data = (kernel_ulong_t)&mcp9983d_chip_config }, 942 { .name = "mcp9984", .driver_data = (kernel_ulong_t)&mcp9984_chip_config }, 943 { .name = "mcp9984d", .driver_data = (kernel_ulong_t)&mcp9984d_chip_config }, 944 { .name = "mcp9985", .driver_data = (kernel_ulong_t)&mcp9985_chip_config }, 945 { .name = "mcp9985d", .driver_data = (kernel_ulong_t)&mcp9985d_chip_config }, 946 { } 947 }; 948 MODULE_DEVICE_TABLE(i2c, mcp9982_id); 949 950 static const struct of_device_id mcp9982_of_match[] = { 951 { 952 .compatible = "microchip,mcp9933", 953 .data = &mcp9933_chip_config, 954 }, { 955 .compatible = "microchip,mcp9933d", 956 .data = &mcp9933d_chip_config, 957 }, { 958 .compatible = "microchip,mcp9982", 959 .data = &mcp9982_chip_config, 960 }, { 961 .compatible = "microchip,mcp9982d", 962 .data = &mcp9982d_chip_config, 963 }, { 964 .compatible = "microchip,mcp9983", 965 .data = &mcp9983_chip_config, 966 }, { 967 .compatible = "microchip,mcp9983d", 968 .data = &mcp9983d_chip_config, 969 }, { 970 .compatible = "microchip,mcp9984", 971 .data = &mcp9984_chip_config, 972 }, { 973 .compatible = "microchip,mcp9984d", 974 .data = &mcp9984d_chip_config, 975 }, { 976 .compatible = "microchip,mcp9985", 977 .data = &mcp9985_chip_config, 978 }, { 979 .compatible = "microchip,mcp9985d", 980 .data = &mcp9985d_chip_config, 981 }, 982 { } 983 }; 984 MODULE_DEVICE_TABLE(of, mcp9982_of_match); 985 986 static struct i2c_driver mcp9982_driver = { 987 .driver = { 988 .name = "mcp9982", 989 .of_match_table = mcp9982_of_match, 990 }, 991 .probe = mcp9982_probe, 992 .id_table = mcp9982_id, 993 }; 994 module_i2c_driver(mcp9982_driver); 995 996 MODULE_AUTHOR("Victor Duicu <victor.duicu@microchip.com>"); 997 MODULE_DESCRIPTION("MCP998X/33 and MCP998XD/33D Multichannel Automotive Temperature Monitor Driver"); 998 MODULE_LICENSE("GPL"); 999