1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller (HWMON) 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 #include <linux/auxiliary_bus.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bits.h> 12 13 #include <linux/debugfs.h> 14 #include <linux/device.h> 15 #include <linux/device/devres.h> 16 #include <linux/hwmon.h> 17 #include <linux/i2c.h> 18 #include <linux/math.h> 19 #include <linux/math64.h> 20 #include <linux/minmax.h> 21 #include <linux/module.h> 22 23 #include <linux/property.h> 24 #include <linux/regmap.h> 25 #include <linux/unaligned.h> 26 #include <linux/units.h> 27 28 #define LTC4283_SYSTEM_STATUS 0x00 29 #define LTC4283_FAULT_STATUS 0x03 30 #define LTC4283_OV_MASK BIT(0) 31 #define LTC4283_UV_MASK BIT(1) 32 #define LTC4283_OC_MASK BIT(2) 33 #define LTC4283_FET_BAD_MASK BIT(3) 34 #define LTC4283_FET_SHORT_MASK BIT(6) 35 #define LTC4283_FAULT_LOG 0x04 36 #define LTC4283_OV_FAULT_MASK BIT(0) 37 #define LTC4283_UV_FAULT_MASK BIT(1) 38 #define LTC4283_OC_FAULT_MASK BIT(2) 39 #define LTC4283_FET_BAD_FAULT_MASK BIT(3) 40 #define LTC4283_PGI_FAULT_MASK BIT(4) 41 #define LTC4283_PWR_FAIL_FAULT_MASK BIT(5) 42 #define LTC4283_FET_SHORT_FAULT_MASK BIT(6) 43 #define LTC4283_ADC_ALM_LOG_1 0x05 44 #define LTC4283_POWER_LOW_ALM BIT(0) 45 #define LTC4283_POWER_HIGH_ALM BIT(1) 46 #define LTC4283_SENSE_LOW_ALM BIT(4) 47 #define LTC4283_SENSE_HIGH_ALM BIT(5) 48 #define LTC4283_ADC_ALM_LOG_2 0x06 49 #define LTC4283_ADC_ALM_LOG_3 0x07 50 #define LTC4283_ADC_ALM_LOG_4 0x08 51 #define LTC4283_ADC_ALM_LOG_5 0x09 52 #define LTC4283_CONTROL_1 0x0a 53 #define LTC4283_RW_PAGE_MASK BIT(0) 54 #define LTC4283_PIGIO2_ACLB_MASK BIT(2) 55 #define LTC4283_PWRGD_RST_CTRL_MASK BIT(3) 56 #define LTC4283_FET_BAD_OFF_MASK BIT(4) 57 #define LTC4283_THERM_TMR_MASK BIT(5) 58 #define LTC4283_DVDT_MASK BIT(6) 59 #define LTC4283_CONTROL_2 0x0b 60 #define LTC4283_OV_RETRY_MASK BIT(0) 61 #define LTC4283_UV_RETRY_MASK BIT(1) 62 #define LTC4283_OC_RETRY_MASK GENMASK(3, 2) 63 #define LTC4283_FET_BAD_RETRY_MASK GENMASK(5, 4) 64 #define LTC4283_EXT_FAULT_RETRY_MASK BIT(7) 65 #define LTC4283_RESERVED_OC 0x0c 66 #define LTC4283_CONFIG_1 0x0d 67 #define LTC4283_FB_MASK GENMASK(3, 2) 68 #define LTC4283_ILIM_MASK GENMASK(7, 4) 69 #define LTC4283_CONFIG_2 0x0e 70 #define LTC4283_COOLING_DL_MASK GENMASK(3, 1) 71 #define LTC4283_FTBD_DL_MASK GENMASK(5, 4) 72 #define LTC4283_CONFIG_3 0x0f 73 #define LTC4283_VPWR_DRNS_MASK BIT(6) 74 #define LTC4283_EXTFLT_TURN_OFF_MASK BIT(7) 75 #define LTC4283_PGIO_CONFIG 0x10 76 #define LTC4283_PGIO1_CFG_MASK GENMASK(1, 0) 77 #define LTC4283_PGIO2_CFG_MASK GENMASK(3, 2) 78 #define LTC4283_PGIO3_CFG_MASK GENMASK(5, 4) 79 #define LTC4283_PGIO4_CFG_MASK GENMASK(7, 6) 80 #define LTC4283_PGIO_CONFIG_2 0x11 81 #define LTC4283_ADC_MASK GENMASK(2, 0) 82 #define LTC4283_ADC_SELECT(c) (0x13 + (c) / 8) 83 #define LTC4283_ADC_SELECT_MASK(c) BIT((c) % 8) 84 #define LTC4283_SENSE_MIN_TH 0x1b 85 #define LTC4283_SENSE_MAX_TH 0x1c 86 #define LTC4283_VPWR_MIN_TH 0x1d 87 #define LTC4283_VPWR_MAX_TH 0x1e 88 #define LTC4283_POWER_MIN_TH 0x1f 89 #define LTC4283_POWER_MAX_TH 0x20 90 #define LTC4283_ADC_2_MIN_TH(c) (0x21 + (c) * 2) 91 #define LTC4283_ADC_2_MAX_TH(c) (0x22 + (c) * 2) 92 #define LTC4283_ADC_2_MIN_TH_DIFF(c) (0x39 + (c) * 2) 93 #define LTC4283_ADC_2_MAX_TH_DIFF(c) (0x3a + (c) * 2) 94 #define LTC4283_SENSE 0x41 95 #define LTC4283_SENSE_MIN 0x42 96 #define LTC4283_SENSE_MAX 0x43 97 #define LTC4283_VPWR 0x44 98 #define LTC4283_VPWR_MIN 0x45 99 #define LTC4283_VPWR_MAX 0x46 100 #define LTC4283_POWER 0x47 101 #define LTC4283_POWER_MIN 0x48 102 #define LTC4283_POWER_MAX 0x49 103 #define LTC4283_RESERVED_68 0x68 104 #define LTC4283_RESERVED_6D 0x6D 105 /* get channels from ADC 2 */ 106 #define LTC4283_ADC_2(c) (0x4a + (c) * 3) 107 #define LTC4283_ADC_2_MIN(c) (0x4b + (c) * 3) 108 #define LTC4283_ADC_2_MAX(c) (0x4c + (c) * 3) 109 #define LTC4283_ADC_2_DIFF(c) (0x6e + (c) * 3) 110 #define LTC4283_ADC_2_MIN_DIFF(c) (0x6f + (c) * 3) 111 #define LTC4283_ADC_2_MAX_DIFF(c) (0x70 + (c) * 3) 112 #define LTC4283_ENERGY 0x7a 113 #define LTC4283_METER_CONTROL 0x84 114 #define LTC4283_INTEGRATE_I_MASK BIT(0) 115 #define LTC4283_METER_HALT_MASK BIT(6) 116 #define LTC4283_RESERVED_86 0x86 117 #define LTC4283_RESERVED_8F 0x8F 118 #define LTC4283_FAULT_LOG_CTRL 0x90 119 #define LTC4283_FAULT_LOG_EN_MASK BIT(7) 120 #define LTC4283_RESERVED_91 0x91 121 #define LTC4283_RESERVED_A1 0xA1 122 #define LTC4283_RESERVED_A3 0xA3 123 #define LTC4283_RESERVED_AC 0xAC 124 #define LTC4283_POWER_PLAY_MSB 0xE7 125 #define LTC4283_POWER_PLAY_LSB 0xE8 126 #define LTC4283_RESERVED_F1 0xF1 127 #define LTC4283_RESERVED_FF 0xFF 128 129 /* also applies for differential channels */ 130 #define LTC4283_ADC1_FS_uV 32768 131 #define LTC4283_ADC2_FS_mV 2048 132 #define LTC4283_TCONV_uS 64103 133 #define LTC4283_VILIM_MIN_uV 15000 134 #define LTC4283_VILIM_MAX_uV 30000 135 #define LTC4283_VILIM_RANGE \ 136 (LTC4283_VILIM_MAX_uV - LTC4283_VILIM_MIN_uV + 1) 137 138 #define LTC4283_PGIO_FUNC_GPIO 2 139 #define LTC4283_PGIO2_FUNC_ACLB 3 140 141 /* 142 * Maximum value for rsense in nano ohms. The reasoning for this value is that 143 * it's the max value for which multiplying by 256 does not overflow long on 144 * 32bits. For the minimum value, is a sane minimum rsense for which power_max 145 * does not overflow 32bits. 146 */ 147 #define LTC4283_MAX_RSENSE 1677721599 148 #define LTC4283_MIN_RSENSE 50000 149 150 /* voltage channels */ 151 enum { 152 LTC4283_CHAN_VIN, 153 LTC4283_CHAN_VPWR, 154 LTC4283_CHAN_ADI_1, 155 LTC4283_CHAN_ADI_2, 156 LTC4283_CHAN_ADI_3, 157 LTC4283_CHAN_ADI_4, 158 LTC4283_CHAN_ADIO_1, 159 LTC4283_CHAN_ADIO_2, 160 LTC4283_CHAN_ADIO_3, 161 LTC4283_CHAN_ADIO_4, 162 LTC4283_CHAN_DRNS, 163 LTC4283_CHAN_DRAIN, 164 /* differential channels */ 165 LTC4283_CHAN_ADIN12, 166 LTC4283_CHAN_ADIN34, 167 LTC4283_CHAN_ADIO12, 168 LTC4283_CHAN_ADIO34, 169 LTC4283_CHAN_MAX 170 }; 171 172 /* Just for ease of use on the regmap */ 173 #define LTC4283_ADIO34_MAX \ 174 LTC4283_ADC_2_MAX_DIFF(LTC4283_CHAN_ADIO34 - LTC4283_CHAN_ADIN12) 175 176 struct ltc4283_hwmon { 177 struct regmap *map; 178 struct i2c_client *client; 179 unsigned long gpio_mask; 180 unsigned long ch_enable_mask; 181 /* in microwatt */ 182 unsigned long power_max; 183 /* in millivolt */ 184 u32 vsense_max; 185 /* in tenths of microohm*/ 186 u32 rsense; 187 bool energy_en; 188 bool ext_fault; 189 }; 190 191 static int ltc4283_read_voltage_word(const struct ltc4283_hwmon *st, 192 u32 reg, u32 fs, long *val) 193 { 194 unsigned int __raw; 195 int ret; 196 197 ret = regmap_read(st->map, reg, &__raw); 198 if (ret) 199 return ret; 200 201 *val = DIV_ROUND_CLOSEST(__raw * fs, BIT(16)); 202 return 0; 203 } 204 205 static int ltc4283_read_voltage_byte(const struct ltc4283_hwmon *st, 206 u32 reg, u32 fs, long *val) 207 { 208 int ret; 209 u32 in; 210 211 ret = regmap_read(st->map, reg, &in); 212 if (ret) 213 return ret; 214 215 *val = DIV_ROUND_CLOSEST(in * fs, BIT(8)); 216 return 0; 217 } 218 219 static u32 ltc4283_in_reg(u32 attr, u32 channel) 220 { 221 switch (attr) { 222 case hwmon_in_input: 223 if (channel == LTC4283_CHAN_VPWR) 224 return LTC4283_VPWR; 225 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 226 return LTC4283_ADC_2(channel - LTC4283_CHAN_ADI_1); 227 return LTC4283_ADC_2_DIFF(channel - LTC4283_CHAN_ADIN12); 228 case hwmon_in_highest: 229 if (channel == LTC4283_CHAN_VPWR) 230 return LTC4283_VPWR_MAX; 231 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 232 return LTC4283_ADC_2_MAX(channel - LTC4283_CHAN_ADI_1); 233 return LTC4283_ADC_2_MAX_DIFF(channel - LTC4283_CHAN_ADIN12); 234 case hwmon_in_lowest: 235 if (channel == LTC4283_CHAN_VPWR) 236 return LTC4283_VPWR_MIN; 237 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 238 return LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1); 239 return LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12); 240 case hwmon_in_max: 241 if (channel == LTC4283_CHAN_VPWR) 242 return LTC4283_VPWR_MAX_TH; 243 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 244 return LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1); 245 return LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 246 default: 247 if (channel == LTC4283_CHAN_VPWR) 248 return LTC4283_VPWR_MIN_TH; 249 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 250 return LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1); 251 return LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 252 } 253 } 254 255 static int ltc4283_read_in_vals(const struct ltc4283_hwmon *st, 256 u32 attr, u32 channel, long *val) 257 { 258 u32 reg = ltc4283_in_reg(attr, channel); 259 int ret; 260 261 if (channel < LTC4283_CHAN_ADIN12) { 262 if (attr != hwmon_in_max && attr != hwmon_in_min) 263 return ltc4283_read_voltage_word(st, reg, 264 LTC4283_ADC2_FS_mV, 265 val); 266 267 return ltc4283_read_voltage_byte(st, reg, 268 LTC4283_ADC2_FS_mV, val); 269 } 270 271 if (attr != hwmon_in_max && attr != hwmon_in_min) 272 ret = ltc4283_read_voltage_word(st, reg, 273 LTC4283_ADC1_FS_uV, val); 274 else 275 ret = ltc4283_read_voltage_byte(st, reg, 276 LTC4283_ADC1_FS_uV, val); 277 if (ret) 278 return ret; 279 280 *val = DIV_ROUND_CLOSEST(*val, MILLI); 281 return 0; 282 } 283 284 static int ltc4283_read_alarm(struct ltc4283_hwmon *st, u32 reg, 285 u32 mask, long *val) 286 { 287 u32 alarm; 288 int ret; 289 290 ret = regmap_read(st->map, reg, &alarm); 291 if (ret) 292 return ret; 293 294 *val = !!(alarm & mask); 295 296 /* If not status/fault logs, clear the alarm after reading it. */ 297 if (reg != LTC4283_FAULT_STATUS && reg != LTC4283_FAULT_LOG) 298 return regmap_write(st->map, reg, alarm & ~mask); 299 300 return 0; 301 } 302 303 static int ltc4283_read_in_alarm(struct ltc4283_hwmon *st, u32 channel, 304 bool max_alm, long *val) 305 { 306 if (channel == LTC4283_CHAN_VPWR) 307 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 308 BIT(2 + max_alm), val); 309 310 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_ADI_4) { 311 u32 bit = (channel - LTC4283_CHAN_ADI_1) * 2; 312 /* 313 * Lower channels go to higher bits. We also want to go +1 down 314 * in the min_alarm case. 315 */ 316 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_2, 317 BIT(7 - bit - !max_alm), val); 318 } 319 320 if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) { 321 u32 bit = (channel - LTC4283_CHAN_ADIO_1) * 2; 322 323 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_3, 324 BIT(7 - bit - !max_alm), val); 325 } 326 327 if (channel >= LTC4283_CHAN_ADIN12 && channel <= LTC4283_CHAN_ADIO34) { 328 u32 bit = (channel - LTC4283_CHAN_ADIN12) * 2; 329 330 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_5, 331 BIT(7 - bit - !max_alm), val); 332 } 333 334 if (channel == LTC4283_CHAN_DRNS) 335 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, 336 BIT(6 + max_alm), val); 337 338 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, BIT(4 + max_alm), 339 val); 340 } 341 342 static int ltc4283_read_in(struct ltc4283_hwmon *st, u32 attr, u32 channel, 343 long *val) 344 { 345 switch (attr) { 346 case hwmon_in_input: 347 if (!test_bit(channel, &st->ch_enable_mask)) 348 return -ENODATA; 349 350 return ltc4283_read_in_vals(st, attr, channel, val); 351 case hwmon_in_highest: 352 case hwmon_in_lowest: 353 case hwmon_in_max: 354 case hwmon_in_min: 355 return ltc4283_read_in_vals(st, attr, channel, val); 356 case hwmon_in_max_alarm: 357 return ltc4283_read_in_alarm(st, channel, true, val); 358 case hwmon_in_min_alarm: 359 return ltc4283_read_in_alarm(st, channel, false, val); 360 case hwmon_in_crit_alarm: 361 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 362 LTC4283_OV_MASK, val); 363 case hwmon_in_lcrit_alarm: 364 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 365 LTC4283_UV_MASK, val); 366 case hwmon_in_fault: 367 /* 368 * We report failure if we detect either a fer_bad or a 369 * fet_short in the status register. 370 */ 371 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 372 LTC4283_FET_BAD_MASK | LTC4283_FET_SHORT_MASK, val); 373 case hwmon_in_enable: 374 *val = test_bit(channel, &st->ch_enable_mask); 375 return 0; 376 default: 377 return -EOPNOTSUPP; 378 } 379 return 0; 380 } 381 382 static int ltc4283_read_current_word(const struct ltc4283_hwmon *st, u32 reg, 383 long *val) 384 { 385 u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; 386 unsigned int __raw; 387 int ret; 388 389 ret = regmap_read(st->map, reg, &__raw); 390 if (ret) 391 return ret; 392 393 *val = DIV64_U64_ROUND_CLOSEST(__raw * temp, 394 BIT_ULL(16) * st->rsense); 395 396 return 0; 397 } 398 399 static int ltc4283_read_current_byte(const struct ltc4283_hwmon *st, u32 reg, 400 long *val) 401 { 402 u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; 403 u32 curr; 404 int ret; 405 406 ret = regmap_read(st->map, reg, &curr); 407 if (ret) 408 return ret; 409 410 *val = DIV_ROUND_CLOSEST_ULL(curr * temp, BIT(8) * st->rsense); 411 return 0; 412 } 413 414 static int ltc4283_read_curr(struct ltc4283_hwmon *st, u32 attr, long *val) 415 { 416 switch (attr) { 417 case hwmon_curr_input: 418 return ltc4283_read_current_word(st, LTC4283_SENSE, val); 419 case hwmon_curr_highest: 420 return ltc4283_read_current_word(st, LTC4283_SENSE_MAX, val); 421 case hwmon_curr_lowest: 422 return ltc4283_read_current_word(st, LTC4283_SENSE_MIN, val); 423 case hwmon_curr_max: 424 return ltc4283_read_current_byte(st, LTC4283_SENSE_MAX_TH, val); 425 case hwmon_curr_min: 426 return ltc4283_read_current_byte(st, LTC4283_SENSE_MIN_TH, val); 427 case hwmon_curr_max_alarm: 428 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 429 LTC4283_SENSE_HIGH_ALM, val); 430 case hwmon_curr_min_alarm: 431 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 432 LTC4283_SENSE_LOW_ALM, val); 433 case hwmon_curr_crit_alarm: 434 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 435 LTC4283_OC_MASK, val); 436 default: 437 return -EOPNOTSUPP; 438 } 439 } 440 441 static int ltc4283_read_power_word(const struct ltc4283_hwmon *st, 442 u32 reg, long *val) 443 { 444 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 445 unsigned int __raw; 446 int ret; 447 448 ret = regmap_read(st->map, reg, &__raw); 449 if (ret) 450 return ret; 451 452 /* 453 * Power is given by: 454 * P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense) 455 */ 456 *val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense); 457 458 return 0; 459 } 460 461 static int ltc4283_read_power_byte(const struct ltc4283_hwmon *st, 462 u32 reg, long *val) 463 { 464 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 465 u32 power; 466 int ret; 467 468 ret = regmap_read(st->map, reg, &power); 469 if (ret) 470 return ret; 471 472 *val = DIV_ROUND_CLOSEST_ULL(power * temp, BIT(8) * st->rsense); 473 474 return 0; 475 } 476 477 static int ltc4283_read_power(struct ltc4283_hwmon *st, u32 attr, long *val) 478 { 479 switch (attr) { 480 case hwmon_power_input: 481 return ltc4283_read_power_word(st, LTC4283_POWER, val); 482 case hwmon_power_input_highest: 483 return ltc4283_read_power_word(st, LTC4283_POWER_MAX, val); 484 case hwmon_power_input_lowest: 485 return ltc4283_read_power_word(st, LTC4283_POWER_MIN, val); 486 case hwmon_power_max_alarm: 487 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 488 LTC4283_POWER_HIGH_ALM, val); 489 case hwmon_power_min_alarm: 490 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 491 LTC4283_POWER_LOW_ALM, val); 492 case hwmon_power_max: 493 return ltc4283_read_power_byte(st, LTC4283_POWER_MAX_TH, val); 494 case hwmon_power_min: 495 return ltc4283_read_power_byte(st, LTC4283_POWER_MIN_TH, val); 496 default: 497 return -EOPNOTSUPP; 498 } 499 } 500 501 static int ltc4283_read_energy(struct ltc4283_hwmon *st, u32 attr, s64 *val) 502 { 503 u64 temp = LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV, energy; 504 u8 raw[8] = {}; 505 int ret; 506 507 if (!st->energy_en) 508 return -ENODATA; 509 510 ret = i2c_smbus_read_i2c_block_data(st->client, LTC4283_ENERGY, 6, raw); 511 if (ret < 0) 512 return ret; 513 if (ret != 6) 514 return -EIO; 515 516 energy = get_unaligned_be64(raw) >> 16; 517 518 /* 519 * The formula for energy is given by: 520 * E = CODE(48b) * 32.768mV * 2.048V * Tconv / 2^24 * Rsense 521 * 522 * As Rsense can have tenths of micro-ohm resolution, we need to 523 * multiply by DECA to get microjoule. 524 */ 525 526 /* 527 * Use mul_u64_u64_div_u64() to handle the 128-bit intermediate 528 * product of energy (up to 48 bits) * temp * Tconv without overflow. 529 * Multiply rsense by CENTI to convert from tenths-of-microohm back 530 * to nanoohm so the result comes out in microjoule. 531 */ 532 energy = mul_u64_u64_div_u64(energy, temp * LTC4283_TCONV_uS, 533 BIT_ULL(24) * st->rsense * CENTI); 534 535 *val = energy; 536 return 0; 537 } 538 539 static int ltc4283_read(struct device *dev, enum hwmon_sensor_types type, 540 u32 attr, int channel, long *val) 541 { 542 struct ltc4283_hwmon *st = dev_get_drvdata(dev); 543 544 switch (type) { 545 case hwmon_in: 546 return ltc4283_read_in(st, attr, channel, val); 547 case hwmon_curr: 548 return ltc4283_read_curr(st, attr, val); 549 case hwmon_power: 550 return ltc4283_read_power(st, attr, val); 551 case hwmon_energy: 552 *val = st->energy_en; 553 return 0; 554 case hwmon_energy64: 555 return ltc4283_read_energy(st, attr, (s64 *)val); 556 default: 557 return -EOPNOTSUPP; 558 } 559 } 560 561 static int ltc4283_write_power_byte(const struct ltc4283_hwmon *st, u32 reg, 562 long val) 563 { 564 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 565 u32 __raw; 566 567 val = clamp_val(val, 0, st->power_max); 568 __raw = DIV64_U64_ROUND_CLOSEST(val * BIT_ULL(8) * st->rsense, temp); 569 570 return regmap_write(st->map, reg, __raw); 571 } 572 573 static int ltc4283_write_power_word(const struct ltc4283_hwmon *st, 574 u32 reg, unsigned long val) 575 { 576 u64 divisor = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 577 u16 __raw; 578 579 __raw = mul_u64_u64_div_u64(val, st->rsense * BIT_ULL(16), divisor); 580 581 return regmap_write(st->map, reg, __raw); 582 } 583 584 static int ltc4283_reset_power_hist(struct ltc4283_hwmon *st) 585 { 586 int ret; 587 588 ret = ltc4283_write_power_word(st, LTC4283_POWER_MIN, st->power_max); 589 if (ret) 590 return ret; 591 592 ret = ltc4283_write_power_word(st, LTC4283_POWER_MAX, 0); 593 if (ret) 594 return ret; 595 596 /* Clear possible power faults. */ 597 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 598 LTC4283_PWR_FAIL_FAULT_MASK | LTC4283_PGI_FAULT_MASK); 599 } 600 601 static int ltc4283_write_power(struct ltc4283_hwmon *st, u32 attr, long val) 602 { 603 switch (attr) { 604 case hwmon_power_max: 605 return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, val); 606 case hwmon_power_min: 607 return ltc4283_write_power_byte(st, LTC4283_POWER_MIN_TH, val); 608 case hwmon_power_reset_history: 609 return ltc4283_reset_power_hist(st); 610 default: 611 return -EOPNOTSUPP; 612 } 613 } 614 615 static int ltc4283_write_in_history(struct ltc4283_hwmon *st, u32 reg, 616 long lowest, u32 fs) 617 { 618 u32 __raw; 619 int ret; 620 621 __raw = DIV_ROUND_CLOSEST(BIT(16) * lowest, fs); 622 if (__raw == BIT(16)) 623 __raw = U16_MAX; 624 625 ret = regmap_write(st->map, reg, __raw); 626 if (ret) 627 return ret; 628 629 return regmap_write(st->map, reg + 1, 0); 630 } 631 632 static int ltc4283_write_in_byte(const struct ltc4283_hwmon *st, 633 u32 reg, u32 fs, long val) 634 { 635 u32 __raw; 636 637 val = clamp_val(val, 0, fs); 638 __raw = DIV_ROUND_CLOSEST(val * BIT(8), fs); 639 if (__raw == BIT(8)) 640 __raw = U8_MAX; 641 642 return regmap_write(st->map, reg, __raw); 643 } 644 645 static int ltc4283_reset_in_hist(struct ltc4283_hwmon *st, u32 channel) 646 { 647 u32 reg, fs; 648 int ret; 649 650 /* 651 * Make sure to clear possible under/over voltage faults. Otherwise the 652 * chip won't latch on again. 653 */ 654 if (channel == LTC4283_CHAN_VIN) 655 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 656 LTC4283_OV_FAULT_MASK | LTC4283_UV_FAULT_MASK); 657 658 if (channel == LTC4283_CHAN_VPWR) 659 return ltc4283_write_in_history(st, LTC4283_VPWR_MIN, 660 LTC4283_ADC2_FS_mV, 661 LTC4283_ADC2_FS_mV); 662 663 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) { 664 fs = LTC4283_ADC2_FS_mV; 665 reg = LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1); 666 } else { 667 fs = LTC4283_ADC1_FS_uV; 668 reg = LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12); 669 } 670 671 ret = ltc4283_write_in_history(st, reg, fs, fs); 672 if (ret) 673 return ret; 674 if (channel != LTC4283_CHAN_DRAIN) 675 return 0; 676 677 /* Then, let's also clear possible fet faults. Same as above. */ 678 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 679 LTC4283_FET_BAD_FAULT_MASK | LTC4283_FET_SHORT_FAULT_MASK); 680 } 681 682 static int ltc4283_write_in_en(struct ltc4283_hwmon *st, u32 channel, bool en) 683 { 684 unsigned int bit, adc_idx = channel - LTC4283_CHAN_ADI_1; 685 unsigned int reg = LTC4283_ADC_SELECT(adc_idx); 686 int ret; 687 688 bit = LTC4283_ADC_SELECT_MASK(adc_idx); 689 if (channel > LTC4283_CHAN_DRAIN) 690 /* Account for two reserved fields after DRAIN. */ 691 bit <<= 2; 692 693 if (en) 694 ret = regmap_set_bits(st->map, reg, bit); 695 else 696 ret = regmap_clear_bits(st->map, reg, bit); 697 if (ret) 698 return ret; 699 700 __assign_bit(channel, &st->ch_enable_mask, en); 701 return 0; 702 } 703 704 static int ltc4283_write_minmax(struct ltc4283_hwmon *st, long val, 705 u32 channel, bool is_max) 706 { 707 u32 reg; 708 709 if (channel == LTC4283_CHAN_VPWR) { 710 if (is_max) 711 return ltc4283_write_in_byte(st, LTC4283_VPWR_MAX_TH, 712 LTC4283_ADC2_FS_mV, val); 713 714 return ltc4283_write_in_byte(st, LTC4283_VPWR_MIN_TH, 715 LTC4283_ADC2_FS_mV, val); 716 } 717 718 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) { 719 if (is_max) { 720 reg = LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1); 721 return ltc4283_write_in_byte(st, reg, 722 LTC4283_ADC2_FS_mV, val); 723 } 724 725 reg = LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1); 726 return ltc4283_write_in_byte(st, reg, LTC4283_ADC2_FS_mV, val); 727 } 728 729 /* Clamp before multiplying to avoid overflow on any arch. */ 730 val = clamp_val(val, 0, LONG_MAX / MILLI); 731 732 if (is_max) { 733 reg = LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 734 return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, 735 val * MILLI); 736 } 737 738 reg = LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 739 return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, val * MILLI); 740 } 741 742 static int ltc4283_write_in(struct ltc4283_hwmon *st, u32 attr, long val, 743 int channel) 744 { 745 switch (attr) { 746 case hwmon_in_max: 747 return ltc4283_write_minmax(st, val, channel, true); 748 case hwmon_in_min: 749 return ltc4283_write_minmax(st, val, channel, false); 750 case hwmon_in_reset_history: 751 return ltc4283_reset_in_hist(st, channel); 752 case hwmon_in_enable: 753 return ltc4283_write_in_en(st, channel, !!val); 754 default: 755 return -EOPNOTSUPP; 756 } 757 } 758 759 static int ltc4283_write_curr_byte(const struct ltc4283_hwmon *st, 760 u32 reg, long val) 761 { 762 u32 temp = LTC4283_ADC1_FS_uV * DECA * MILLI; 763 u32 reg_val, isense_max; 764 765 isense_max = DIV_ROUND_CLOSEST(st->vsense_max * MICRO * DECA, st->rsense); 766 val = clamp_val(val, 0, isense_max); 767 reg_val = DIV_ROUND_CLOSEST_ULL(val * BIT_ULL(8) * st->rsense, temp); 768 769 return regmap_write(st->map, reg, reg_val); 770 } 771 772 static int ltc4283_write_curr_history(struct ltc4283_hwmon *st) 773 { 774 int ret; 775 776 ret = ltc4283_write_in_history(st, LTC4283_SENSE_MIN, 777 st->vsense_max * MILLI, 778 LTC4283_ADC1_FS_uV); 779 if (ret) 780 return ret; 781 782 /* Now, let's also clear possible overcurrent logs. */ 783 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 784 LTC4283_OC_FAULT_MASK); 785 } 786 787 static int ltc4283_write_curr(struct ltc4283_hwmon *st, u32 attr, long val) 788 { 789 switch (attr) { 790 case hwmon_curr_max: 791 return ltc4283_write_curr_byte(st, LTC4283_SENSE_MAX_TH, val); 792 case hwmon_curr_min: 793 return ltc4283_write_curr_byte(st, LTC4283_SENSE_MIN_TH, val); 794 case hwmon_curr_reset_history: 795 return ltc4283_write_curr_history(st); 796 default: 797 return -EOPNOTSUPP; 798 } 799 } 800 801 static int ltc4283_energy_enable_set(struct ltc4283_hwmon *st, long val) 802 { 803 int ret; 804 805 /* Setting the bit halts the meter. */ 806 val = !!val; 807 ret = regmap_update_bits(st->map, LTC4283_METER_CONTROL, 808 LTC4283_METER_HALT_MASK, 809 FIELD_PREP(LTC4283_METER_HALT_MASK, !val)); 810 if (ret) 811 return ret; 812 813 st->energy_en = val; 814 815 return 0; 816 } 817 818 static int ltc4283_write(struct device *dev, enum hwmon_sensor_types type, 819 u32 attr, int channel, long val) 820 { 821 struct ltc4283_hwmon *st = dev_get_drvdata(dev); 822 823 switch (type) { 824 case hwmon_power: 825 return ltc4283_write_power(st, attr, val); 826 case hwmon_in: 827 return ltc4283_write_in(st, attr, val, channel); 828 case hwmon_curr: 829 return ltc4283_write_curr(st, attr, val); 830 case hwmon_energy: 831 return ltc4283_energy_enable_set(st, val); 832 default: 833 return -EOPNOTSUPP; 834 } 835 } 836 837 static umode_t ltc4283_in_is_visible(const struct ltc4283_hwmon *st, 838 u32 attr, int channel) 839 { 840 /* If ADIO is set as a GPIO, don´t make it visible. */ 841 if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) { 842 /* ADIOX pins come at index 0 in the gpio mask. */ 843 channel -= LTC4283_CHAN_ADIO_1; 844 if (test_bit(channel, &st->gpio_mask)) 845 return 0; 846 } 847 848 /* Also take care of differential channels. */ 849 if (channel >= LTC4283_CHAN_ADIO12 && channel <= LTC4283_CHAN_ADIO34) { 850 channel -= LTC4283_CHAN_ADIO12; 851 /* If one channel in the pair is used, make it invisible. */ 852 if (test_bit(channel * 2, &st->gpio_mask) || 853 test_bit(channel * 2 + 1, &st->gpio_mask)) 854 return 0; 855 } 856 857 switch (attr) { 858 case hwmon_in_input: 859 case hwmon_in_highest: 860 case hwmon_in_lowest: 861 case hwmon_in_max_alarm: 862 case hwmon_in_min_alarm: 863 case hwmon_in_label: 864 case hwmon_in_lcrit_alarm: 865 case hwmon_in_crit_alarm: 866 case hwmon_in_fault: 867 return 0444; 868 case hwmon_in_max: 869 case hwmon_in_min: 870 case hwmon_in_enable: 871 return 0644; 872 case hwmon_in_reset_history: 873 return 0200; 874 default: 875 return 0; 876 } 877 } 878 879 static umode_t ltc4283_curr_is_visible(u32 attr) 880 { 881 switch (attr) { 882 case hwmon_curr_input: 883 case hwmon_curr_highest: 884 case hwmon_curr_lowest: 885 case hwmon_curr_max_alarm: 886 case hwmon_curr_min_alarm: 887 case hwmon_curr_crit_alarm: 888 case hwmon_curr_label: 889 return 0444; 890 case hwmon_curr_max: 891 case hwmon_curr_min: 892 return 0644; 893 case hwmon_curr_reset_history: 894 return 0200; 895 default: 896 return 0; 897 } 898 } 899 900 static umode_t ltc4283_power_is_visible(u32 attr) 901 { 902 switch (attr) { 903 case hwmon_power_input: 904 case hwmon_power_input_highest: 905 case hwmon_power_input_lowest: 906 case hwmon_power_label: 907 case hwmon_power_max_alarm: 908 case hwmon_power_min_alarm: 909 return 0444; 910 case hwmon_power_max: 911 case hwmon_power_min: 912 return 0644; 913 case hwmon_power_reset_history: 914 return 0200; 915 default: 916 return 0; 917 } 918 } 919 920 static umode_t ltc4283_is_visible(const void *data, 921 enum hwmon_sensor_types type, 922 u32 attr, int channel) 923 { 924 switch (type) { 925 case hwmon_in: 926 return ltc4283_in_is_visible(data, attr, channel); 927 case hwmon_curr: 928 return ltc4283_curr_is_visible(attr); 929 case hwmon_power: 930 return ltc4283_power_is_visible(attr); 931 case hwmon_energy: 932 /* hwmon_energy_enable */ 933 return 0644; 934 case hwmon_energy64: 935 /* hwmon_energy_input */ 936 return 0444; 937 default: 938 return 0; 939 } 940 } 941 942 static const char * const ltc4283_in_strs[] = { 943 "VIN", "VPWR", "VADI1", "VADI2", "VADI3", "VADI4", "VADIO1", "VADIO2", 944 "VADIO3", "VADIO4", "DRNS", "DRAIN", "ADIN2-ADIN1", "ADIN4-ADIN3", 945 "ADIO2-ADIO1", "ADIO4-ADIO3" 946 }; 947 948 static int ltc4283_read_labels(struct device *dev, 949 enum hwmon_sensor_types type, 950 u32 attr, int channel, const char **str) 951 { 952 switch (type) { 953 case hwmon_in: 954 *str = ltc4283_in_strs[channel]; 955 return 0; 956 case hwmon_curr: 957 *str = "ISENSE"; 958 return 0; 959 case hwmon_power: 960 *str = "Power"; 961 return 0; 962 default: 963 return -EOPNOTSUPP; 964 } 965 } 966 967 /* 968 * Set max limits for ISENSE and Power as that depends on the max voltage on 969 * rsense that is defined in ILIM_ADJUST. This is specially important for power 970 * because for some rsense and vfsout values, if we allow the default raw 255 971 * value, that would overflow long in 32bit archs when reading back the max 972 * power limit. 973 */ 974 static int ltc4283_set_max_limits(struct ltc4283_hwmon *st, struct device *dev) 975 { 976 u32 temp = st->vsense_max * DECA * MICRO; 977 int ret; 978 979 ret = ltc4283_write_in_byte(st, LTC4283_SENSE_MAX_TH, LTC4283_ADC1_FS_uV, 980 st->vsense_max * MILLI); 981 if (ret) 982 return ret; 983 984 /* Power is given by ISENSE * Vout. */ 985 st->power_max = DIV_ROUND_CLOSEST(temp, st->rsense) * LTC4283_ADC2_FS_mV; 986 return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, st->power_max); 987 } 988 989 static int ltc4283_parse_array_prop(const struct ltc4283_hwmon *st, 990 struct device *dev, const char *prop, 991 const u32 *vals, u32 n_vals) 992 { 993 u32 prop_val; 994 int ret; 995 u32 i; 996 997 ret = device_property_read_u32(dev, prop, &prop_val); 998 if (ret) 999 return n_vals; 1000 1001 for (i = 0; i < n_vals; i++) { 1002 if (prop_val != vals[i]) 1003 continue; 1004 1005 return i; 1006 } 1007 1008 return dev_err_probe(dev, -EINVAL, 1009 "Invalid %s property value %u\n", prop, prop_val); 1010 } 1011 1012 static int ltc4283_get_defaults(struct ltc4283_hwmon *st) 1013 { 1014 u32 reg_val, ilm_adjust, c; 1015 int ret; 1016 1017 ret = regmap_read(st->map, LTC4283_METER_CONTROL, ®_val); 1018 if (ret) 1019 return ret; 1020 1021 st->energy_en = !FIELD_GET(LTC4283_METER_HALT_MASK, reg_val); 1022 1023 ret = regmap_read(st->map, LTC4283_CONFIG_1, ®_val); 1024 if (ret) 1025 return ret; 1026 1027 ilm_adjust = FIELD_GET(LTC4283_ILIM_MASK, reg_val); 1028 st->vsense_max = LTC4283_VILIM_MIN_uV / MILLI + ilm_adjust; 1029 1030 ret = regmap_read(st->map, LTC4283_PGIO_CONFIG, ®_val); 1031 if (ret) 1032 return ret; 1033 1034 /* Can be latter overwritten in ltc4283_pgio_config() */ 1035 if (FIELD_GET(LTC4283_PGIO4_CFG_MASK, reg_val) < LTC4283_PGIO_FUNC_GPIO) 1036 st->ext_fault = true; 1037 1038 /* VPWR and VIN are always enabled */ 1039 __set_bit(LTC4283_CHAN_VIN, &st->ch_enable_mask); 1040 __set_bit(LTC4283_CHAN_VPWR, &st->ch_enable_mask); 1041 for (c = LTC4283_CHAN_ADI_1; c < LTC4283_CHAN_MAX; c++) { 1042 u32 chan = c - LTC4283_CHAN_ADI_1, bit; 1043 1044 ret = regmap_read(st->map, LTC4283_ADC_SELECT(chan), ®_val); 1045 if (ret) 1046 return ret; 1047 1048 bit = LTC4283_ADC_SELECT_MASK(chan); 1049 if (c > LTC4283_CHAN_DRAIN) 1050 /* account for two reserved fields after DRAIN */ 1051 bit <<= 2; 1052 1053 if (!(bit & reg_val)) 1054 continue; 1055 1056 __set_bit(c, &st->ch_enable_mask); 1057 } 1058 1059 return 0; 1060 } 1061 1062 static const char * const ltc4283_pgio1_funcs[] = { 1063 "inverted_power_good", "power_good", "gpio" 1064 }; 1065 1066 static const char * const ltc4283_pgio2_funcs[] = { 1067 "inverted_power_good", "power_good", "gpio", "active_current_limiting" 1068 }; 1069 1070 static const char * const ltc4283_pgio3_funcs[] = { 1071 "inverted_power_good_input", "power_good_input", "gpio" 1072 }; 1073 1074 static const char * const ltc4283_pgio4_funcs[] = { 1075 "inverted_external_fault", "external_fault", "gpio" 1076 }; 1077 1078 enum { 1079 LTC4283_PIN_ADIO1, 1080 LTC4283_PIN_ADIO2, 1081 LTC4283_PIN_ADIO3, 1082 LTC4283_PIN_ADIO4, 1083 LTC4283_PIN_PGIO1, 1084 LTC4283_PIN_PGIO2, 1085 LTC4283_PIN_PGIO3, 1086 LTC4283_PIN_PGIO4, 1087 }; 1088 1089 static int ltc4283_pgio_config(struct ltc4283_hwmon *st, struct device *dev) 1090 { 1091 int ret, func; 1092 1093 func = device_property_match_property_string(dev, "adi,pgio1-func", 1094 ltc4283_pgio1_funcs, 1095 ARRAY_SIZE(ltc4283_pgio1_funcs)); 1096 if (func < 0 && func != -EINVAL) 1097 return dev_err_probe(dev, func, 1098 "Invalid adi,pgio1-func property\n"); 1099 if (func >= 0) { 1100 if (func == LTC4283_PGIO_FUNC_GPIO) { 1101 __set_bit(LTC4283_PIN_PGIO1, &st->gpio_mask); 1102 /* If GPIO, default to an input pin. */ 1103 func++; 1104 } 1105 1106 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1107 LTC4283_PGIO1_CFG_MASK, 1108 FIELD_PREP(LTC4283_PGIO1_CFG_MASK, func)); 1109 if (ret) 1110 return ret; 1111 } 1112 1113 func = device_property_match_property_string(dev, "adi,pgio2-func", 1114 ltc4283_pgio2_funcs, 1115 ARRAY_SIZE(ltc4283_pgio2_funcs)); 1116 1117 if (func < 0 && func != -EINVAL) 1118 return dev_err_probe(dev, func, 1119 "Invalid adi,pgio2-func property\n"); 1120 if (func >= 0) { 1121 if (func != LTC4283_PGIO2_FUNC_ACLB) { 1122 if (func == LTC4283_PGIO_FUNC_GPIO) { 1123 __set_bit(LTC4283_PIN_PGIO2, &st->gpio_mask); 1124 func++; 1125 } 1126 1127 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1128 LTC4283_PGIO2_CFG_MASK, 1129 FIELD_PREP(LTC4283_PGIO2_CFG_MASK, func)); 1130 } else { 1131 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, 1132 LTC4283_PIGIO2_ACLB_MASK); 1133 } 1134 1135 if (ret) 1136 return ret; 1137 } 1138 1139 func = device_property_match_property_string(dev, "adi,pgio3-func", 1140 ltc4283_pgio3_funcs, 1141 ARRAY_SIZE(ltc4283_pgio3_funcs)); 1142 1143 if (func < 0 && func != -EINVAL) 1144 return dev_err_probe(dev, func, 1145 "Invalid adi,pgio3-func property\n"); 1146 if (func >= 0) { 1147 if (func == LTC4283_PGIO_FUNC_GPIO) { 1148 __set_bit(LTC4283_PIN_PGIO3, &st->gpio_mask); 1149 func++; 1150 } 1151 1152 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1153 LTC4283_PGIO3_CFG_MASK, 1154 FIELD_PREP(LTC4283_PGIO3_CFG_MASK, func)); 1155 if (ret) 1156 return ret; 1157 } 1158 1159 func = device_property_match_property_string(dev, "adi,pgio4-func", 1160 ltc4283_pgio4_funcs, 1161 ARRAY_SIZE(ltc4283_pgio4_funcs)); 1162 1163 if (func < 0 && func != -EINVAL) 1164 return dev_err_probe(dev, func, 1165 "Invalid adi,pgio4-func property\n"); 1166 if (func >= 0) { 1167 if (func == LTC4283_PGIO_FUNC_GPIO) { 1168 __set_bit(LTC4283_PIN_PGIO4, &st->gpio_mask); 1169 func++; 1170 st->ext_fault = false; 1171 } else { 1172 st->ext_fault = true; 1173 } 1174 1175 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1176 LTC4283_PGIO4_CFG_MASK, 1177 FIELD_PREP(LTC4283_PGIO4_CFG_MASK, func)); 1178 if (ret) 1179 return ret; 1180 } 1181 1182 return 0; 1183 } 1184 1185 static int ltc4283_adio_config(struct ltc4283_hwmon *st, struct device *dev, 1186 const char *prop, u32 pin) 1187 { 1188 u32 adc_idx; 1189 int ret; 1190 1191 if (!device_property_read_bool(dev, prop)) 1192 return 0; 1193 1194 adc_idx = LTC4283_CHAN_ADIO_1 - LTC4283_CHAN_ADI_1 + pin; 1195 ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(adc_idx), 1196 LTC4283_ADC_SELECT_MASK(adc_idx)); 1197 if (ret) 1198 return ret; 1199 1200 __set_bit(pin, &st->gpio_mask); 1201 return 0; 1202 } 1203 1204 static int ltc4283_pin_config(struct ltc4283_hwmon *st, struct device *dev) 1205 { 1206 int ret; 1207 1208 ret = ltc4283_pgio_config(st, dev); 1209 if (ret) 1210 return ret; 1211 1212 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio1", LTC4283_PIN_ADIO1); 1213 if (ret) 1214 return ret; 1215 1216 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio2", LTC4283_PIN_ADIO2); 1217 if (ret) 1218 return ret; 1219 1220 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio3", LTC4283_PIN_ADIO3); 1221 if (ret) 1222 return ret; 1223 1224 return ltc4283_adio_config(st, dev, "adi,gpio-on-adio4", LTC4283_PIN_ADIO4); 1225 } 1226 1227 static const char * const ltc4283_oc_fet_retry[] = { 1228 "latch-off", "1", "7", "unlimited" 1229 }; 1230 1231 static const u32 ltc4283_fb_factor[] = { 1232 100, 50, 20, 10 1233 }; 1234 1235 static const u32 ltc4283_cooling_dl[] = { 1236 512, 1002, 2005, 4100, 8190, 16400, 32800, 65600 1237 }; 1238 1239 static const u32 ltc4283_fet_bad_delay[] = { 1240 256, 512, 1002, 2005 1241 }; 1242 1243 static int ltc4283_setup(struct ltc4283_hwmon *st, struct device *dev) 1244 { 1245 u32 val; 1246 int ret; 1247 1248 /* The part has an eeprom so let's get the needed defaults from it */ 1249 ret = ltc4283_get_defaults(st); 1250 if (ret) 1251 return ret; 1252 1253 /* 1254 * Default to LTC4283_MIN_RSENSE so we can probe without FW properties. 1255 */ 1256 st->rsense = LTC4283_MIN_RSENSE; 1257 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1258 &st->rsense); 1259 if (!ret) { 1260 if (st->rsense < LTC4283_MIN_RSENSE || st->rsense > LTC4283_MAX_RSENSE) 1261 return dev_err_probe(dev, -EINVAL, 1262 "adi,rsense-nano-ohms(%u) too small or too large [%u %u]\n", 1263 st->rsense, LTC4283_MIN_RSENSE, LTC4283_MAX_RSENSE); 1264 } 1265 1266 /* 1267 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1268 * means we need nano in the bindings. However, to make things easier to 1269 * handle (with respect to overflows) we divide it by 100 as we don't 1270 * really need the last two digits. 1271 */ 1272 st->rsense /= CENTI; 1273 1274 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1275 &st->vsense_max); 1276 if (!ret) { 1277 u32 reg_val; 1278 1279 if (!in_range(st->vsense_max, LTC4283_VILIM_MIN_uV, 1280 LTC4283_VILIM_RANGE)) { 1281 return dev_err_probe(dev, -EINVAL, 1282 "adi,current-limit-sense-microvolt (%u) out of range [%u %u]\n", 1283 st->vsense_max, LTC4283_VILIM_MIN_uV, 1284 LTC4283_VILIM_MAX_uV); 1285 } 1286 1287 st->vsense_max /= MILLI; 1288 reg_val = FIELD_PREP(LTC4283_ILIM_MASK, 1289 st->vsense_max - LTC4283_VILIM_MIN_uV / MILLI); 1290 ret = regmap_update_bits(st->map, LTC4283_CONFIG_1, 1291 LTC4283_ILIM_MASK, reg_val); 1292 if (ret) 1293 return ret; 1294 } 1295 1296 ret = ltc4283_parse_array_prop(st, dev, "adi,current-limit-foldback-factor", 1297 ltc4283_fb_factor, ARRAY_SIZE(ltc4283_fb_factor)); 1298 if (ret < 0) 1299 return ret; 1300 if (ret < ARRAY_SIZE(ltc4283_fb_factor)) { 1301 ret = regmap_update_bits(st->map, LTC4283_CONFIG_1, LTC4283_FB_MASK, 1302 FIELD_PREP(LTC4283_FB_MASK, ret)); 1303 if (ret) 1304 return ret; 1305 } 1306 1307 ret = ltc4283_parse_array_prop(st, dev, "adi,cooling-delay-ms", 1308 ltc4283_cooling_dl, ARRAY_SIZE(ltc4283_cooling_dl)); 1309 if (ret < 0) 1310 return ret; 1311 if (ret < ARRAY_SIZE(ltc4283_cooling_dl)) { 1312 ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_COOLING_DL_MASK, 1313 FIELD_PREP(LTC4283_COOLING_DL_MASK, ret)); 1314 if (ret) 1315 return ret; 1316 } 1317 1318 ret = ltc4283_parse_array_prop(st, dev, "adi,fet-bad-timer-delay-ms", 1319 ltc4283_fet_bad_delay, ARRAY_SIZE(ltc4283_fet_bad_delay)); 1320 if (ret < 0) 1321 return ret; 1322 if (ret < ARRAY_SIZE(ltc4283_fet_bad_delay)) { 1323 ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_FTBD_DL_MASK, 1324 FIELD_PREP(LTC4283_FTBD_DL_MASK, ret)); 1325 if (ret) 1326 return ret; 1327 } 1328 1329 ret = ltc4283_set_max_limits(st, dev); 1330 if (ret) 1331 return ret; 1332 1333 ret = ltc4283_pin_config(st, dev); 1334 if (ret) 1335 return ret; 1336 1337 if (device_property_read_bool(dev, "adi,power-good-reset-on-fet")) { 1338 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1339 LTC4283_PWRGD_RST_CTRL_MASK); 1340 if (ret) 1341 return ret; 1342 } 1343 1344 if (device_property_read_bool(dev, "adi,fet-turn-off-disable")) { 1345 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1346 LTC4283_FET_BAD_OFF_MASK); 1347 if (ret) 1348 return ret; 1349 } 1350 1351 if (device_property_read_bool(dev, "adi,tmr-pull-down-disable")) { 1352 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, 1353 LTC4283_THERM_TMR_MASK); 1354 if (ret) 1355 return ret; 1356 } 1357 1358 if (device_property_read_bool(dev, "adi,dvdt-inrush-control-disable")) { 1359 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1360 LTC4283_DVDT_MASK); 1361 if (ret) 1362 return ret; 1363 } 1364 1365 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1366 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2, 1367 LTC4283_UV_RETRY_MASK); 1368 if (ret) 1369 return ret; 1370 } 1371 1372 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1373 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2, 1374 LTC4283_OV_RETRY_MASK); 1375 if (ret) 1376 return ret; 1377 } 1378 1379 if (device_property_read_bool(dev, "adi,external-fault-retry-enable")) { 1380 if (!st->ext_fault) 1381 return dev_err_probe(dev, -EINVAL, 1382 "adi,external-fault-retry-enable set but PGIO4 not configured\n"); 1383 ret = regmap_set_bits(st->map, LTC4283_CONTROL_2, 1384 LTC4283_EXT_FAULT_RETRY_MASK); 1385 if (ret) 1386 return ret; 1387 } 1388 1389 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1390 ret = regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL, 1391 LTC4283_FAULT_LOG_EN_MASK); 1392 if (ret) 1393 return ret; 1394 } 1395 1396 ret = device_property_match_property_string(dev, "adi,overcurrent-retries", 1397 ltc4283_oc_fet_retry, 1398 ARRAY_SIZE(ltc4283_oc_fet_retry)); 1399 /* We still want to catch when an invalid string is given. */ 1400 if (ret < 0 && ret != -EINVAL) 1401 return dev_err_probe(dev, ret, 1402 "adi,overcurrent-retries invalid value\n"); 1403 if (ret >= 0) { 1404 ret = regmap_update_bits(st->map, LTC4283_CONTROL_2, 1405 LTC4283_OC_RETRY_MASK, 1406 FIELD_PREP(LTC4283_OC_RETRY_MASK, ret)); 1407 if (ret) 1408 return ret; 1409 } 1410 1411 ret = device_property_match_property_string(dev, "adi,fet-bad-retries", 1412 ltc4283_oc_fet_retry, 1413 ARRAY_SIZE(ltc4283_oc_fet_retry)); 1414 if (ret < 0 && ret != -EINVAL) 1415 return dev_err_probe(dev, ret, 1416 "adi,fet-bad-retries invalid value\n"); 1417 if (ret >= 0) { 1418 ret = regmap_update_bits(st->map, LTC4283_CONTROL_2, 1419 LTC4283_FET_BAD_RETRY_MASK, 1420 FIELD_PREP(LTC4283_FET_BAD_RETRY_MASK, ret)); 1421 if (ret) 1422 return ret; 1423 } 1424 1425 if (device_property_read_bool(dev, "adi,external-fault-fet-off-enable")) { 1426 if (!st->ext_fault) 1427 return dev_err_probe(dev, -EINVAL, 1428 "adi,external-fault-fet-off-enable set but PGIO4 not configured\n"); 1429 ret = regmap_set_bits(st->map, LTC4283_CONFIG_3, 1430 LTC4283_EXTFLT_TURN_OFF_MASK); 1431 if (ret) 1432 return ret; 1433 } 1434 1435 if (device_property_read_bool(dev, "adi,vpower-drns-enable")) { 1436 u32 chan = LTC4283_CHAN_DRNS - LTC4283_CHAN_ADI_1; 1437 1438 __clear_bit(LTC4283_CHAN_DRNS, &st->ch_enable_mask); 1439 /* 1440 * Then, let's by default disable DRNS from ADC2 given that it 1441 * is already being monitored by the VPWR channel. One can still 1442 * enable it later on if needed. 1443 */ 1444 ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(chan), 1445 LTC4283_ADC_SELECT_MASK(chan)); 1446 if (ret) 1447 return ret; 1448 1449 val = 1; 1450 } else { 1451 val = 0; 1452 } 1453 1454 ret = regmap_update_bits(st->map, LTC4283_CONFIG_3, 1455 LTC4283_VPWR_DRNS_MASK, 1456 FIELD_PREP(LTC4283_VPWR_DRNS_MASK, val)); 1457 if (ret) 1458 return ret; 1459 1460 /* Make sure the ADC has 12bit resolution since we're assuming that. */ 1461 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG_2, 1462 LTC4283_ADC_MASK, 1463 FIELD_PREP(LTC4283_ADC_MASK, 3)); 1464 if (ret) 1465 return ret; 1466 1467 /* Energy reads (which are 6 byte block reads) rely on page access */ 1468 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, LTC4283_RW_PAGE_MASK); 1469 if (ret) 1470 return ret; 1471 1472 /* 1473 * Make sure we are integrating power as we only support reporting 1474 * consumed energy. 1475 */ 1476 return regmap_clear_bits(st->map, LTC4283_METER_CONTROL, 1477 LTC4283_INTEGRATE_I_MASK); 1478 } 1479 1480 static const struct hwmon_channel_info * const ltc4283_info[] = { 1481 HWMON_CHANNEL_INFO(in, 1482 HWMON_I_LCRIT_ALARM | HWMON_I_CRIT_ALARM | 1483 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1484 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1485 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1486 HWMON_I_MAX_ALARM | HWMON_I_RESET_HISTORY | 1487 HWMON_I_LABEL, 1488 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1489 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1490 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1491 HWMON_I_ENABLE | HWMON_I_LABEL, 1492 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1493 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1494 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1495 HWMON_I_ENABLE | HWMON_I_LABEL, 1496 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1497 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1498 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1499 HWMON_I_ENABLE | HWMON_I_LABEL, 1500 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1501 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1502 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1503 HWMON_I_ENABLE | HWMON_I_LABEL, 1504 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1505 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1506 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1507 HWMON_I_ENABLE | HWMON_I_LABEL, 1508 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1509 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1510 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1511 HWMON_I_ENABLE | HWMON_I_LABEL, 1512 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1513 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1514 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1515 HWMON_I_ENABLE | HWMON_I_LABEL, 1516 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1517 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1518 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1519 HWMON_I_ENABLE | HWMON_I_LABEL, 1520 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1521 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1522 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1523 HWMON_I_ENABLE | HWMON_I_LABEL, 1524 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1525 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1526 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1527 HWMON_I_FAULT | HWMON_I_ENABLE | HWMON_I_LABEL, 1528 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1529 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1530 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1531 HWMON_I_ENABLE | HWMON_I_LABEL, 1532 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1533 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1534 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1535 HWMON_I_ENABLE | HWMON_I_LABEL, 1536 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1537 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1538 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1539 HWMON_I_ENABLE | HWMON_I_LABEL, 1540 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1541 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1542 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1543 HWMON_I_ENABLE | HWMON_I_LABEL), 1544 HWMON_CHANNEL_INFO(curr, 1545 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1546 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1547 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1548 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1549 HWMON_CHANNEL_INFO(power, 1550 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1551 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1552 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1553 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1554 HWMON_CHANNEL_INFO(energy, 1555 HWMON_E_ENABLE), 1556 HWMON_CHANNEL_INFO(energy64, 1557 HWMON_E_INPUT), 1558 NULL 1559 }; 1560 1561 static const struct hwmon_ops ltc4283_ops = { 1562 .read = ltc4283_read, 1563 .write = ltc4283_write, 1564 .is_visible = ltc4283_is_visible, 1565 .read_string = ltc4283_read_labels, 1566 }; 1567 1568 static const struct hwmon_chip_info ltc4283_chip_info = { 1569 .ops = <c4283_ops, 1570 .info = ltc4283_info, 1571 }; 1572 1573 static int ltc4283_show_fault_log(void *arg, u64 *val, u32 mask) 1574 { 1575 struct ltc4283_hwmon *st = arg; 1576 long alarm; 1577 int ret; 1578 1579 ret = ltc4283_read_alarm(st, LTC4283_FAULT_LOG, mask, &alarm); 1580 if (ret) 1581 return ret; 1582 1583 *val = alarm; 1584 1585 return 0; 1586 } 1587 1588 static int ltc4283_show_in0_lcrit_fault_log(void *arg, u64 *val) 1589 { 1590 return ltc4283_show_fault_log(arg, val, LTC4283_UV_FAULT_MASK); 1591 } 1592 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_lcrit_fault_log, 1593 ltc4283_show_in0_lcrit_fault_log, NULL, "%llu\n"); 1594 1595 static int ltc4283_show_in0_crit_fault_log(void *arg, u64 *val) 1596 { 1597 return ltc4283_show_fault_log(arg, val, LTC4283_OV_FAULT_MASK); 1598 } 1599 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_crit_fault_log, 1600 ltc4283_show_in0_crit_fault_log, NULL, "%llu\n"); 1601 1602 static int ltc4283_show_fet_bad_fault_log(void *arg, u64 *val) 1603 { 1604 return ltc4283_show_fault_log(arg, val, LTC4283_FET_BAD_FAULT_MASK); 1605 } 1606 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_bad_fault_log, 1607 ltc4283_show_fet_bad_fault_log, NULL, "%llu\n"); 1608 1609 static int ltc4283_show_fet_short_fault_log(void *arg, u64 *val) 1610 { 1611 return ltc4283_show_fault_log(arg, val, LTC4283_FET_SHORT_FAULT_MASK); 1612 } 1613 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_short_fault_log, 1614 ltc4283_show_fet_short_fault_log, NULL, "%llu\n"); 1615 1616 static int ltc4283_show_curr1_crit_fault_log(void *arg, u64 *val) 1617 { 1618 return ltc4283_show_fault_log(arg, val, LTC4283_OC_FAULT_MASK); 1619 } 1620 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_curr1_crit_fault_log, 1621 ltc4283_show_curr1_crit_fault_log, NULL, "%llu\n"); 1622 1623 static int ltc4283_show_power1_failed_fault_log(void *arg, u64 *val) 1624 { 1625 return ltc4283_show_fault_log(arg, val, LTC4283_PWR_FAIL_FAULT_MASK); 1626 } 1627 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_failed_fault_log, 1628 ltc4283_show_power1_failed_fault_log, NULL, "%llu\n"); 1629 1630 static int ltc4283_show_power1_good_input_fault_log(void *arg, u64 *val) 1631 { 1632 return ltc4283_show_fault_log(arg, val, LTC4283_PGI_FAULT_MASK); 1633 } 1634 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_good_input_fault_log, 1635 ltc4283_show_power1_good_input_fault_log, NULL, "%llu\n"); 1636 1637 static void ltc4283_debugfs_init(struct ltc4283_hwmon *st, struct i2c_client *i2c) 1638 { 1639 debugfs_create_file_unsafe("in0_crit_fault_log", 0400, i2c->debugfs, st, 1640 <c4283_in0_crit_fault_log); 1641 debugfs_create_file_unsafe("in0_lcrit_fault_log", 0400, i2c->debugfs, st, 1642 <c4283_in0_lcrit_fault_log); 1643 debugfs_create_file_unsafe("in11_fet_bad_fault_log", 0400, i2c->debugfs, st, 1644 <c4283_fet_bad_fault_log); 1645 debugfs_create_file_unsafe("in11_fet_short_fault_log", 0400, i2c->debugfs, st, 1646 <c4283_fet_short_fault_log); 1647 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1648 <c4283_curr1_crit_fault_log); 1649 debugfs_create_file_unsafe("power1_failed_fault_log", 0400, i2c->debugfs, st, 1650 <c4283_power1_failed_fault_log); 1651 debugfs_create_file_unsafe("power1_good_input_fault_log", 0400, i2c->debugfs, 1652 st, <c4283_power1_good_input_fault_log); 1653 } 1654 1655 static bool ltc4283_is_word_reg(unsigned int reg) 1656 { 1657 return reg >= LTC4283_SENSE && reg <= LTC4283_ADIO34_MAX; 1658 } 1659 1660 static int ltc4283_reg_read(void *context, unsigned int reg, unsigned int *val) 1661 { 1662 struct i2c_client *client = context; 1663 int ret; 1664 1665 if (ltc4283_is_word_reg(reg)) 1666 ret = i2c_smbus_read_word_swapped(client, reg); 1667 else 1668 ret = i2c_smbus_read_byte_data(client, reg); 1669 1670 if (ret < 0) 1671 return ret; 1672 1673 *val = ret; 1674 return 0; 1675 } 1676 1677 static int ltc4283_reg_write(void *context, unsigned int reg, unsigned int val) 1678 { 1679 struct i2c_client *client = context; 1680 1681 if (ltc4283_is_word_reg(reg)) 1682 return i2c_smbus_write_word_swapped(client, reg, val); 1683 1684 return i2c_smbus_write_byte_data(client, reg, val); 1685 } 1686 1687 static const struct regmap_bus ltc4283_regmap_bus = { 1688 .reg_read = ltc4283_reg_read, 1689 .reg_write = ltc4283_reg_write, 1690 }; 1691 1692 static bool ltc4283_writable_reg(struct device *dev, unsigned int reg) 1693 { 1694 switch (reg) { 1695 case LTC4283_SYSTEM_STATUS ... LTC4283_FAULT_STATUS: 1696 return false; 1697 case LTC4283_RESERVED_OC: 1698 return false; 1699 case LTC4283_RESERVED_86 ... LTC4283_RESERVED_8F: 1700 return false; 1701 case LTC4283_RESERVED_91 ... LTC4283_RESERVED_A1: 1702 return false; 1703 case LTC4283_RESERVED_A3: 1704 return false; 1705 case LTC4283_RESERVED_AC: 1706 return false; 1707 case LTC4283_POWER_PLAY_MSB ... LTC4283_POWER_PLAY_LSB: 1708 return false; 1709 case LTC4283_RESERVED_F1 ... LTC4283_RESERVED_FF: 1710 return false; 1711 default: 1712 return true; 1713 } 1714 } 1715 1716 static const struct regmap_config ltc4283_regmap_config = { 1717 .reg_bits = 8, 1718 .val_bits = 16, 1719 .max_register = 0xFF, 1720 .writeable_reg = ltc4283_writable_reg, 1721 }; 1722 1723 static int ltc4283_probe(struct i2c_client *client) 1724 { 1725 struct device *dev = &client->dev, *hwmon; 1726 struct auxiliary_device *adev; 1727 struct ltc4283_hwmon *st; 1728 int ret, id; 1729 1730 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1731 if (!st) 1732 return -ENOMEM; 1733 1734 if (!i2c_check_functionality(client->adapter, 1735 I2C_FUNC_SMBUS_BYTE_DATA | 1736 I2C_FUNC_SMBUS_WORD_DATA | 1737 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) 1738 return -EOPNOTSUPP; 1739 1740 st->client = client; 1741 st->map = devm_regmap_init(dev, <c4283_regmap_bus, client, 1742 <c4283_regmap_config); 1743 if (IS_ERR(st->map)) 1744 return dev_err_probe(dev, PTR_ERR(st->map), 1745 "Failed to create regmap\n"); 1746 1747 ret = ltc4283_setup(st, dev); 1748 if (ret) 1749 return ret; 1750 1751 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4283", st, 1752 <c4283_chip_info, NULL); 1753 1754 if (IS_ERR(hwmon)) 1755 return PTR_ERR(hwmon); 1756 1757 ltc4283_debugfs_init(st, client); 1758 1759 if (!st->gpio_mask) 1760 return 0; 1761 1762 id = (client->adapter->nr << 10) | client->addr; 1763 adev = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, "gpio", 1764 &st->gpio_mask, id); 1765 if (!adev) 1766 return dev_err_probe(dev, -ENODEV, "Failed to add GPIO device\n"); 1767 1768 return 0; 1769 } 1770 1771 static const struct of_device_id ltc4283_of_match[] = { 1772 { .compatible = "adi,ltc4283" }, 1773 { } 1774 }; 1775 MODULE_DEVICE_TABLE(of, ltc4283_of_match); 1776 1777 static const struct i2c_device_id ltc4283_i2c_id[] = { 1778 { "ltc4283" }, 1779 { } 1780 }; 1781 MODULE_DEVICE_TABLE(i2c, ltc4283_i2c_id); 1782 1783 static struct i2c_driver ltc4283_driver = { 1784 .driver = { 1785 .name = "ltc4283", 1786 .of_match_table = ltc4283_of_match, 1787 }, 1788 .probe = ltc4283_probe, 1789 .id_table = ltc4283_i2c_id, 1790 }; 1791 module_i2c_driver(ltc4283_driver); 1792 1793 MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>"); 1794 MODULE_DESCRIPTION("LTC4283 Hot Swap Controller driver"); 1795 MODULE_LICENSE("GPL"); 1796