1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Analog Devices LTC4283 I2C Negative Voltage Hot Swap Controller (HWMON) 4 * 5 * Copyright 2025 Analog Devices Inc. 6 */ 7 #include <linux/auxiliary_bus.h> 8 #include <linux/bitfield.h> 9 #include <linux/bitmap.h> 10 #include <linux/bitops.h> 11 #include <linux/bits.h> 12 13 #include <linux/debugfs.h> 14 #include <linux/device.h> 15 #include <linux/device/devres.h> 16 #include <linux/hwmon.h> 17 #include <linux/i2c.h> 18 #include <linux/math.h> 19 #include <linux/math64.h> 20 #include <linux/minmax.h> 21 #include <linux/module.h> 22 23 #include <linux/mod_devicetable.h> 24 #include <linux/property.h> 25 #include <linux/regmap.h> 26 #include <linux/unaligned.h> 27 #include <linux/units.h> 28 29 #define LTC4283_SYSTEM_STATUS 0x00 30 #define LTC4283_FAULT_STATUS 0x03 31 #define LTC4283_OV_MASK BIT(0) 32 #define LTC4283_UV_MASK BIT(1) 33 #define LTC4283_OC_MASK BIT(2) 34 #define LTC4283_FET_BAD_MASK BIT(3) 35 #define LTC4283_FET_SHORT_MASK BIT(6) 36 #define LTC4283_FAULT_LOG 0x04 37 #define LTC4283_OV_FAULT_MASK BIT(0) 38 #define LTC4283_UV_FAULT_MASK BIT(1) 39 #define LTC4283_OC_FAULT_MASK BIT(2) 40 #define LTC4283_FET_BAD_FAULT_MASK BIT(3) 41 #define LTC4283_PGI_FAULT_MASK BIT(4) 42 #define LTC4283_PWR_FAIL_FAULT_MASK BIT(5) 43 #define LTC4283_FET_SHORT_FAULT_MASK BIT(6) 44 #define LTC4283_ADC_ALM_LOG_1 0x05 45 #define LTC4283_POWER_LOW_ALM BIT(0) 46 #define LTC4283_POWER_HIGH_ALM BIT(1) 47 #define LTC4283_SENSE_LOW_ALM BIT(4) 48 #define LTC4283_SENSE_HIGH_ALM BIT(5) 49 #define LTC4283_ADC_ALM_LOG_2 0x06 50 #define LTC4283_ADC_ALM_LOG_3 0x07 51 #define LTC4283_ADC_ALM_LOG_4 0x08 52 #define LTC4283_ADC_ALM_LOG_5 0x09 53 #define LTC4283_CONTROL_1 0x0a 54 #define LTC4283_RW_PAGE_MASK BIT(0) 55 #define LTC4283_PIGIO2_ACLB_MASK BIT(2) 56 #define LTC4283_PWRGD_RST_CTRL_MASK BIT(3) 57 #define LTC4283_FET_BAD_OFF_MASK BIT(4) 58 #define LTC4283_THERM_TMR_MASK BIT(5) 59 #define LTC4283_DVDT_MASK BIT(6) 60 #define LTC4283_CONTROL_2 0x0b 61 #define LTC4283_OV_RETRY_MASK BIT(0) 62 #define LTC4283_UV_RETRY_MASK BIT(1) 63 #define LTC4283_OC_RETRY_MASK GENMASK(3, 2) 64 #define LTC4283_FET_BAD_RETRY_MASK GENMASK(5, 4) 65 #define LTC4283_EXT_FAULT_RETRY_MASK BIT(7) 66 #define LTC4283_RESERVED_OC 0x0c 67 #define LTC4283_CONFIG_1 0x0d 68 #define LTC4283_FB_MASK GENMASK(3, 2) 69 #define LTC4283_ILIM_MASK GENMASK(7, 4) 70 #define LTC4283_CONFIG_2 0x0e 71 #define LTC4283_COOLING_DL_MASK GENMASK(3, 1) 72 #define LTC4283_FTBD_DL_MASK GENMASK(5, 4) 73 #define LTC4283_CONFIG_3 0x0f 74 #define LTC4283_VPWR_DRNS_MASK BIT(6) 75 #define LTC4283_EXTFLT_TURN_OFF_MASK BIT(7) 76 #define LTC4283_PGIO_CONFIG 0x10 77 #define LTC4283_PGIO1_CFG_MASK GENMASK(1, 0) 78 #define LTC4283_PGIO2_CFG_MASK GENMASK(3, 2) 79 #define LTC4283_PGIO3_CFG_MASK GENMASK(5, 4) 80 #define LTC4283_PGIO4_CFG_MASK GENMASK(7, 6) 81 #define LTC4283_PGIO_CONFIG_2 0x11 82 #define LTC4283_ADC_MASK GENMASK(2, 0) 83 #define LTC4283_ADC_SELECT(c) (0x13 + (c) / 8) 84 #define LTC4283_ADC_SELECT_MASK(c) BIT((c) % 8) 85 #define LTC4283_SENSE_MIN_TH 0x1b 86 #define LTC4283_SENSE_MAX_TH 0x1c 87 #define LTC4283_VPWR_MIN_TH 0x1d 88 #define LTC4283_VPWR_MAX_TH 0x1e 89 #define LTC4283_POWER_MIN_TH 0x1f 90 #define LTC4283_POWER_MAX_TH 0x20 91 #define LTC4283_ADC_2_MIN_TH(c) (0x21 + (c) * 2) 92 #define LTC4283_ADC_2_MAX_TH(c) (0x22 + (c) * 2) 93 #define LTC4283_ADC_2_MIN_TH_DIFF(c) (0x39 + (c) * 2) 94 #define LTC4283_ADC_2_MAX_TH_DIFF(c) (0x3a + (c) * 2) 95 #define LTC4283_SENSE 0x41 96 #define LTC4283_SENSE_MIN 0x42 97 #define LTC4283_SENSE_MAX 0x43 98 #define LTC4283_VPWR 0x44 99 #define LTC4283_VPWR_MIN 0x45 100 #define LTC4283_VPWR_MAX 0x46 101 #define LTC4283_POWER 0x47 102 #define LTC4283_POWER_MIN 0x48 103 #define LTC4283_POWER_MAX 0x49 104 #define LTC4283_RESERVED_68 0x68 105 #define LTC4283_RESERVED_6D 0x6D 106 /* get channels from ADC 2 */ 107 #define LTC4283_ADC_2(c) (0x4a + (c) * 3) 108 #define LTC4283_ADC_2_MIN(c) (0x4b + (c) * 3) 109 #define LTC4283_ADC_2_MAX(c) (0x4c + (c) * 3) 110 #define LTC4283_ADC_2_DIFF(c) (0x6e + (c) * 3) 111 #define LTC4283_ADC_2_MIN_DIFF(c) (0x6f + (c) * 3) 112 #define LTC4283_ADC_2_MAX_DIFF(c) (0x70 + (c) * 3) 113 #define LTC4283_ENERGY 0x7a 114 #define LTC4283_METER_CONTROL 0x84 115 #define LTC4283_INTEGRATE_I_MASK BIT(0) 116 #define LTC4283_METER_HALT_MASK BIT(6) 117 #define LTC4283_RESERVED_86 0x86 118 #define LTC4283_RESERVED_8F 0x8F 119 #define LTC4283_FAULT_LOG_CTRL 0x90 120 #define LTC4283_FAULT_LOG_EN_MASK BIT(7) 121 #define LTC4283_RESERVED_91 0x91 122 #define LTC4283_RESERVED_A1 0xA1 123 #define LTC4283_RESERVED_A3 0xA3 124 #define LTC4283_RESERVED_AC 0xAC 125 #define LTC4283_POWER_PLAY_MSB 0xE7 126 #define LTC4283_POWER_PLAY_LSB 0xE8 127 #define LTC4283_RESERVED_F1 0xF1 128 #define LTC4283_RESERVED_FF 0xFF 129 130 /* also applies for differential channels */ 131 #define LTC4283_ADC1_FS_uV 32768 132 #define LTC4283_ADC2_FS_mV 2048 133 #define LTC4283_TCONV_uS 64103 134 #define LTC4283_VILIM_MIN_uV 15000 135 #define LTC4283_VILIM_MAX_uV 30000 136 #define LTC4283_VILIM_RANGE \ 137 (LTC4283_VILIM_MAX_uV - LTC4283_VILIM_MIN_uV + 1) 138 139 #define LTC4283_PGIO_FUNC_GPIO 2 140 #define LTC4283_PGIO2_FUNC_ACLB 3 141 142 /* 143 * Maximum value for rsense in nano ohms. The reasoning for this value is that 144 * it's the max value for which multiplying by 256 does not overflow long on 145 * 32bits. For the minimum value, is a sane minimum rsense for which power_max 146 * does not overflow 32bits. 147 */ 148 #define LTC4283_MAX_RSENSE 1677721599 149 #define LTC4283_MIN_RSENSE 50000 150 151 /* voltage channels */ 152 enum { 153 LTC4283_CHAN_VIN, 154 LTC4283_CHAN_VPWR, 155 LTC4283_CHAN_ADI_1, 156 LTC4283_CHAN_ADI_2, 157 LTC4283_CHAN_ADI_3, 158 LTC4283_CHAN_ADI_4, 159 LTC4283_CHAN_ADIO_1, 160 LTC4283_CHAN_ADIO_2, 161 LTC4283_CHAN_ADIO_3, 162 LTC4283_CHAN_ADIO_4, 163 LTC4283_CHAN_DRNS, 164 LTC4283_CHAN_DRAIN, 165 /* differential channels */ 166 LTC4283_CHAN_ADIN12, 167 LTC4283_CHAN_ADIN34, 168 LTC4283_CHAN_ADIO12, 169 LTC4283_CHAN_ADIO34, 170 LTC4283_CHAN_MAX 171 }; 172 173 /* Just for ease of use on the regmap */ 174 #define LTC4283_ADIO34_MAX \ 175 LTC4283_ADC_2_MAX_DIFF(LTC4283_CHAN_ADIO34 - LTC4283_CHAN_ADIN12) 176 177 struct ltc4283_hwmon { 178 struct regmap *map; 179 struct i2c_client *client; 180 unsigned long gpio_mask; 181 unsigned long ch_enable_mask; 182 /* in microwatt */ 183 unsigned long power_max; 184 /* in millivolt */ 185 u32 vsense_max; 186 /* in tenths of microohm*/ 187 u32 rsense; 188 bool energy_en; 189 bool ext_fault; 190 }; 191 192 static int ltc4283_read_voltage_word(const struct ltc4283_hwmon *st, 193 u32 reg, u32 fs, long *val) 194 { 195 unsigned int __raw; 196 int ret; 197 198 ret = regmap_read(st->map, reg, &__raw); 199 if (ret) 200 return ret; 201 202 *val = DIV_ROUND_CLOSEST(__raw * fs, BIT(16)); 203 return 0; 204 } 205 206 static int ltc4283_read_voltage_byte(const struct ltc4283_hwmon *st, 207 u32 reg, u32 fs, long *val) 208 { 209 int ret; 210 u32 in; 211 212 ret = regmap_read(st->map, reg, &in); 213 if (ret) 214 return ret; 215 216 *val = DIV_ROUND_CLOSEST(in * fs, BIT(8)); 217 return 0; 218 } 219 220 static u32 ltc4283_in_reg(u32 attr, u32 channel) 221 { 222 switch (attr) { 223 case hwmon_in_input: 224 if (channel == LTC4283_CHAN_VPWR) 225 return LTC4283_VPWR; 226 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 227 return LTC4283_ADC_2(channel - LTC4283_CHAN_ADI_1); 228 return LTC4283_ADC_2_DIFF(channel - LTC4283_CHAN_ADIN12); 229 case hwmon_in_highest: 230 if (channel == LTC4283_CHAN_VPWR) 231 return LTC4283_VPWR_MAX; 232 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 233 return LTC4283_ADC_2_MAX(channel - LTC4283_CHAN_ADI_1); 234 return LTC4283_ADC_2_MAX_DIFF(channel - LTC4283_CHAN_ADIN12); 235 case hwmon_in_lowest: 236 if (channel == LTC4283_CHAN_VPWR) 237 return LTC4283_VPWR_MIN; 238 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 239 return LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1); 240 return LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12); 241 case hwmon_in_max: 242 if (channel == LTC4283_CHAN_VPWR) 243 return LTC4283_VPWR_MAX_TH; 244 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 245 return LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1); 246 return LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 247 default: 248 if (channel == LTC4283_CHAN_VPWR) 249 return LTC4283_VPWR_MIN_TH; 250 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) 251 return LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1); 252 return LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 253 } 254 } 255 256 static int ltc4283_read_in_vals(const struct ltc4283_hwmon *st, 257 u32 attr, u32 channel, long *val) 258 { 259 u32 reg = ltc4283_in_reg(attr, channel); 260 int ret; 261 262 if (channel < LTC4283_CHAN_ADIN12) { 263 if (attr != hwmon_in_max && attr != hwmon_in_min) 264 return ltc4283_read_voltage_word(st, reg, 265 LTC4283_ADC2_FS_mV, 266 val); 267 268 return ltc4283_read_voltage_byte(st, reg, 269 LTC4283_ADC2_FS_mV, val); 270 } 271 272 if (attr != hwmon_in_max && attr != hwmon_in_min) 273 ret = ltc4283_read_voltage_word(st, reg, 274 LTC4283_ADC1_FS_uV, val); 275 else 276 ret = ltc4283_read_voltage_byte(st, reg, 277 LTC4283_ADC1_FS_uV, val); 278 if (ret) 279 return ret; 280 281 *val = DIV_ROUND_CLOSEST(*val, MILLI); 282 return 0; 283 } 284 285 static int ltc4283_read_alarm(struct ltc4283_hwmon *st, u32 reg, 286 u32 mask, long *val) 287 { 288 u32 alarm; 289 int ret; 290 291 ret = regmap_read(st->map, reg, &alarm); 292 if (ret) 293 return ret; 294 295 *val = !!(alarm & mask); 296 297 /* If not status/fault logs, clear the alarm after reading it. */ 298 if (reg != LTC4283_FAULT_STATUS && reg != LTC4283_FAULT_LOG) 299 return regmap_write(st->map, reg, alarm & ~mask); 300 301 return 0; 302 } 303 304 static int ltc4283_read_in_alarm(struct ltc4283_hwmon *st, u32 channel, 305 bool max_alm, long *val) 306 { 307 if (channel == LTC4283_CHAN_VPWR) 308 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 309 BIT(2 + max_alm), val); 310 311 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_ADI_4) { 312 u32 bit = (channel - LTC4283_CHAN_ADI_1) * 2; 313 /* 314 * Lower channels go to higher bits. We also want to go +1 down 315 * in the min_alarm case. 316 */ 317 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_2, 318 BIT(7 - bit - !max_alm), val); 319 } 320 321 if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) { 322 u32 bit = (channel - LTC4283_CHAN_ADIO_1) * 2; 323 324 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_3, 325 BIT(7 - bit - !max_alm), val); 326 } 327 328 if (channel >= LTC4283_CHAN_ADIN12 && channel <= LTC4283_CHAN_ADIO34) { 329 u32 bit = (channel - LTC4283_CHAN_ADIN12) * 2; 330 331 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_5, 332 BIT(7 - bit - !max_alm), val); 333 } 334 335 if (channel == LTC4283_CHAN_DRNS) 336 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, 337 BIT(6 + max_alm), val); 338 339 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_4, BIT(4 + max_alm), 340 val); 341 } 342 343 static int ltc4283_read_in(struct ltc4283_hwmon *st, u32 attr, u32 channel, 344 long *val) 345 { 346 switch (attr) { 347 case hwmon_in_input: 348 if (!test_bit(channel, &st->ch_enable_mask)) 349 return -ENODATA; 350 351 return ltc4283_read_in_vals(st, attr, channel, val); 352 case hwmon_in_highest: 353 case hwmon_in_lowest: 354 case hwmon_in_max: 355 case hwmon_in_min: 356 return ltc4283_read_in_vals(st, attr, channel, val); 357 case hwmon_in_max_alarm: 358 return ltc4283_read_in_alarm(st, channel, true, val); 359 case hwmon_in_min_alarm: 360 return ltc4283_read_in_alarm(st, channel, false, val); 361 case hwmon_in_crit_alarm: 362 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 363 LTC4283_OV_MASK, val); 364 case hwmon_in_lcrit_alarm: 365 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 366 LTC4283_UV_MASK, val); 367 case hwmon_in_fault: 368 /* 369 * We report failure if we detect either a fer_bad or a 370 * fet_short in the status register. 371 */ 372 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 373 LTC4283_FET_BAD_MASK | LTC4283_FET_SHORT_MASK, val); 374 case hwmon_in_enable: 375 *val = test_bit(channel, &st->ch_enable_mask); 376 return 0; 377 default: 378 return -EOPNOTSUPP; 379 } 380 return 0; 381 } 382 383 static int ltc4283_read_current_word(const struct ltc4283_hwmon *st, u32 reg, 384 long *val) 385 { 386 u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; 387 unsigned int __raw; 388 int ret; 389 390 ret = regmap_read(st->map, reg, &__raw); 391 if (ret) 392 return ret; 393 394 *val = DIV64_U64_ROUND_CLOSEST(__raw * temp, 395 BIT_ULL(16) * st->rsense); 396 397 return 0; 398 } 399 400 static int ltc4283_read_current_byte(const struct ltc4283_hwmon *st, u32 reg, 401 long *val) 402 { 403 u64 temp = (u64)LTC4283_ADC1_FS_uV * DECA * MILLI; 404 u32 curr; 405 int ret; 406 407 ret = regmap_read(st->map, reg, &curr); 408 if (ret) 409 return ret; 410 411 *val = DIV_ROUND_CLOSEST_ULL(curr * temp, BIT(8) * st->rsense); 412 return 0; 413 } 414 415 static int ltc4283_read_curr(struct ltc4283_hwmon *st, u32 attr, long *val) 416 { 417 switch (attr) { 418 case hwmon_curr_input: 419 return ltc4283_read_current_word(st, LTC4283_SENSE, val); 420 case hwmon_curr_highest: 421 return ltc4283_read_current_word(st, LTC4283_SENSE_MAX, val); 422 case hwmon_curr_lowest: 423 return ltc4283_read_current_word(st, LTC4283_SENSE_MIN, val); 424 case hwmon_curr_max: 425 return ltc4283_read_current_byte(st, LTC4283_SENSE_MAX_TH, val); 426 case hwmon_curr_min: 427 return ltc4283_read_current_byte(st, LTC4283_SENSE_MIN_TH, val); 428 case hwmon_curr_max_alarm: 429 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 430 LTC4283_SENSE_HIGH_ALM, val); 431 case hwmon_curr_min_alarm: 432 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 433 LTC4283_SENSE_LOW_ALM, val); 434 case hwmon_curr_crit_alarm: 435 return ltc4283_read_alarm(st, LTC4283_FAULT_STATUS, 436 LTC4283_OC_MASK, val); 437 default: 438 return -EOPNOTSUPP; 439 } 440 } 441 442 static int ltc4283_read_power_word(const struct ltc4283_hwmon *st, 443 u32 reg, long *val) 444 { 445 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 446 unsigned int __raw; 447 int ret; 448 449 ret = regmap_read(st->map, reg, &__raw); 450 if (ret) 451 return ret; 452 453 /* 454 * Power is given by: 455 * P = CODE(16b) * 32.768mV * 2.048V / (2^16 * Rsense) 456 */ 457 *val = DIV64_U64_ROUND_CLOSEST(temp * __raw, BIT_ULL(16) * st->rsense); 458 459 return 0; 460 } 461 462 static int ltc4283_read_power_byte(const struct ltc4283_hwmon *st, 463 u32 reg, long *val) 464 { 465 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 466 u32 power; 467 int ret; 468 469 ret = regmap_read(st->map, reg, &power); 470 if (ret) 471 return ret; 472 473 *val = DIV_ROUND_CLOSEST_ULL(power * temp, BIT(8) * st->rsense); 474 475 return 0; 476 } 477 478 static int ltc4283_read_power(struct ltc4283_hwmon *st, u32 attr, long *val) 479 { 480 switch (attr) { 481 case hwmon_power_input: 482 return ltc4283_read_power_word(st, LTC4283_POWER, val); 483 case hwmon_power_input_highest: 484 return ltc4283_read_power_word(st, LTC4283_POWER_MAX, val); 485 case hwmon_power_input_lowest: 486 return ltc4283_read_power_word(st, LTC4283_POWER_MIN, val); 487 case hwmon_power_max_alarm: 488 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 489 LTC4283_POWER_HIGH_ALM, val); 490 case hwmon_power_min_alarm: 491 return ltc4283_read_alarm(st, LTC4283_ADC_ALM_LOG_1, 492 LTC4283_POWER_LOW_ALM, val); 493 case hwmon_power_max: 494 return ltc4283_read_power_byte(st, LTC4283_POWER_MAX_TH, val); 495 case hwmon_power_min: 496 return ltc4283_read_power_byte(st, LTC4283_POWER_MIN_TH, val); 497 default: 498 return -EOPNOTSUPP; 499 } 500 } 501 502 static int ltc4283_read_energy(struct ltc4283_hwmon *st, u32 attr, s64 *val) 503 { 504 u64 temp = LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV, energy; 505 u8 raw[8] = {}; 506 int ret; 507 508 if (!st->energy_en) 509 return -ENODATA; 510 511 ret = i2c_smbus_read_i2c_block_data(st->client, LTC4283_ENERGY, 6, raw); 512 if (ret < 0) 513 return ret; 514 if (ret != 6) 515 return -EIO; 516 517 energy = get_unaligned_be64(raw) >> 16; 518 519 /* 520 * The formula for energy is given by: 521 * E = CODE(48b) * 32.768mV * 2.048V * Tconv / 2^24 * Rsense 522 * 523 * As Rsense can have tenths of micro-ohm resolution, we need to 524 * multiply by DECA to get microjoule. 525 */ 526 527 /* 528 * Use mul_u64_u64_div_u64() to handle the 128-bit intermediate 529 * product of energy (up to 48 bits) * temp * Tconv without overflow. 530 * Multiply rsense by CENTI to convert from tenths-of-microohm back 531 * to nanoohm so the result comes out in microjoule. 532 */ 533 energy = mul_u64_u64_div_u64(energy, temp * LTC4283_TCONV_uS, 534 BIT_ULL(24) * st->rsense * CENTI); 535 536 *val = energy; 537 return 0; 538 } 539 540 static int ltc4283_read(struct device *dev, enum hwmon_sensor_types type, 541 u32 attr, int channel, long *val) 542 { 543 struct ltc4283_hwmon *st = dev_get_drvdata(dev); 544 545 switch (type) { 546 case hwmon_in: 547 return ltc4283_read_in(st, attr, channel, val); 548 case hwmon_curr: 549 return ltc4283_read_curr(st, attr, val); 550 case hwmon_power: 551 return ltc4283_read_power(st, attr, val); 552 case hwmon_energy: 553 *val = st->energy_en; 554 return 0; 555 case hwmon_energy64: 556 return ltc4283_read_energy(st, attr, (s64 *)val); 557 default: 558 return -EOPNOTSUPP; 559 } 560 } 561 562 static int ltc4283_write_power_byte(const struct ltc4283_hwmon *st, u32 reg, 563 long val) 564 { 565 u64 temp = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 566 u32 __raw; 567 568 val = clamp_val(val, 0, st->power_max); 569 __raw = DIV64_U64_ROUND_CLOSEST(val * BIT_ULL(8) * st->rsense, temp); 570 571 return regmap_write(st->map, reg, __raw); 572 } 573 574 static int ltc4283_write_power_word(const struct ltc4283_hwmon *st, 575 u32 reg, unsigned long val) 576 { 577 u64 divisor = (u64)LTC4283_ADC1_FS_uV * LTC4283_ADC2_FS_mV * DECA * MILLI; 578 u16 __raw; 579 580 __raw = mul_u64_u64_div_u64(val, st->rsense * BIT_ULL(16), divisor); 581 582 return regmap_write(st->map, reg, __raw); 583 } 584 585 static int ltc4283_reset_power_hist(struct ltc4283_hwmon *st) 586 { 587 int ret; 588 589 ret = ltc4283_write_power_word(st, LTC4283_POWER_MIN, st->power_max); 590 if (ret) 591 return ret; 592 593 ret = ltc4283_write_power_word(st, LTC4283_POWER_MAX, 0); 594 if (ret) 595 return ret; 596 597 /* Clear possible power faults. */ 598 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 599 LTC4283_PWR_FAIL_FAULT_MASK | LTC4283_PGI_FAULT_MASK); 600 } 601 602 static int ltc4283_write_power(struct ltc4283_hwmon *st, u32 attr, long val) 603 { 604 switch (attr) { 605 case hwmon_power_max: 606 return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, val); 607 case hwmon_power_min: 608 return ltc4283_write_power_byte(st, LTC4283_POWER_MIN_TH, val); 609 case hwmon_power_reset_history: 610 return ltc4283_reset_power_hist(st); 611 default: 612 return -EOPNOTSUPP; 613 } 614 } 615 616 static int ltc4283_write_in_history(struct ltc4283_hwmon *st, u32 reg, 617 long lowest, u32 fs) 618 { 619 u32 __raw; 620 int ret; 621 622 __raw = DIV_ROUND_CLOSEST(BIT(16) * lowest, fs); 623 if (__raw == BIT(16)) 624 __raw = U16_MAX; 625 626 ret = regmap_write(st->map, reg, __raw); 627 if (ret) 628 return ret; 629 630 return regmap_write(st->map, reg + 1, 0); 631 } 632 633 static int ltc4283_write_in_byte(const struct ltc4283_hwmon *st, 634 u32 reg, u32 fs, long val) 635 { 636 u32 __raw; 637 638 val = clamp_val(val, 0, fs); 639 __raw = DIV_ROUND_CLOSEST(val * BIT(8), fs); 640 if (__raw == BIT(8)) 641 __raw = U8_MAX; 642 643 return regmap_write(st->map, reg, __raw); 644 } 645 646 static int ltc4283_reset_in_hist(struct ltc4283_hwmon *st, u32 channel) 647 { 648 u32 reg, fs; 649 int ret; 650 651 /* 652 * Make sure to clear possible under/over voltage faults. Otherwise the 653 * chip won't latch on again. 654 */ 655 if (channel == LTC4283_CHAN_VIN) 656 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 657 LTC4283_OV_FAULT_MASK | LTC4283_UV_FAULT_MASK); 658 659 if (channel == LTC4283_CHAN_VPWR) 660 return ltc4283_write_in_history(st, LTC4283_VPWR_MIN, 661 LTC4283_ADC2_FS_mV, 662 LTC4283_ADC2_FS_mV); 663 664 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) { 665 fs = LTC4283_ADC2_FS_mV; 666 reg = LTC4283_ADC_2_MIN(channel - LTC4283_CHAN_ADI_1); 667 } else { 668 fs = LTC4283_ADC1_FS_uV; 669 reg = LTC4283_ADC_2_MIN_DIFF(channel - LTC4283_CHAN_ADIN12); 670 } 671 672 ret = ltc4283_write_in_history(st, reg, fs, fs); 673 if (ret) 674 return ret; 675 if (channel != LTC4283_CHAN_DRAIN) 676 return 0; 677 678 /* Then, let's also clear possible fet faults. Same as above. */ 679 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 680 LTC4283_FET_BAD_FAULT_MASK | LTC4283_FET_SHORT_FAULT_MASK); 681 } 682 683 static int ltc4283_write_in_en(struct ltc4283_hwmon *st, u32 channel, bool en) 684 { 685 unsigned int bit, adc_idx = channel - LTC4283_CHAN_ADI_1; 686 unsigned int reg = LTC4283_ADC_SELECT(adc_idx); 687 int ret; 688 689 bit = LTC4283_ADC_SELECT_MASK(adc_idx); 690 if (channel > LTC4283_CHAN_DRAIN) 691 /* Account for two reserved fields after DRAIN. */ 692 bit <<= 2; 693 694 if (en) 695 ret = regmap_set_bits(st->map, reg, bit); 696 else 697 ret = regmap_clear_bits(st->map, reg, bit); 698 if (ret) 699 return ret; 700 701 __assign_bit(channel, &st->ch_enable_mask, en); 702 return 0; 703 } 704 705 static int ltc4283_write_minmax(struct ltc4283_hwmon *st, long val, 706 u32 channel, bool is_max) 707 { 708 u32 reg; 709 710 if (channel == LTC4283_CHAN_VPWR) { 711 if (is_max) 712 return ltc4283_write_in_byte(st, LTC4283_VPWR_MAX_TH, 713 LTC4283_ADC2_FS_mV, val); 714 715 return ltc4283_write_in_byte(st, LTC4283_VPWR_MIN_TH, 716 LTC4283_ADC2_FS_mV, val); 717 } 718 719 if (channel >= LTC4283_CHAN_ADI_1 && channel <= LTC4283_CHAN_DRAIN) { 720 if (is_max) { 721 reg = LTC4283_ADC_2_MAX_TH(channel - LTC4283_CHAN_ADI_1); 722 return ltc4283_write_in_byte(st, reg, 723 LTC4283_ADC2_FS_mV, val); 724 } 725 726 reg = LTC4283_ADC_2_MIN_TH(channel - LTC4283_CHAN_ADI_1); 727 return ltc4283_write_in_byte(st, reg, LTC4283_ADC2_FS_mV, val); 728 } 729 730 /* Clamp before multiplying to avoid overflow on any arch. */ 731 val = clamp_val(val, 0, LONG_MAX / MILLI); 732 733 if (is_max) { 734 reg = LTC4283_ADC_2_MAX_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 735 return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, 736 val * MILLI); 737 } 738 739 reg = LTC4283_ADC_2_MIN_TH_DIFF(channel - LTC4283_CHAN_ADIN12); 740 return ltc4283_write_in_byte(st, reg, LTC4283_ADC1_FS_uV, val * MILLI); 741 } 742 743 static int ltc4283_write_in(struct ltc4283_hwmon *st, u32 attr, long val, 744 int channel) 745 { 746 switch (attr) { 747 case hwmon_in_max: 748 return ltc4283_write_minmax(st, val, channel, true); 749 case hwmon_in_min: 750 return ltc4283_write_minmax(st, val, channel, false); 751 case hwmon_in_reset_history: 752 return ltc4283_reset_in_hist(st, channel); 753 case hwmon_in_enable: 754 return ltc4283_write_in_en(st, channel, !!val); 755 default: 756 return -EOPNOTSUPP; 757 } 758 } 759 760 static int ltc4283_write_curr_byte(const struct ltc4283_hwmon *st, 761 u32 reg, long val) 762 { 763 u32 temp = LTC4283_ADC1_FS_uV * DECA * MILLI; 764 u32 reg_val, isense_max; 765 766 isense_max = DIV_ROUND_CLOSEST(st->vsense_max * MICRO * DECA, st->rsense); 767 val = clamp_val(val, 0, isense_max); 768 reg_val = DIV_ROUND_CLOSEST_ULL(val * BIT_ULL(8) * st->rsense, temp); 769 770 return regmap_write(st->map, reg, reg_val); 771 } 772 773 static int ltc4283_write_curr_history(struct ltc4283_hwmon *st) 774 { 775 int ret; 776 777 ret = ltc4283_write_in_history(st, LTC4283_SENSE_MIN, 778 st->vsense_max * MILLI, 779 LTC4283_ADC1_FS_uV); 780 if (ret) 781 return ret; 782 783 /* Now, let's also clear possible overcurrent logs. */ 784 return regmap_clear_bits(st->map, LTC4283_FAULT_LOG, 785 LTC4283_OC_FAULT_MASK); 786 } 787 788 static int ltc4283_write_curr(struct ltc4283_hwmon *st, u32 attr, long val) 789 { 790 switch (attr) { 791 case hwmon_curr_max: 792 return ltc4283_write_curr_byte(st, LTC4283_SENSE_MAX_TH, val); 793 case hwmon_curr_min: 794 return ltc4283_write_curr_byte(st, LTC4283_SENSE_MIN_TH, val); 795 case hwmon_curr_reset_history: 796 return ltc4283_write_curr_history(st); 797 default: 798 return -EOPNOTSUPP; 799 } 800 } 801 802 static int ltc4283_energy_enable_set(struct ltc4283_hwmon *st, long val) 803 { 804 int ret; 805 806 /* Setting the bit halts the meter. */ 807 val = !!val; 808 ret = regmap_update_bits(st->map, LTC4283_METER_CONTROL, 809 LTC4283_METER_HALT_MASK, 810 FIELD_PREP(LTC4283_METER_HALT_MASK, !val)); 811 if (ret) 812 return ret; 813 814 st->energy_en = val; 815 816 return 0; 817 } 818 819 static int ltc4283_write(struct device *dev, enum hwmon_sensor_types type, 820 u32 attr, int channel, long val) 821 { 822 struct ltc4283_hwmon *st = dev_get_drvdata(dev); 823 824 switch (type) { 825 case hwmon_power: 826 return ltc4283_write_power(st, attr, val); 827 case hwmon_in: 828 return ltc4283_write_in(st, attr, val, channel); 829 case hwmon_curr: 830 return ltc4283_write_curr(st, attr, val); 831 case hwmon_energy: 832 return ltc4283_energy_enable_set(st, val); 833 default: 834 return -EOPNOTSUPP; 835 } 836 } 837 838 static umode_t ltc4283_in_is_visible(const struct ltc4283_hwmon *st, 839 u32 attr, int channel) 840 { 841 /* If ADIO is set as a GPIO, don´t make it visible. */ 842 if (channel >= LTC4283_CHAN_ADIO_1 && channel <= LTC4283_CHAN_ADIO_4) { 843 /* ADIOX pins come at index 0 in the gpio mask. */ 844 channel -= LTC4283_CHAN_ADIO_1; 845 if (test_bit(channel, &st->gpio_mask)) 846 return 0; 847 } 848 849 /* Also take care of differential channels. */ 850 if (channel >= LTC4283_CHAN_ADIO12 && channel <= LTC4283_CHAN_ADIO34) { 851 channel -= LTC4283_CHAN_ADIO12; 852 /* If one channel in the pair is used, make it invisible. */ 853 if (test_bit(channel * 2, &st->gpio_mask) || 854 test_bit(channel * 2 + 1, &st->gpio_mask)) 855 return 0; 856 } 857 858 switch (attr) { 859 case hwmon_in_input: 860 case hwmon_in_highest: 861 case hwmon_in_lowest: 862 case hwmon_in_max_alarm: 863 case hwmon_in_min_alarm: 864 case hwmon_in_label: 865 case hwmon_in_lcrit_alarm: 866 case hwmon_in_crit_alarm: 867 case hwmon_in_fault: 868 return 0444; 869 case hwmon_in_max: 870 case hwmon_in_min: 871 case hwmon_in_enable: 872 return 0644; 873 case hwmon_in_reset_history: 874 return 0200; 875 default: 876 return 0; 877 } 878 } 879 880 static umode_t ltc4283_curr_is_visible(u32 attr) 881 { 882 switch (attr) { 883 case hwmon_curr_input: 884 case hwmon_curr_highest: 885 case hwmon_curr_lowest: 886 case hwmon_curr_max_alarm: 887 case hwmon_curr_min_alarm: 888 case hwmon_curr_crit_alarm: 889 case hwmon_curr_label: 890 return 0444; 891 case hwmon_curr_max: 892 case hwmon_curr_min: 893 return 0644; 894 case hwmon_curr_reset_history: 895 return 0200; 896 default: 897 return 0; 898 } 899 } 900 901 static umode_t ltc4283_power_is_visible(u32 attr) 902 { 903 switch (attr) { 904 case hwmon_power_input: 905 case hwmon_power_input_highest: 906 case hwmon_power_input_lowest: 907 case hwmon_power_label: 908 case hwmon_power_max_alarm: 909 case hwmon_power_min_alarm: 910 return 0444; 911 case hwmon_power_max: 912 case hwmon_power_min: 913 return 0644; 914 case hwmon_power_reset_history: 915 return 0200; 916 default: 917 return 0; 918 } 919 } 920 921 static umode_t ltc4283_is_visible(const void *data, 922 enum hwmon_sensor_types type, 923 u32 attr, int channel) 924 { 925 switch (type) { 926 case hwmon_in: 927 return ltc4283_in_is_visible(data, attr, channel); 928 case hwmon_curr: 929 return ltc4283_curr_is_visible(attr); 930 case hwmon_power: 931 return ltc4283_power_is_visible(attr); 932 case hwmon_energy: 933 /* hwmon_energy_enable */ 934 return 0644; 935 case hwmon_energy64: 936 /* hwmon_energy_input */ 937 return 0444; 938 default: 939 return 0; 940 } 941 } 942 943 static const char * const ltc4283_in_strs[] = { 944 "VIN", "VPWR", "VADI1", "VADI2", "VADI3", "VADI4", "VADIO1", "VADIO2", 945 "VADIO3", "VADIO4", "DRNS", "DRAIN", "ADIN2-ADIN1", "ADIN4-ADIN3", 946 "ADIO2-ADIO1", "ADIO4-ADIO3" 947 }; 948 949 static int ltc4283_read_labels(struct device *dev, 950 enum hwmon_sensor_types type, 951 u32 attr, int channel, const char **str) 952 { 953 switch (type) { 954 case hwmon_in: 955 *str = ltc4283_in_strs[channel]; 956 return 0; 957 case hwmon_curr: 958 *str = "ISENSE"; 959 return 0; 960 case hwmon_power: 961 *str = "Power"; 962 return 0; 963 default: 964 return -EOPNOTSUPP; 965 } 966 } 967 968 /* 969 * Set max limits for ISENSE and Power as that depends on the max voltage on 970 * rsense that is defined in ILIM_ADJUST. This is specially important for power 971 * because for some rsense and vfsout values, if we allow the default raw 255 972 * value, that would overflow long in 32bit archs when reading back the max 973 * power limit. 974 */ 975 static int ltc4283_set_max_limits(struct ltc4283_hwmon *st, struct device *dev) 976 { 977 u32 temp = st->vsense_max * DECA * MICRO; 978 int ret; 979 980 ret = ltc4283_write_in_byte(st, LTC4283_SENSE_MAX_TH, LTC4283_ADC1_FS_uV, 981 st->vsense_max * MILLI); 982 if (ret) 983 return ret; 984 985 /* Power is given by ISENSE * Vout. */ 986 st->power_max = DIV_ROUND_CLOSEST(temp, st->rsense) * LTC4283_ADC2_FS_mV; 987 return ltc4283_write_power_byte(st, LTC4283_POWER_MAX_TH, st->power_max); 988 } 989 990 static int ltc4283_parse_array_prop(const struct ltc4283_hwmon *st, 991 struct device *dev, const char *prop, 992 const u32 *vals, u32 n_vals) 993 { 994 u32 prop_val; 995 int ret; 996 u32 i; 997 998 ret = device_property_read_u32(dev, prop, &prop_val); 999 if (ret) 1000 return n_vals; 1001 1002 for (i = 0; i < n_vals; i++) { 1003 if (prop_val != vals[i]) 1004 continue; 1005 1006 return i; 1007 } 1008 1009 return dev_err_probe(dev, -EINVAL, 1010 "Invalid %s property value %u\n", prop, prop_val); 1011 } 1012 1013 static int ltc4283_get_defaults(struct ltc4283_hwmon *st) 1014 { 1015 u32 reg_val, ilm_adjust, c; 1016 int ret; 1017 1018 ret = regmap_read(st->map, LTC4283_METER_CONTROL, ®_val); 1019 if (ret) 1020 return ret; 1021 1022 st->energy_en = !FIELD_GET(LTC4283_METER_HALT_MASK, reg_val); 1023 1024 ret = regmap_read(st->map, LTC4283_CONFIG_1, ®_val); 1025 if (ret) 1026 return ret; 1027 1028 ilm_adjust = FIELD_GET(LTC4283_ILIM_MASK, reg_val); 1029 st->vsense_max = LTC4283_VILIM_MIN_uV / MILLI + ilm_adjust; 1030 1031 ret = regmap_read(st->map, LTC4283_PGIO_CONFIG, ®_val); 1032 if (ret) 1033 return ret; 1034 1035 /* Can be latter overwritten in ltc4283_pgio_config() */ 1036 if (FIELD_GET(LTC4283_PGIO4_CFG_MASK, reg_val) < LTC4283_PGIO_FUNC_GPIO) 1037 st->ext_fault = true; 1038 1039 /* VPWR and VIN are always enabled */ 1040 __set_bit(LTC4283_CHAN_VIN, &st->ch_enable_mask); 1041 __set_bit(LTC4283_CHAN_VPWR, &st->ch_enable_mask); 1042 for (c = LTC4283_CHAN_ADI_1; c < LTC4283_CHAN_MAX; c++) { 1043 u32 chan = c - LTC4283_CHAN_ADI_1, bit; 1044 1045 ret = regmap_read(st->map, LTC4283_ADC_SELECT(chan), ®_val); 1046 if (ret) 1047 return ret; 1048 1049 bit = LTC4283_ADC_SELECT_MASK(chan); 1050 if (c > LTC4283_CHAN_DRAIN) 1051 /* account for two reserved fields after DRAIN */ 1052 bit <<= 2; 1053 1054 if (!(bit & reg_val)) 1055 continue; 1056 1057 __set_bit(c, &st->ch_enable_mask); 1058 } 1059 1060 return 0; 1061 } 1062 1063 static const char * const ltc4283_pgio1_funcs[] = { 1064 "inverted_power_good", "power_good", "gpio" 1065 }; 1066 1067 static const char * const ltc4283_pgio2_funcs[] = { 1068 "inverted_power_good", "power_good", "gpio", "active_current_limiting" 1069 }; 1070 1071 static const char * const ltc4283_pgio3_funcs[] = { 1072 "inverted_power_good_input", "power_good_input", "gpio" 1073 }; 1074 1075 static const char * const ltc4283_pgio4_funcs[] = { 1076 "inverted_external_fault", "external_fault", "gpio" 1077 }; 1078 1079 enum { 1080 LTC4283_PIN_ADIO1, 1081 LTC4283_PIN_ADIO2, 1082 LTC4283_PIN_ADIO3, 1083 LTC4283_PIN_ADIO4, 1084 LTC4283_PIN_PGIO1, 1085 LTC4283_PIN_PGIO2, 1086 LTC4283_PIN_PGIO3, 1087 LTC4283_PIN_PGIO4, 1088 }; 1089 1090 static int ltc4283_pgio_config(struct ltc4283_hwmon *st, struct device *dev) 1091 { 1092 int ret, func; 1093 1094 func = device_property_match_property_string(dev, "adi,pgio1-func", 1095 ltc4283_pgio1_funcs, 1096 ARRAY_SIZE(ltc4283_pgio1_funcs)); 1097 if (func < 0 && func != -EINVAL) 1098 return dev_err_probe(dev, func, 1099 "Invalid adi,pgio1-func property\n"); 1100 if (func >= 0) { 1101 if (func == LTC4283_PGIO_FUNC_GPIO) { 1102 __set_bit(LTC4283_PIN_PGIO1, &st->gpio_mask); 1103 /* If GPIO, default to an input pin. */ 1104 func++; 1105 } 1106 1107 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1108 LTC4283_PGIO1_CFG_MASK, 1109 FIELD_PREP(LTC4283_PGIO1_CFG_MASK, func)); 1110 if (ret) 1111 return ret; 1112 } 1113 1114 func = device_property_match_property_string(dev, "adi,pgio2-func", 1115 ltc4283_pgio2_funcs, 1116 ARRAY_SIZE(ltc4283_pgio2_funcs)); 1117 1118 if (func < 0 && func != -EINVAL) 1119 return dev_err_probe(dev, func, 1120 "Invalid adi,pgio2-func property\n"); 1121 if (func >= 0) { 1122 if (func != LTC4283_PGIO2_FUNC_ACLB) { 1123 if (func == LTC4283_PGIO_FUNC_GPIO) { 1124 __set_bit(LTC4283_PIN_PGIO2, &st->gpio_mask); 1125 func++; 1126 } 1127 1128 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1129 LTC4283_PGIO2_CFG_MASK, 1130 FIELD_PREP(LTC4283_PGIO2_CFG_MASK, func)); 1131 } else { 1132 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, 1133 LTC4283_PIGIO2_ACLB_MASK); 1134 } 1135 1136 if (ret) 1137 return ret; 1138 } 1139 1140 func = device_property_match_property_string(dev, "adi,pgio3-func", 1141 ltc4283_pgio3_funcs, 1142 ARRAY_SIZE(ltc4283_pgio3_funcs)); 1143 1144 if (func < 0 && func != -EINVAL) 1145 return dev_err_probe(dev, func, 1146 "Invalid adi,pgio3-func property\n"); 1147 if (func >= 0) { 1148 if (func == LTC4283_PGIO_FUNC_GPIO) { 1149 __set_bit(LTC4283_PIN_PGIO3, &st->gpio_mask); 1150 func++; 1151 } 1152 1153 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1154 LTC4283_PGIO3_CFG_MASK, 1155 FIELD_PREP(LTC4283_PGIO3_CFG_MASK, func)); 1156 if (ret) 1157 return ret; 1158 } 1159 1160 func = device_property_match_property_string(dev, "adi,pgio4-func", 1161 ltc4283_pgio4_funcs, 1162 ARRAY_SIZE(ltc4283_pgio4_funcs)); 1163 1164 if (func < 0 && func != -EINVAL) 1165 return dev_err_probe(dev, func, 1166 "Invalid adi,pgio4-func property\n"); 1167 if (func >= 0) { 1168 if (func == LTC4283_PGIO_FUNC_GPIO) { 1169 __set_bit(LTC4283_PIN_PGIO4, &st->gpio_mask); 1170 func++; 1171 st->ext_fault = false; 1172 } else { 1173 st->ext_fault = true; 1174 } 1175 1176 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG, 1177 LTC4283_PGIO4_CFG_MASK, 1178 FIELD_PREP(LTC4283_PGIO4_CFG_MASK, func)); 1179 if (ret) 1180 return ret; 1181 } 1182 1183 return 0; 1184 } 1185 1186 static int ltc4283_adio_config(struct ltc4283_hwmon *st, struct device *dev, 1187 const char *prop, u32 pin) 1188 { 1189 u32 adc_idx; 1190 int ret; 1191 1192 if (!device_property_read_bool(dev, prop)) 1193 return 0; 1194 1195 adc_idx = LTC4283_CHAN_ADIO_1 - LTC4283_CHAN_ADI_1 + pin; 1196 ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(adc_idx), 1197 LTC4283_ADC_SELECT_MASK(adc_idx)); 1198 if (ret) 1199 return ret; 1200 1201 __set_bit(pin, &st->gpio_mask); 1202 return 0; 1203 } 1204 1205 static int ltc4283_pin_config(struct ltc4283_hwmon *st, struct device *dev) 1206 { 1207 int ret; 1208 1209 ret = ltc4283_pgio_config(st, dev); 1210 if (ret) 1211 return ret; 1212 1213 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio1", LTC4283_PIN_ADIO1); 1214 if (ret) 1215 return ret; 1216 1217 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio2", LTC4283_PIN_ADIO2); 1218 if (ret) 1219 return ret; 1220 1221 ret = ltc4283_adio_config(st, dev, "adi,gpio-on-adio3", LTC4283_PIN_ADIO3); 1222 if (ret) 1223 return ret; 1224 1225 return ltc4283_adio_config(st, dev, "adi,gpio-on-adio4", LTC4283_PIN_ADIO4); 1226 } 1227 1228 static const char * const ltc4283_oc_fet_retry[] = { 1229 "latch-off", "1", "7", "unlimited" 1230 }; 1231 1232 static const u32 ltc4283_fb_factor[] = { 1233 100, 50, 20, 10 1234 }; 1235 1236 static const u32 ltc4283_cooling_dl[] = { 1237 512, 1002, 2005, 4100, 8190, 16400, 32800, 65600 1238 }; 1239 1240 static const u32 ltc4283_fet_bad_delay[] = { 1241 256, 512, 1002, 2005 1242 }; 1243 1244 static int ltc4283_setup(struct ltc4283_hwmon *st, struct device *dev) 1245 { 1246 u32 val; 1247 int ret; 1248 1249 /* The part has an eeprom so let's get the needed defaults from it */ 1250 ret = ltc4283_get_defaults(st); 1251 if (ret) 1252 return ret; 1253 1254 /* 1255 * Default to LTC4283_MIN_RSENSE so we can probe without FW properties. 1256 */ 1257 st->rsense = LTC4283_MIN_RSENSE; 1258 ret = device_property_read_u32(dev, "adi,rsense-nano-ohms", 1259 &st->rsense); 1260 if (!ret) { 1261 if (st->rsense < LTC4283_MIN_RSENSE || st->rsense > LTC4283_MAX_RSENSE) 1262 return dev_err_probe(dev, -EINVAL, 1263 "adi,rsense-nano-ohms(%u) too small or too large [%u %u]\n", 1264 st->rsense, LTC4283_MIN_RSENSE, LTC4283_MAX_RSENSE); 1265 } 1266 1267 /* 1268 * The resolution for rsense is tenths of micro (eg: 62.5 uOhm) which 1269 * means we need nano in the bindings. However, to make things easier to 1270 * handle (with respect to overflows) we divide it by 100 as we don't 1271 * really need the last two digits. 1272 */ 1273 st->rsense /= CENTI; 1274 1275 ret = device_property_read_u32(dev, "adi,current-limit-sense-microvolt", 1276 &st->vsense_max); 1277 if (!ret) { 1278 u32 reg_val; 1279 1280 if (!in_range(st->vsense_max, LTC4283_VILIM_MIN_uV, 1281 LTC4283_VILIM_RANGE)) { 1282 return dev_err_probe(dev, -EINVAL, 1283 "adi,current-limit-sense-microvolt (%u) out of range [%u %u]\n", 1284 st->vsense_max, LTC4283_VILIM_MIN_uV, 1285 LTC4283_VILIM_MAX_uV); 1286 } 1287 1288 st->vsense_max /= MILLI; 1289 reg_val = FIELD_PREP(LTC4283_ILIM_MASK, 1290 st->vsense_max - LTC4283_VILIM_MIN_uV / MILLI); 1291 ret = regmap_update_bits(st->map, LTC4283_CONFIG_1, 1292 LTC4283_ILIM_MASK, reg_val); 1293 if (ret) 1294 return ret; 1295 } 1296 1297 ret = ltc4283_parse_array_prop(st, dev, "adi,current-limit-foldback-factor", 1298 ltc4283_fb_factor, ARRAY_SIZE(ltc4283_fb_factor)); 1299 if (ret < 0) 1300 return ret; 1301 if (ret < ARRAY_SIZE(ltc4283_fb_factor)) { 1302 ret = regmap_update_bits(st->map, LTC4283_CONFIG_1, LTC4283_FB_MASK, 1303 FIELD_PREP(LTC4283_FB_MASK, ret)); 1304 if (ret) 1305 return ret; 1306 } 1307 1308 ret = ltc4283_parse_array_prop(st, dev, "adi,cooling-delay-ms", 1309 ltc4283_cooling_dl, ARRAY_SIZE(ltc4283_cooling_dl)); 1310 if (ret < 0) 1311 return ret; 1312 if (ret < ARRAY_SIZE(ltc4283_cooling_dl)) { 1313 ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_COOLING_DL_MASK, 1314 FIELD_PREP(LTC4283_COOLING_DL_MASK, ret)); 1315 if (ret) 1316 return ret; 1317 } 1318 1319 ret = ltc4283_parse_array_prop(st, dev, "adi,fet-bad-timer-delay-ms", 1320 ltc4283_fet_bad_delay, ARRAY_SIZE(ltc4283_fet_bad_delay)); 1321 if (ret < 0) 1322 return ret; 1323 if (ret < ARRAY_SIZE(ltc4283_fet_bad_delay)) { 1324 ret = regmap_update_bits(st->map, LTC4283_CONFIG_2, LTC4283_FTBD_DL_MASK, 1325 FIELD_PREP(LTC4283_FTBD_DL_MASK, ret)); 1326 if (ret) 1327 return ret; 1328 } 1329 1330 ret = ltc4283_set_max_limits(st, dev); 1331 if (ret) 1332 return ret; 1333 1334 ret = ltc4283_pin_config(st, dev); 1335 if (ret) 1336 return ret; 1337 1338 if (device_property_read_bool(dev, "adi,power-good-reset-on-fet")) { 1339 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1340 LTC4283_PWRGD_RST_CTRL_MASK); 1341 if (ret) 1342 return ret; 1343 } 1344 1345 if (device_property_read_bool(dev, "adi,fet-turn-off-disable")) { 1346 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1347 LTC4283_FET_BAD_OFF_MASK); 1348 if (ret) 1349 return ret; 1350 } 1351 1352 if (device_property_read_bool(dev, "adi,tmr-pull-down-disable")) { 1353 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, 1354 LTC4283_THERM_TMR_MASK); 1355 if (ret) 1356 return ret; 1357 } 1358 1359 if (device_property_read_bool(dev, "adi,dvdt-inrush-control-disable")) { 1360 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_1, 1361 LTC4283_DVDT_MASK); 1362 if (ret) 1363 return ret; 1364 } 1365 1366 if (device_property_read_bool(dev, "adi,undervoltage-retry-disable")) { 1367 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2, 1368 LTC4283_UV_RETRY_MASK); 1369 if (ret) 1370 return ret; 1371 } 1372 1373 if (device_property_read_bool(dev, "adi,overvoltage-retry-disable")) { 1374 ret = regmap_clear_bits(st->map, LTC4283_CONTROL_2, 1375 LTC4283_OV_RETRY_MASK); 1376 if (ret) 1377 return ret; 1378 } 1379 1380 if (device_property_read_bool(dev, "adi,external-fault-retry-enable")) { 1381 if (!st->ext_fault) 1382 return dev_err_probe(dev, -EINVAL, 1383 "adi,external-fault-retry-enable set but PGIO4 not configured\n"); 1384 ret = regmap_set_bits(st->map, LTC4283_CONTROL_2, 1385 LTC4283_EXT_FAULT_RETRY_MASK); 1386 if (ret) 1387 return ret; 1388 } 1389 1390 if (device_property_read_bool(dev, "adi,fault-log-enable")) { 1391 ret = regmap_set_bits(st->map, LTC4283_FAULT_LOG_CTRL, 1392 LTC4283_FAULT_LOG_EN_MASK); 1393 if (ret) 1394 return ret; 1395 } 1396 1397 ret = device_property_match_property_string(dev, "adi,overcurrent-retries", 1398 ltc4283_oc_fet_retry, 1399 ARRAY_SIZE(ltc4283_oc_fet_retry)); 1400 /* We still want to catch when an invalid string is given. */ 1401 if (ret < 0 && ret != -EINVAL) 1402 return dev_err_probe(dev, ret, 1403 "adi,overcurrent-retries invalid value\n"); 1404 if (ret >= 0) { 1405 ret = regmap_update_bits(st->map, LTC4283_CONTROL_2, 1406 LTC4283_OC_RETRY_MASK, 1407 FIELD_PREP(LTC4283_OC_RETRY_MASK, ret)); 1408 if (ret) 1409 return ret; 1410 } 1411 1412 ret = device_property_match_property_string(dev, "adi,fet-bad-retries", 1413 ltc4283_oc_fet_retry, 1414 ARRAY_SIZE(ltc4283_oc_fet_retry)); 1415 if (ret < 0 && ret != -EINVAL) 1416 return dev_err_probe(dev, ret, 1417 "adi,fet-bad-retries invalid value\n"); 1418 if (ret >= 0) { 1419 ret = regmap_update_bits(st->map, LTC4283_CONTROL_2, 1420 LTC4283_FET_BAD_RETRY_MASK, 1421 FIELD_PREP(LTC4283_FET_BAD_RETRY_MASK, ret)); 1422 if (ret) 1423 return ret; 1424 } 1425 1426 if (device_property_read_bool(dev, "adi,external-fault-fet-off-enable")) { 1427 if (!st->ext_fault) 1428 return dev_err_probe(dev, -EINVAL, 1429 "adi,external-fault-fet-off-enable set but PGIO4 not configured\n"); 1430 ret = regmap_set_bits(st->map, LTC4283_CONFIG_3, 1431 LTC4283_EXTFLT_TURN_OFF_MASK); 1432 if (ret) 1433 return ret; 1434 } 1435 1436 if (device_property_read_bool(dev, "adi,vpower-drns-enable")) { 1437 u32 chan = LTC4283_CHAN_DRNS - LTC4283_CHAN_ADI_1; 1438 1439 __clear_bit(LTC4283_CHAN_DRNS, &st->ch_enable_mask); 1440 /* 1441 * Then, let's by default disable DRNS from ADC2 given that it 1442 * is already being monitored by the VPWR channel. One can still 1443 * enable it later on if needed. 1444 */ 1445 ret = regmap_clear_bits(st->map, LTC4283_ADC_SELECT(chan), 1446 LTC4283_ADC_SELECT_MASK(chan)); 1447 if (ret) 1448 return ret; 1449 1450 val = 1; 1451 } else { 1452 val = 0; 1453 } 1454 1455 ret = regmap_update_bits(st->map, LTC4283_CONFIG_3, 1456 LTC4283_VPWR_DRNS_MASK, 1457 FIELD_PREP(LTC4283_VPWR_DRNS_MASK, val)); 1458 if (ret) 1459 return ret; 1460 1461 /* Make sure the ADC has 12bit resolution since we're assuming that. */ 1462 ret = regmap_update_bits(st->map, LTC4283_PGIO_CONFIG_2, 1463 LTC4283_ADC_MASK, 1464 FIELD_PREP(LTC4283_ADC_MASK, 3)); 1465 if (ret) 1466 return ret; 1467 1468 /* Energy reads (which are 6 byte block reads) rely on page access */ 1469 ret = regmap_set_bits(st->map, LTC4283_CONTROL_1, LTC4283_RW_PAGE_MASK); 1470 if (ret) 1471 return ret; 1472 1473 /* 1474 * Make sure we are integrating power as we only support reporting 1475 * consumed energy. 1476 */ 1477 return regmap_clear_bits(st->map, LTC4283_METER_CONTROL, 1478 LTC4283_INTEGRATE_I_MASK); 1479 } 1480 1481 static const struct hwmon_channel_info * const ltc4283_info[] = { 1482 HWMON_CHANNEL_INFO(in, 1483 HWMON_I_LCRIT_ALARM | HWMON_I_CRIT_ALARM | 1484 HWMON_I_RESET_HISTORY | HWMON_I_LABEL, 1485 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1486 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1487 HWMON_I_MAX_ALARM | HWMON_I_RESET_HISTORY | 1488 HWMON_I_LABEL, 1489 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1490 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1491 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1492 HWMON_I_ENABLE | HWMON_I_LABEL, 1493 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1494 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1495 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1496 HWMON_I_ENABLE | HWMON_I_LABEL, 1497 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1498 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1499 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1500 HWMON_I_ENABLE | HWMON_I_LABEL, 1501 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1502 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1503 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1504 HWMON_I_ENABLE | HWMON_I_LABEL, 1505 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1506 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1507 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1508 HWMON_I_ENABLE | HWMON_I_LABEL, 1509 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1510 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1511 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1512 HWMON_I_ENABLE | HWMON_I_LABEL, 1513 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1514 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1515 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1516 HWMON_I_ENABLE | HWMON_I_LABEL, 1517 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1518 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1519 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1520 HWMON_I_ENABLE | HWMON_I_LABEL, 1521 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1522 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1523 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1524 HWMON_I_ENABLE | HWMON_I_LABEL, 1525 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1526 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1527 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1528 HWMON_I_FAULT | HWMON_I_ENABLE | HWMON_I_LABEL, 1529 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1530 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1531 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1532 HWMON_I_ENABLE | HWMON_I_LABEL, 1533 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1534 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1535 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1536 HWMON_I_ENABLE | HWMON_I_LABEL, 1537 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1538 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1539 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1540 HWMON_I_ENABLE | HWMON_I_LABEL, 1541 HWMON_I_INPUT | HWMON_I_LOWEST | HWMON_I_HIGHEST | 1542 HWMON_I_MAX | HWMON_I_MIN | HWMON_I_MIN_ALARM | 1543 HWMON_I_RESET_HISTORY | HWMON_I_MAX_ALARM | 1544 HWMON_I_ENABLE | HWMON_I_LABEL), 1545 HWMON_CHANNEL_INFO(curr, 1546 HWMON_C_INPUT | HWMON_C_LOWEST | HWMON_C_HIGHEST | 1547 HWMON_C_MAX | HWMON_C_MIN | HWMON_C_MIN_ALARM | 1548 HWMON_C_MAX_ALARM | HWMON_C_CRIT_ALARM | 1549 HWMON_C_RESET_HISTORY | HWMON_C_LABEL), 1550 HWMON_CHANNEL_INFO(power, 1551 HWMON_P_INPUT | HWMON_P_INPUT_LOWEST | 1552 HWMON_P_INPUT_HIGHEST | HWMON_P_MAX | HWMON_P_MIN | 1553 HWMON_P_MAX_ALARM | HWMON_P_MIN_ALARM | 1554 HWMON_P_RESET_HISTORY | HWMON_P_LABEL), 1555 HWMON_CHANNEL_INFO(energy, 1556 HWMON_E_ENABLE), 1557 HWMON_CHANNEL_INFO(energy64, 1558 HWMON_E_INPUT), 1559 NULL 1560 }; 1561 1562 static const struct hwmon_ops ltc4283_ops = { 1563 .read = ltc4283_read, 1564 .write = ltc4283_write, 1565 .is_visible = ltc4283_is_visible, 1566 .read_string = ltc4283_read_labels, 1567 }; 1568 1569 static const struct hwmon_chip_info ltc4283_chip_info = { 1570 .ops = <c4283_ops, 1571 .info = ltc4283_info, 1572 }; 1573 1574 static int ltc4283_show_fault_log(void *arg, u64 *val, u32 mask) 1575 { 1576 struct ltc4283_hwmon *st = arg; 1577 long alarm; 1578 int ret; 1579 1580 ret = ltc4283_read_alarm(st, LTC4283_FAULT_LOG, mask, &alarm); 1581 if (ret) 1582 return ret; 1583 1584 *val = alarm; 1585 1586 return 0; 1587 } 1588 1589 static int ltc4283_show_in0_lcrit_fault_log(void *arg, u64 *val) 1590 { 1591 return ltc4283_show_fault_log(arg, val, LTC4283_UV_FAULT_MASK); 1592 } 1593 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_lcrit_fault_log, 1594 ltc4283_show_in0_lcrit_fault_log, NULL, "%llu\n"); 1595 1596 static int ltc4283_show_in0_crit_fault_log(void *arg, u64 *val) 1597 { 1598 return ltc4283_show_fault_log(arg, val, LTC4283_OV_FAULT_MASK); 1599 } 1600 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_in0_crit_fault_log, 1601 ltc4283_show_in0_crit_fault_log, NULL, "%llu\n"); 1602 1603 static int ltc4283_show_fet_bad_fault_log(void *arg, u64 *val) 1604 { 1605 return ltc4283_show_fault_log(arg, val, LTC4283_FET_BAD_FAULT_MASK); 1606 } 1607 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_bad_fault_log, 1608 ltc4283_show_fet_bad_fault_log, NULL, "%llu\n"); 1609 1610 static int ltc4283_show_fet_short_fault_log(void *arg, u64 *val) 1611 { 1612 return ltc4283_show_fault_log(arg, val, LTC4283_FET_SHORT_FAULT_MASK); 1613 } 1614 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_fet_short_fault_log, 1615 ltc4283_show_fet_short_fault_log, NULL, "%llu\n"); 1616 1617 static int ltc4283_show_curr1_crit_fault_log(void *arg, u64 *val) 1618 { 1619 return ltc4283_show_fault_log(arg, val, LTC4283_OC_FAULT_MASK); 1620 } 1621 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_curr1_crit_fault_log, 1622 ltc4283_show_curr1_crit_fault_log, NULL, "%llu\n"); 1623 1624 static int ltc4283_show_power1_failed_fault_log(void *arg, u64 *val) 1625 { 1626 return ltc4283_show_fault_log(arg, val, LTC4283_PWR_FAIL_FAULT_MASK); 1627 } 1628 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_failed_fault_log, 1629 ltc4283_show_power1_failed_fault_log, NULL, "%llu\n"); 1630 1631 static int ltc4283_show_power1_good_input_fault_log(void *arg, u64 *val) 1632 { 1633 return ltc4283_show_fault_log(arg, val, LTC4283_PGI_FAULT_MASK); 1634 } 1635 DEFINE_DEBUGFS_ATTRIBUTE(ltc4283_power1_good_input_fault_log, 1636 ltc4283_show_power1_good_input_fault_log, NULL, "%llu\n"); 1637 1638 static void ltc4283_debugfs_init(struct ltc4283_hwmon *st, struct i2c_client *i2c) 1639 { 1640 debugfs_create_file_unsafe("in0_crit_fault_log", 0400, i2c->debugfs, st, 1641 <c4283_in0_crit_fault_log); 1642 debugfs_create_file_unsafe("in0_lcrit_fault_log", 0400, i2c->debugfs, st, 1643 <c4283_in0_lcrit_fault_log); 1644 debugfs_create_file_unsafe("in11_fet_bad_fault_log", 0400, i2c->debugfs, st, 1645 <c4283_fet_bad_fault_log); 1646 debugfs_create_file_unsafe("in11_fet_short_fault_log", 0400, i2c->debugfs, st, 1647 <c4283_fet_short_fault_log); 1648 debugfs_create_file_unsafe("curr1_crit_fault_log", 0400, i2c->debugfs, st, 1649 <c4283_curr1_crit_fault_log); 1650 debugfs_create_file_unsafe("power1_failed_fault_log", 0400, i2c->debugfs, st, 1651 <c4283_power1_failed_fault_log); 1652 debugfs_create_file_unsafe("power1_good_input_fault_log", 0400, i2c->debugfs, 1653 st, <c4283_power1_good_input_fault_log); 1654 } 1655 1656 static bool ltc4283_is_word_reg(unsigned int reg) 1657 { 1658 return reg >= LTC4283_SENSE && reg <= LTC4283_ADIO34_MAX; 1659 } 1660 1661 static int ltc4283_reg_read(void *context, unsigned int reg, unsigned int *val) 1662 { 1663 struct i2c_client *client = context; 1664 int ret; 1665 1666 if (ltc4283_is_word_reg(reg)) 1667 ret = i2c_smbus_read_word_swapped(client, reg); 1668 else 1669 ret = i2c_smbus_read_byte_data(client, reg); 1670 1671 if (ret < 0) 1672 return ret; 1673 1674 *val = ret; 1675 return 0; 1676 } 1677 1678 static int ltc4283_reg_write(void *context, unsigned int reg, unsigned int val) 1679 { 1680 struct i2c_client *client = context; 1681 1682 if (ltc4283_is_word_reg(reg)) 1683 return i2c_smbus_write_word_swapped(client, reg, val); 1684 1685 return i2c_smbus_write_byte_data(client, reg, val); 1686 } 1687 1688 static const struct regmap_bus ltc4283_regmap_bus = { 1689 .reg_read = ltc4283_reg_read, 1690 .reg_write = ltc4283_reg_write, 1691 }; 1692 1693 static bool ltc4283_writable_reg(struct device *dev, unsigned int reg) 1694 { 1695 switch (reg) { 1696 case LTC4283_SYSTEM_STATUS ... LTC4283_FAULT_STATUS: 1697 return false; 1698 case LTC4283_RESERVED_OC: 1699 return false; 1700 case LTC4283_RESERVED_86 ... LTC4283_RESERVED_8F: 1701 return false; 1702 case LTC4283_RESERVED_91 ... LTC4283_RESERVED_A1: 1703 return false; 1704 case LTC4283_RESERVED_A3: 1705 return false; 1706 case LTC4283_RESERVED_AC: 1707 return false; 1708 case LTC4283_POWER_PLAY_MSB ... LTC4283_POWER_PLAY_LSB: 1709 return false; 1710 case LTC4283_RESERVED_F1 ... LTC4283_RESERVED_FF: 1711 return false; 1712 default: 1713 return true; 1714 } 1715 } 1716 1717 static const struct regmap_config ltc4283_regmap_config = { 1718 .reg_bits = 8, 1719 .val_bits = 16, 1720 .max_register = 0xFF, 1721 .writeable_reg = ltc4283_writable_reg, 1722 }; 1723 1724 static int ltc4283_probe(struct i2c_client *client) 1725 { 1726 struct device *dev = &client->dev, *hwmon; 1727 struct auxiliary_device *adev; 1728 struct ltc4283_hwmon *st; 1729 int ret, id; 1730 1731 st = devm_kzalloc(dev, sizeof(*st), GFP_KERNEL); 1732 if (!st) 1733 return -ENOMEM; 1734 1735 if (!i2c_check_functionality(client->adapter, 1736 I2C_FUNC_SMBUS_BYTE_DATA | 1737 I2C_FUNC_SMBUS_WORD_DATA | 1738 I2C_FUNC_SMBUS_READ_I2C_BLOCK)) 1739 return -EOPNOTSUPP; 1740 1741 st->client = client; 1742 st->map = devm_regmap_init(dev, <c4283_regmap_bus, client, 1743 <c4283_regmap_config); 1744 if (IS_ERR(st->map)) 1745 return dev_err_probe(dev, PTR_ERR(st->map), 1746 "Failed to create regmap\n"); 1747 1748 ret = ltc4283_setup(st, dev); 1749 if (ret) 1750 return ret; 1751 1752 hwmon = devm_hwmon_device_register_with_info(dev, "ltc4283", st, 1753 <c4283_chip_info, NULL); 1754 1755 if (IS_ERR(hwmon)) 1756 return PTR_ERR(hwmon); 1757 1758 ltc4283_debugfs_init(st, client); 1759 1760 if (!st->gpio_mask) 1761 return 0; 1762 1763 id = (client->adapter->nr << 10) | client->addr; 1764 adev = __devm_auxiliary_device_create(dev, KBUILD_MODNAME, "gpio", 1765 &st->gpio_mask, id); 1766 if (!adev) 1767 return dev_err_probe(dev, -ENODEV, "Failed to add GPIO device\n"); 1768 1769 return 0; 1770 } 1771 1772 static const struct of_device_id ltc4283_of_match[] = { 1773 { .compatible = "adi,ltc4283" }, 1774 { } 1775 }; 1776 1777 static const struct i2c_device_id ltc4283_i2c_id[] = { 1778 { "ltc4283" }, 1779 { } 1780 }; 1781 MODULE_DEVICE_TABLE(i2c, ltc4283_i2c_id); 1782 1783 static struct i2c_driver ltc4283_driver = { 1784 .driver = { 1785 .name = "ltc4283", 1786 .of_match_table = ltc4283_of_match, 1787 }, 1788 .probe = ltc4283_probe, 1789 .id_table = ltc4283_i2c_id, 1790 }; 1791 module_i2c_driver(ltc4283_driver); 1792 1793 MODULE_AUTHOR("Nuno Sá <nuno.sa@analog.com>"); 1794 MODULE_DESCRIPTION("LTC4283 Hot Swap Controller driver"); 1795 MODULE_LICENSE("GPL"); 1796