1 // SPDX-License-Identifier: GPL-2.0 2 // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 4 use kernel::{ 5 io::{ 6 register, 7 register::WithBase, 8 Io, // 9 }, 10 prelude::*, 11 sizes::SizeConstants, 12 time, // 13 }; 14 15 use crate::{ 16 driver::Bar0, 17 falcon::{ 18 DmaTrfCmdSize, 19 FalconCoreRev, 20 FalconCoreRevSubversion, 21 FalconEngine, 22 FalconFbifMemType, 23 FalconFbifTarget, 24 FalconMem, 25 FalconModSelAlgo, 26 FalconSecurityModel, 27 PFalcon2Base, 28 PFalconBase, 29 PeregrineCoreSelect, // 30 }, 31 gpu::{ 32 Architecture, 33 Chipset, // 34 }, 35 }; 36 37 // PMC 38 39 register! { 40 /// Basic revision information about the GPU. 41 pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 { 42 /// Lower bits of the architecture. 43 28:24 architecture_0; 44 /// Implementation version of the architecture. 45 23:20 implementation; 46 /// MSB of the architecture. 47 8:8 architecture_1; 48 /// Major revision of the chip. 49 7:4 major_revision; 50 /// Minor revision of the chip. 51 3:0 minor_revision; 52 } 53 54 /// Extended architecture information. 55 pub(crate) NV_PMC_BOOT_42(u32) @ 0x00000a00 { 56 /// Architecture value. 57 29:24 architecture ?=> Architecture; 58 /// Implementation version of the architecture. 59 23:20 implementation; 60 /// Major revision of the chip. 61 19:16 major_revision; 62 /// Minor revision of the chip. 63 15:12 minor_revision; 64 } 65 } 66 67 impl NV_PMC_BOOT_0 { 68 pub(crate) fn is_older_than_fermi(self) -> bool { 69 // From https://github.com/NVIDIA/open-gpu-doc/tree/master/manuals : 70 const NV_PMC_BOOT_0_ARCHITECTURE_GF100: u32 = 0xc; 71 72 // Older chips left arch1 zeroed out. That, combined with an arch0 value that is less than 73 // GF100, means "older than Fermi". 74 self.architecture_1() == 0 && self.architecture_0() < NV_PMC_BOOT_0_ARCHITECTURE_GF100 75 } 76 } 77 78 impl NV_PMC_BOOT_42 { 79 /// Combines `architecture` and `implementation` to obtain a code unique to the chipset. 80 pub(crate) fn chipset(self) -> Result<Chipset> { 81 self.architecture() 82 .map(|arch| { 83 ((arch as u32) << Self::IMPLEMENTATION_RANGE.len()) 84 | u32::from(self.implementation()) 85 }) 86 .and_then(Chipset::try_from) 87 } 88 89 /// Returns the raw architecture value from the register. 90 fn architecture_raw(self) -> u8 { 91 ((self.into_raw() >> Self::ARCHITECTURE_RANGE.start()) 92 & ((1 << Self::ARCHITECTURE_RANGE.len()) - 1)) as u8 93 } 94 } 95 96 impl kernel::fmt::Display for NV_PMC_BOOT_42 { 97 fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { 98 write!( 99 f, 100 "boot42 = 0x{:08x} (architecture 0x{:x}, implementation 0x{:x})", 101 self.inner, 102 self.architecture_raw(), 103 self.implementation() 104 ) 105 } 106 } 107 108 // PBUS 109 110 register! { 111 pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} 112 113 /// Scratch register 0xe used as FRTS firmware error code. 114 pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { 115 31:16 frts_err_code; 116 } 117 } 118 119 // PFB 120 121 register! { 122 /// Low bits of the physical system memory address used by the GPU to perform sysmembar 123 /// operations (see [`crate::fb::SysmemFlush`]). 124 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { 125 31:0 adr_39_08; 126 } 127 128 /// High bits of the physical system memory address used by the GPU to perform sysmembar 129 /// operations (see [`crate::fb::SysmemFlush`]). 130 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 { 131 23:0 adr_63_40; 132 } 133 134 pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { 135 30:30 ecc_mode_enabled => bool; 136 9:4 lower_mag; 137 3:0 lower_scale; 138 } 139 140 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 { 141 /// Bits 12..40 of the lower (inclusive) bound of the WPR2 region. 142 31:4 lo_val; 143 } 144 145 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 { 146 /// Bits 12..40 of the higher (exclusive) bound of the WPR2 region. 147 31:4 hi_val; 148 } 149 } 150 151 /// Base of the GB10x HSHUB0 register window (`NV_HSHUB0_PRIV_BASE` in Open RM). 152 /// 153 /// The base is provided by the GB10x framebuffer HAL. 154 pub(crate) struct Hshub0Base(()); 155 156 /// Base of the GB20x FBHUB0 register window (`NV_FBHUB0_PRI_BASE` in Open RM). 157 /// 158 /// The base is provided by the GB20x framebuffer HAL. 159 pub(crate) struct Fbhub0Base(()); 160 161 register! { 162 // GB10x sysmem flush registers, relative to the HSHUB0 base. GB10x routes sysmembar 163 // through a primary and an EG (egress) pair that must both be programmed to the same 164 // address. Hardware ignores bits 7:0 of each LO register. The boot path uses a fixed 165 // HSHUB0 base, so the multiple runtime-discovered HSHUB bases are not needed here. 166 pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base + 0x00000e50 { 167 31:0 adr => u32; 168 } 169 170 pub(crate) NV_PFB_HSHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + 0x00000e54 { 171 19:0 adr; 172 } 173 174 pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Hshub0Base + 0x000006c0 { 175 31:0 adr => u32; 176 } 177 178 pub(crate) NV_PFB_HSHUB_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Hshub0Base + 0x000006c4 { 179 19:0 adr; 180 } 181 182 // GB20x sysmem flush registers, relative to the FBHUB0 base. Unlike the older 183 // NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address with an 8-bit 184 // right-shift, these take the raw address split into lower and upper halves. Hardware 185 // ignores bits 7:0 of the LO register. 186 pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ Fbhub0Base + 0x00001d58 { 187 31:0 adr => u32; 188 } 189 190 pub(crate) NV_PFB_FBHUB_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ Fbhub0Base + 0x00001d5c { 191 19:0 adr; 192 } 193 } 194 195 impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { 196 /// Returns the usable framebuffer size, in bytes. 197 pub(crate) fn usable_fb_size(self) -> u64 { 198 let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale())) * u64::SZ_1M; 199 200 if self.ecc_mode_enabled() { 201 // Remove the amount of memory reserved for ECC (one per 16 units). 202 size / 16 * 15 203 } else { 204 size 205 } 206 } 207 } 208 209 impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { 210 /// Returns the lower (inclusive) bound of the WPR2 region. 211 pub(crate) fn lower_bound(self) -> u64 { 212 u64::from(self.lo_val()) << 12 213 } 214 } 215 216 impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { 217 /// Returns the higher (exclusive) bound of the WPR2 region. 218 /// 219 /// A value of zero means the WPR2 region is not set. 220 pub(crate) fn higher_bound(self) -> u64 { 221 u64::from(self.hi_val()) << 12 222 } 223 224 /// Returns whether the WPR2 region is currently set. 225 pub(crate) fn is_wpr2_set(self) -> bool { 226 self.hi_val() != 0 227 } 228 } 229 230 // PGSP 231 232 register! { 233 pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 { 234 31:0 address; 235 } 236 } 237 238 // PGC6 register space. 239 // 240 // `GC6` is a GPU low-power state where VRAM is in self-refresh and the GPU is powered down (except 241 // for power rails needed to keep self-refresh working and important registers and hardware 242 // blocks). 243 // 244 // These scratch registers remain powered on even in a low-power state and have a designated group 245 // number. 246 247 register! { 248 /// Boot Sequence Interface (BSI) register used to determine 249 /// if GSP reload/resume has completed during the boot process. 250 pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { 251 26:26 boot_stage_3_handoff => bool; 252 } 253 254 /// Privilege level mask register. It dictates whether the host CPU has privilege to access the 255 /// `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 256 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK(u32) @ 0x00118128 { 257 /// Set after FWSEC lowers its protection level. 258 0:0 read_protection_level0 => bool; 259 } 260 261 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 262 /// first element. Be conservative until we know the actual size or need to use more registers. 263 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(u32)[1] @ 0x00118234 {} 264 265 /// Scratch group 05 register 0 used as GFW boot progress indicator. 266 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT(u32) 267 => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0] { 268 /// Progress of GFW boot (0xff means completed). 269 7:0 progress; 270 } 271 272 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_42(u32) @ 0x001183a4 { 273 31:0 value; 274 } 275 276 /// Scratch group 42 register used as framebuffer size. 277 pub(crate) NV_USABLE_FB_SIZE_IN_MB(u32) => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 { 278 /// Usable framebuffer size, in megabytes. 279 31:0 value; 280 } 281 } 282 283 impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { 284 /// Returns `true` if GFW boot is completed. 285 pub(crate) fn completed(self) -> bool { 286 self.progress() == 0xff 287 } 288 } 289 290 impl NV_USABLE_FB_SIZE_IN_MB { 291 /// Returns the usable framebuffer size, in bytes. 292 pub(crate) fn usable_fb_size(self) -> u64 { 293 u64::from(self.value()) * u64::SZ_1M 294 } 295 } 296 297 // PDISP 298 299 register! { 300 pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { 301 /// VGA workspace base address divided by 0x10000. 302 31:8 addr; 303 /// Set if the `addr` field is valid. 304 3:3 status_valid => bool; 305 } 306 } 307 308 impl NV_PDISP_VGA_WORKSPACE_BASE { 309 /// Returns the base address of the VGA workspace, or `None` if none exists. 310 pub(crate) fn vga_workspace_addr(self) -> Option<u64> { 311 if self.status_valid() { 312 Some(u64::from(self.addr()) << 16) 313 } else { 314 None 315 } 316 } 317 } 318 319 // FUSE 320 321 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; 322 323 register! { 324 pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 { 325 15:0 data => u16; 326 } 327 328 pub(crate) NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 { 329 15:0 data => u16; 330 } 331 332 pub(crate) NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 { 333 15:0 data => u16; 334 } 335 } 336 337 // PFALCON 338 339 register! { 340 pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { 341 6:6 swgen0 => bool; 342 4:4 halt => bool; 343 } 344 345 pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 { 346 31:0 value => u32; 347 } 348 349 pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 { 350 31:0 value => u32; 351 } 352 353 /// Used to store version information about the firmware running 354 /// on the Falcon processor. 355 pub(crate) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 { 356 31:0 value => u32; 357 } 358 359 pub(crate) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 { 360 31:0 value => u32; 361 } 362 363 pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { 364 /// Signal indicating that reset is completed (GA102+). 365 31:31 reset_ready => bool; 366 /// Set to 0 after memory scrubbing is completed. 367 12:12 mem_scrubbing => bool; 368 10:10 riscv => bool; 369 } 370 371 pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 { 372 6:6 alias_en => bool; 373 4:4 halted => bool; 374 1:1 startcpu => bool; 375 } 376 377 pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 { 378 31:0 value => u32; 379 } 380 381 pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c { 382 7:7 secure_stat => bool; 383 6:3 dmaq_num; 384 2:2 imem_scrubbing => bool; 385 1:1 dmem_scrubbing => bool; 386 0:0 require_ctx => bool; 387 } 388 389 pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x00000110 { 390 31:0 base => u32; 391 } 392 393 pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x00000114 { 394 23:0 offs; 395 } 396 397 pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118 { 398 16:16 set_dmtag; 399 14:12 ctxdma; 400 10:8 size ?=> DmaTrfCmdSize; 401 5:5 is_write => bool; 402 4:4 imem => bool; 403 3:2 sec; 404 1:1 idle => bool; 405 0:0 full => bool; 406 } 407 408 pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x0000011c { 409 31:0 offs => u32; 410 } 411 412 pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x00000128 { 413 8:0 base; 414 } 415 416 pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c { 417 /// Core revision subversion. 418 7:6 core_rev_subversion => FalconCoreRevSubversion; 419 /// Security model. 420 5:4 security_model ?=> FalconSecurityModel; 421 /// Core revision. 422 3:0 core_rev ?=> FalconCoreRev; 423 } 424 425 pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000130 { 426 1:1 startcpu => bool; 427 } 428 429 /// IMEM access control register. Up to 4 ports are available for IMEM access. 430 pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ PFalconBase + 0x00000180 { 431 /// Access secure IMEM. 432 28:28 secure => bool; 433 /// Auto-increment on write. 434 24:24 aincw => bool; 435 /// IMEM block and word offset. 436 15:0 offs; 437 } 438 439 /// IMEM data register. Reading/writing this register accesses IMEM at the address 440 /// specified by the corresponding IMEMC register. 441 pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ PFalconBase + 0x00000184 { 442 31:0 data; 443 } 444 445 /// IMEM tag register. Used to set the tag for the current IMEM block. 446 pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ PFalconBase + 0x00000188 { 447 15:0 tag; 448 } 449 450 /// DMEM access control register. Up to 8 ports are available for DMEM access. 451 pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ PFalconBase + 0x000001c0 { 452 /// Auto-increment on write. 453 24:24 aincw => bool; 454 /// DMEM block and word offset. 455 15:0 offs; 456 } 457 458 /// DMEM data register. Reading/writing this register accesses DMEM at the address 459 /// specified by the corresponding DMEMC register. 460 pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ PFalconBase + 0x000001c4 { 461 31:0 data; 462 } 463 464 /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the 465 /// falcon instance. 466 pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 { 467 0:0 reset => bool; 468 } 469 470 pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 { 471 2:2 mem_type => FalconFbifMemType; 472 1:0 target ?=> FalconFbifTarget; 473 } 474 475 pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { 476 7:7 allow_phys_no_ctx => bool; 477 } 478 479 // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). 480 // These provide the falcon external memory communication interface. 481 482 pub(crate) NV_PFALCON_FALCON_EMEMC(u32) @ PFalconBase + 0x00000ac0 { 483 /// EMEM byte offset (4-byte aligned) within the block. 484 7:2 offs; 485 /// EMEM block to access. 486 15:8 blk; 487 /// Auto-increment the offset after each write. 488 24:24 aincw => bool; 489 /// Auto-increment the offset after each read. 490 25:25 aincr => bool; 491 } 492 493 pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ PFalconBase + 0x00000ac4 { 494 31:0 data => u32; 495 } 496 } 497 498 impl NV_PFALCON_FALCON_DMACTL { 499 /// Returns `true` if memory scrubbing is completed. 500 pub(crate) fn mem_scrubbing_done(self) -> bool { 501 !self.dmem_scrubbing() && !self.imem_scrubbing() 502 } 503 } 504 505 impl NV_PFALCON_FALCON_DMATRFCMD { 506 /// Programs the `imem` and `sec` fields for the given FalconMem 507 pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 508 let this = self.with_imem(mem != FalconMem::Dmem); 509 510 match mem { 511 FalconMem::ImemSecure => this.with_const_sec::<1>(), 512 _ => this.with_const_sec::<0>(), 513 } 514 } 515 } 516 517 impl NV_PFALCON_FALCON_ENGINE { 518 /// Resets the falcon 519 pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) { 520 bar.update(Self::of::<E>(), |r| r.with_reset(true)); 521 522 // TIMEOUT: falcon engine should not take more than 10us to reset. 523 time::delay::fsleep(time::Delta::from_micros(10)); 524 525 bar.update(Self::of::<E>(), |r| r.with_reset(false)); 526 } 527 } 528 529 impl NV_PFALCON_FALCON_HWCFG2 { 530 /// Returns `true` if memory scrubbing is completed. 531 pub(crate) fn mem_scrubbing_done(self) -> bool { 532 !self.mem_scrubbing() 533 } 534 } 535 536 /* PFALCON2 */ 537 538 register! { 539 pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { 540 7:0 algo ?=> FalconModSelAlgo; 541 } 542 543 pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { 544 7:0 ucode_id => u8; 545 } 546 547 pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { 548 31:0 value => u32; 549 } 550 551 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 552 /// first element. Be conservative until we know the actual size or need to use more registers. 553 pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { 554 31:0 value => u32; 555 } 556 } 557 558 // PRISCV 559 560 register! { 561 /// RISC-V status register for debug (Turing and GA100 only). 562 /// Reflects current RISC-V core status. 563 pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { 564 /// RISC-V core active/inactive status. 565 0:0 active_stat => bool; 566 } 567 568 /// GA102 and later. 569 pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { 570 7:7 active_stat => bool; 571 0:0 halted => bool; 572 } 573 574 /// GA102 and later. 575 pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { 576 8:8 br_fetch => bool; 577 4:4 core_select => PeregrineCoreSelect; 578 0:0 valid => bool; 579 } 580 } 581 582 // FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. 583 // These registers manage falcon EMEM communication queues. 584 585 register! { 586 pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { 587 31:0 address => u32; 588 } 589 590 pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { 591 31:0 address => u32; 592 } 593 594 pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { 595 31:0 val => u32; 596 } 597 598 pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { 599 31:0 val => u32; 600 } 601 } 602 603 // The modules below provide registers that are not identical on all supported chips. They should 604 // only be used in HAL modules. 605 606 pub(crate) mod gm107 { 607 use kernel::io::register; 608 609 // FUSE 610 611 register! { 612 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 { 613 0:0 display_disabled => bool; 614 } 615 } 616 } 617 618 pub(crate) mod ga100 { 619 use kernel::io::register; 620 621 // FUSE 622 623 register! { 624 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 { 625 0:0 display_disabled => bool; 626 } 627 } 628 } 629 630 pub(crate) const NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS: u32 = 0xff; 631 632 pub(crate) mod gh100 { 633 use kernel::io::register; 634 635 // PTHERM 636 637 register! { 638 pub(crate) NV_THERM_I2CS_SCRATCH(u32) @ 0x000200bc { 639 31:0 data; 640 } 641 642 // Alias to `NV_THERM_I2CS_SCRATCH` when used to check for FSP boot completion. 643 pub(crate) NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE(u32) => NV_THERM_I2CS_SCRATCH { 644 31:0 fsp_boot_complete; 645 } 646 } 647 } 648 649 pub(crate) mod gb202 { 650 use kernel::io::register; 651 652 // PTHERM 653 654 register! { 655 pub(crate) NV_THERM_I2CS_SCRATCH(u32) @ 0x00ad00bc { 656 31:0 data; 657 } 658 659 // Alias to `NV_THERM_I2CS_SCRATCH` when used to check for FSP boot completion. 660 pub(crate) NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE(u32) => NV_THERM_I2CS_SCRATCH { 661 31:0 fsp_boot_complete; 662 } 663 } 664 } 665