1 // SPDX-License-Identifier: GPL-2.0 2 3 use crate::driver::Bar0; 4 5 // TODO 6 // 7 // Create register definitions via generic macros. See task "Generic register 8 // abstraction" in Documentation/gpu/nova/core/todo.rst. 9 10 const BOOT0_OFFSET: usize = 0x00000000; 11 12 // 3:0 - chipset minor revision 13 const BOOT0_MINOR_REV_SHIFT: u8 = 0; 14 const BOOT0_MINOR_REV_MASK: u32 = 0x0000000f; 15 16 // 7:4 - chipset major revision 17 const BOOT0_MAJOR_REV_SHIFT: u8 = 4; 18 const BOOT0_MAJOR_REV_MASK: u32 = 0x000000f0; 19 20 // 23:20 - chipset implementation Identifier (depends on architecture) 21 const BOOT0_IMPL_SHIFT: u8 = 20; 22 const BOOT0_IMPL_MASK: u32 = 0x00f00000; 23 24 // 28:24 - chipset architecture identifier 25 const BOOT0_ARCH_MASK: u32 = 0x1f000000; 26 27 // 28:20 - chipset identifier (virtual register field combining BOOT0_IMPL and 28 // BOOT0_ARCH) 29 const BOOT0_CHIPSET_SHIFT: u8 = BOOT0_IMPL_SHIFT; 30 const BOOT0_CHIPSET_MASK: u32 = BOOT0_IMPL_MASK | BOOT0_ARCH_MASK; 31 32 #[derive(Copy, Clone)] 33 pub(crate) struct Boot0(u32); 34 35 impl Boot0 { 36 #[inline] 37 pub(crate) fn read(bar: &Bar0) -> Self { 38 Self(bar.read32(BOOT0_OFFSET)) 39 } 40 41 #[inline] 42 pub(crate) fn chipset(&self) -> u32 { 43 (self.0 & BOOT0_CHIPSET_MASK) >> BOOT0_CHIPSET_SHIFT 44 } 45 46 #[inline] 47 pub(crate) fn minor_rev(&self) -> u8 { 48 ((self.0 & BOOT0_MINOR_REV_MASK) >> BOOT0_MINOR_REV_SHIFT) as u8 49 } 50 51 #[inline] 52 pub(crate) fn major_rev(&self) -> u8 { 53 ((self.0 & BOOT0_MAJOR_REV_MASK) >> BOOT0_MAJOR_REV_SHIFT) as u8 54 } 55 } 56