1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::{ 5 register, 6 register::WithBase, 7 Io, // 8 }, 9 prelude::*, 10 sizes::SizeConstants, 11 time, // 12 }; 13 14 use crate::{ 15 driver::Bar0, 16 falcon::{ 17 DmaTrfCmdSize, 18 FalconCoreRev, 19 FalconCoreRevSubversion, 20 FalconEngine, 21 FalconFbifMemType, 22 FalconFbifTarget, 23 FalconMem, 24 FalconModSelAlgo, 25 FalconSecurityModel, 26 PFalcon2Base, 27 PFalconBase, 28 PeregrineCoreSelect, // 29 }, 30 gpu::{ 31 Architecture, 32 Chipset, // 33 }, 34 }; 35 36 // PMC 37 38 register! { 39 /// Basic revision information about the GPU. 40 pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 { 41 /// Lower bits of the architecture. 42 28:24 architecture_0; 43 /// Implementation version of the architecture. 44 23:20 implementation; 45 /// MSB of the architecture. 46 8:8 architecture_1; 47 /// Major revision of the chip. 48 7:4 major_revision; 49 /// Minor revision of the chip. 50 3:0 minor_revision; 51 } 52 53 /// Extended architecture information. 54 pub(crate) NV_PMC_BOOT_42(u32) @ 0x00000a00 { 55 /// Architecture value. 56 29:24 architecture ?=> Architecture; 57 /// Implementation version of the architecture. 58 23:20 implementation; 59 /// Major revision of the chip. 60 19:16 major_revision; 61 /// Minor revision of the chip. 62 15:12 minor_revision; 63 } 64 } 65 66 impl NV_PMC_BOOT_0 { 67 pub(crate) fn is_older_than_fermi(self) -> bool { 68 // From https://github.com/NVIDIA/open-gpu-doc/tree/master/manuals : 69 const NV_PMC_BOOT_0_ARCHITECTURE_GF100: u32 = 0xc; 70 71 // Older chips left arch1 zeroed out. That, combined with an arch0 value that is less than 72 // GF100, means "older than Fermi". 73 self.architecture_1() == 0 && self.architecture_0() < NV_PMC_BOOT_0_ARCHITECTURE_GF100 74 } 75 } 76 77 impl NV_PMC_BOOT_42 { 78 /// Combines `architecture` and `implementation` to obtain a code unique to the chipset. 79 pub(crate) fn chipset(self) -> Result<Chipset> { 80 self.architecture() 81 .map(|arch| { 82 ((arch as u32) << Self::IMPLEMENTATION_RANGE.len()) 83 | u32::from(self.implementation()) 84 }) 85 .and_then(Chipset::try_from) 86 } 87 88 /// Returns the raw architecture value from the register. 89 fn architecture_raw(self) -> u8 { 90 ((self.into_raw() >> Self::ARCHITECTURE_RANGE.start()) 91 & ((1 << Self::ARCHITECTURE_RANGE.len()) - 1)) as u8 92 } 93 } 94 95 impl kernel::fmt::Display for NV_PMC_BOOT_42 { 96 fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { 97 write!( 98 f, 99 "boot42 = 0x{:08x} (architecture 0x{:x}, implementation 0x{:x})", 100 self.inner, 101 self.architecture_raw(), 102 self.implementation() 103 ) 104 } 105 } 106 107 // PBUS 108 109 register! { 110 pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} 111 112 /// Scratch register 0xe used as FRTS firmware error code. 113 pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { 114 31:16 frts_err_code; 115 } 116 } 117 118 // PFB 119 120 register! { 121 /// Low bits of the physical system memory address used by the GPU to perform sysmembar 122 /// operations (see [`crate::fb::SysmemFlush`]). 123 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { 124 31:0 adr_39_08; 125 } 126 127 /// High bits of the physical system memory address used by the GPU to perform sysmembar 128 /// operations (see [`crate::fb::SysmemFlush`]). 129 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 { 130 23:0 adr_63_40; 131 } 132 133 pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { 134 30:30 ecc_mode_enabled => bool; 135 9:4 lower_mag; 136 3:0 lower_scale; 137 } 138 139 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 { 140 /// Bits 12..40 of the lower (inclusive) bound of the WPR2 region. 141 31:4 lo_val; 142 } 143 144 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 { 145 /// Bits 12..40 of the higher (exclusive) bound of the WPR2 region. 146 31:4 hi_val; 147 } 148 } 149 150 impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { 151 /// Returns the usable framebuffer size, in bytes. 152 pub(crate) fn usable_fb_size(self) -> u64 { 153 let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale())) * u64::SZ_1M; 154 155 if self.ecc_mode_enabled() { 156 // Remove the amount of memory reserved for ECC (one per 16 units). 157 size / 16 * 15 158 } else { 159 size 160 } 161 } 162 } 163 164 impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { 165 /// Returns the lower (inclusive) bound of the WPR2 region. 166 pub(crate) fn lower_bound(self) -> u64 { 167 u64::from(self.lo_val()) << 12 168 } 169 } 170 171 impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { 172 /// Returns the higher (exclusive) bound of the WPR2 region. 173 /// 174 /// A value of zero means the WPR2 region is not set. 175 pub(crate) fn higher_bound(self) -> u64 { 176 u64::from(self.hi_val()) << 12 177 } 178 179 /// Returns whether the WPR2 region is currently set. 180 pub(crate) fn is_wpr2_set(self) -> bool { 181 self.hi_val() != 0 182 } 183 } 184 185 // PGSP 186 187 register! { 188 pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 { 189 31:0 address; 190 } 191 } 192 193 // PGC6 register space. 194 // 195 // `GC6` is a GPU low-power state where VRAM is in self-refresh and the GPU is powered down (except 196 // for power rails needed to keep self-refresh working and important registers and hardware 197 // blocks). 198 // 199 // These scratch registers remain powered on even in a low-power state and have a designated group 200 // number. 201 202 register! { 203 /// Boot Sequence Interface (BSI) register used to determine 204 /// if GSP reload/resume has completed during the boot process. 205 pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { 206 26:26 boot_stage_3_handoff => bool; 207 } 208 209 /// Privilege level mask register. It dictates whether the host CPU has privilege to access the 210 /// `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 211 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK(u32) @ 0x00118128 { 212 /// Set after FWSEC lowers its protection level. 213 0:0 read_protection_level0 => bool; 214 } 215 216 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 217 /// first element. Be conservative until we know the actual size or need to use more registers. 218 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(u32)[1] @ 0x00118234 {} 219 220 /// Scratch group 05 register 0 used as GFW boot progress indicator. 221 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT(u32) 222 => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0] { 223 /// Progress of GFW boot (0xff means completed). 224 7:0 progress; 225 } 226 227 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_42(u32) @ 0x001183a4 { 228 31:0 value; 229 } 230 231 /// Scratch group 42 register used as framebuffer size. 232 pub(crate) NV_USABLE_FB_SIZE_IN_MB(u32) => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 { 233 /// Usable framebuffer size, in megabytes. 234 31:0 value; 235 } 236 } 237 238 impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { 239 /// Returns `true` if GFW boot is completed. 240 pub(crate) fn completed(self) -> bool { 241 self.progress() == 0xff 242 } 243 } 244 245 impl NV_USABLE_FB_SIZE_IN_MB { 246 /// Returns the usable framebuffer size, in bytes. 247 pub(crate) fn usable_fb_size(self) -> u64 { 248 u64::from(self.value()) * u64::SZ_1M 249 } 250 } 251 252 // PDISP 253 254 register! { 255 pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { 256 /// VGA workspace base address divided by 0x10000. 257 31:8 addr; 258 /// Set if the `addr` field is valid. 259 3:3 status_valid => bool; 260 } 261 } 262 263 impl NV_PDISP_VGA_WORKSPACE_BASE { 264 /// Returns the base address of the VGA workspace, or `None` if none exists. 265 pub(crate) fn vga_workspace_addr(self) -> Option<u64> { 266 if self.status_valid() { 267 Some(u64::from(self.addr()) << 16) 268 } else { 269 None 270 } 271 } 272 } 273 274 // FUSE 275 276 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; 277 278 register! { 279 pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 { 280 15:0 data => u16; 281 } 282 283 pub(crate) NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 { 284 15:0 data => u16; 285 } 286 287 pub(crate) NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 { 288 15:0 data => u16; 289 } 290 } 291 292 // PFALCON 293 294 register! { 295 pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { 296 6:6 swgen0 => bool; 297 4:4 halt => bool; 298 } 299 300 pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 { 301 31:0 value => u32; 302 } 303 304 pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 { 305 31:0 value => u32; 306 } 307 308 /// Used to store version information about the firmware running 309 /// on the Falcon processor. 310 pub(crate) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 { 311 31:0 value => u32; 312 } 313 314 pub(crate) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 { 315 31:0 value => u32; 316 } 317 318 pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { 319 /// Signal indicating that reset is completed (GA102+). 320 31:31 reset_ready => bool; 321 /// Set to 0 after memory scrubbing is completed. 322 12:12 mem_scrubbing => bool; 323 10:10 riscv => bool; 324 } 325 326 pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 { 327 6:6 alias_en => bool; 328 4:4 halted => bool; 329 1:1 startcpu => bool; 330 } 331 332 pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 { 333 31:0 value => u32; 334 } 335 336 pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c { 337 7:7 secure_stat => bool; 338 6:3 dmaq_num; 339 2:2 imem_scrubbing => bool; 340 1:1 dmem_scrubbing => bool; 341 0:0 require_ctx => bool; 342 } 343 344 pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x00000110 { 345 31:0 base => u32; 346 } 347 348 pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x00000114 { 349 23:0 offs; 350 } 351 352 pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118 { 353 16:16 set_dmtag; 354 14:12 ctxdma; 355 10:8 size ?=> DmaTrfCmdSize; 356 5:5 is_write => bool; 357 4:4 imem => bool; 358 3:2 sec; 359 1:1 idle => bool; 360 0:0 full => bool; 361 } 362 363 pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x0000011c { 364 31:0 offs => u32; 365 } 366 367 pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x00000128 { 368 8:0 base; 369 } 370 371 pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c { 372 /// Core revision subversion. 373 7:6 core_rev_subversion => FalconCoreRevSubversion; 374 /// Security model. 375 5:4 security_model ?=> FalconSecurityModel; 376 /// Core revision. 377 3:0 core_rev ?=> FalconCoreRev; 378 } 379 380 pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000130 { 381 1:1 startcpu => bool; 382 } 383 384 /// IMEM access control register. Up to 4 ports are available for IMEM access. 385 pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ PFalconBase + 0x00000180 { 386 /// Access secure IMEM. 387 28:28 secure => bool; 388 /// Auto-increment on write. 389 24:24 aincw => bool; 390 /// IMEM block and word offset. 391 15:0 offs; 392 } 393 394 /// IMEM data register. Reading/writing this register accesses IMEM at the address 395 /// specified by the corresponding IMEMC register. 396 pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ PFalconBase + 0x00000184 { 397 31:0 data; 398 } 399 400 /// IMEM tag register. Used to set the tag for the current IMEM block. 401 pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ PFalconBase + 0x00000188 { 402 15:0 tag; 403 } 404 405 /// DMEM access control register. Up to 8 ports are available for DMEM access. 406 pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ PFalconBase + 0x000001c0 { 407 /// Auto-increment on write. 408 24:24 aincw => bool; 409 /// DMEM block and word offset. 410 15:0 offs; 411 } 412 413 /// DMEM data register. Reading/writing this register accesses DMEM at the address 414 /// specified by the corresponding DMEMC register. 415 pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ PFalconBase + 0x000001c4 { 416 31:0 data; 417 } 418 419 /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the 420 /// falcon instance. 421 pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 { 422 0:0 reset => bool; 423 } 424 425 pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 { 426 2:2 mem_type => FalconFbifMemType; 427 1:0 target ?=> FalconFbifTarget; 428 } 429 430 pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { 431 7:7 allow_phys_no_ctx => bool; 432 } 433 } 434 435 impl NV_PFALCON_FALCON_DMACTL { 436 /// Returns `true` if memory scrubbing is completed. 437 pub(crate) fn mem_scrubbing_done(self) -> bool { 438 !self.dmem_scrubbing() && !self.imem_scrubbing() 439 } 440 } 441 442 impl NV_PFALCON_FALCON_DMATRFCMD { 443 /// Programs the `imem` and `sec` fields for the given FalconMem 444 pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 445 let this = self.with_imem(mem != FalconMem::Dmem); 446 447 match mem { 448 FalconMem::ImemSecure => this.with_const_sec::<1>(), 449 _ => this.with_const_sec::<0>(), 450 } 451 } 452 } 453 454 impl NV_PFALCON_FALCON_ENGINE { 455 /// Resets the falcon 456 pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) { 457 bar.update(Self::of::<E>(), |r| r.with_reset(true)); 458 459 // TIMEOUT: falcon engine should not take more than 10us to reset. 460 time::delay::fsleep(time::Delta::from_micros(10)); 461 462 bar.update(Self::of::<E>(), |r| r.with_reset(false)); 463 } 464 } 465 466 impl NV_PFALCON_FALCON_HWCFG2 { 467 /// Returns `true` if memory scrubbing is completed. 468 pub(crate) fn mem_scrubbing_done(self) -> bool { 469 !self.mem_scrubbing() 470 } 471 } 472 473 /* PFALCON2 */ 474 475 register! { 476 pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { 477 7:0 algo ?=> FalconModSelAlgo; 478 } 479 480 pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { 481 7:0 ucode_id => u8; 482 } 483 484 pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { 485 31:0 value => u32; 486 } 487 488 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 489 /// first element. Be conservative until we know the actual size or need to use more registers. 490 pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { 491 31:0 value => u32; 492 } 493 } 494 495 // PRISCV 496 497 register! { 498 /// RISC-V status register for debug (Turing and GA100 only). 499 /// Reflects current RISC-V core status. 500 pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { 501 /// RISC-V core active/inactive status. 502 0:0 active_stat => bool; 503 } 504 505 /// GA102 and later. 506 pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { 507 7:7 active_stat => bool; 508 0:0 halted => bool; 509 } 510 511 /// GA102 and later. 512 pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { 513 8:8 br_fetch => bool; 514 4:4 core_select => PeregrineCoreSelect; 515 0:0 valid => bool; 516 } 517 } 518 519 // The modules below provide registers that are not identical on all supported chips. They should 520 // only be used in HAL modules. 521 522 pub(crate) mod gm107 { 523 use kernel::io::register; 524 525 // FUSE 526 527 register! { 528 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 { 529 0:0 display_disabled => bool; 530 } 531 } 532 } 533 534 pub(crate) mod ga100 { 535 use kernel::io::register; 536 537 // FUSE 538 539 register! { 540 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 { 541 0:0 display_disabled => bool; 542 } 543 } 544 } 545