1 // SPDX-License-Identifier: GPL-2.0 2 // SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & AFFILIATES. All rights reserved. 3 4 use kernel::{ 5 io::{ 6 register, 7 Io, 8 Mmio, // 9 }, 10 prelude::*, 11 sizes::SizeConstants, 12 time, // 13 }; 14 15 use crate::{ 16 driver::NovaRegisters, 17 falcon::{ 18 DmaTrfCmdSize, 19 FalconCoreRev, 20 FalconCoreRevSubversion, 21 FalconFbifMemType, 22 FalconFbifTarget, 23 FalconMem, 24 FalconModSelAlgo, 25 FalconSecurityModel, 26 PFalcon2Registers, 27 PFalconRegisters, 28 PeregrineCoreSelect, // 29 }, 30 gpu::{ 31 Architecture, 32 Chipset, // 33 }, 34 }; 35 36 // PMC 37 38 register! { 39 base: NovaRegisters; 40 41 /// Basic revision information about the GPU. 42 pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 { 43 /// Lower bits of the architecture. 44 28:24 architecture_0; 45 /// Implementation version of the architecture. 46 23:20 implementation; 47 /// MSB of the architecture. 48 8:8 architecture_1; 49 /// Major revision of the chip. 50 7:4 major_revision; 51 /// Minor revision of the chip. 52 3:0 minor_revision; 53 } 54 55 /// Extended architecture information. 56 pub(crate) NV_PMC_BOOT_42(u32) @ 0x00000a00 { 57 /// Architecture value. 58 29:24 architecture ?=> Architecture; 59 /// Implementation version of the architecture. 60 23:20 implementation; 61 /// Major revision of the chip. 62 19:16 major_revision; 63 /// Minor revision of the chip. 64 15:12 minor_revision; 65 } 66 } 67 68 impl NV_PMC_BOOT_0 { 69 pub(crate) fn is_older_than_fermi(self) -> bool { 70 // From https://github.com/NVIDIA/open-gpu-doc/tree/master/manuals : 71 const NV_PMC_BOOT_0_ARCHITECTURE_GF100: u32 = 0xc; 72 73 // Older chips left arch1 zeroed out. That, combined with an arch0 value that is less than 74 // GF100, means "older than Fermi". 75 self.architecture_1() == 0 && self.architecture_0() < NV_PMC_BOOT_0_ARCHITECTURE_GF100 76 } 77 } 78 79 impl NV_PMC_BOOT_42 { 80 /// Combines `architecture` and `implementation` to obtain a code unique to the chipset. 81 pub(crate) fn chipset(self) -> Result<Chipset> { 82 self.architecture() 83 .map(|arch| { 84 ((arch as u32) << Self::IMPLEMENTATION_RANGE.len()) 85 | u32::from(self.implementation()) 86 }) 87 .and_then(Chipset::try_from) 88 } 89 90 /// Returns the raw architecture value from the register. 91 fn architecture_raw(self) -> u8 { 92 ((self.into_raw() >> Self::ARCHITECTURE_RANGE.start()) 93 & ((1 << Self::ARCHITECTURE_RANGE.len()) - 1)) as u8 94 } 95 } 96 97 impl kernel::fmt::Display for NV_PMC_BOOT_42 { 98 fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { 99 write!( 100 f, 101 "boot42 = 0x{:08x} (architecture 0x{:x}, implementation 0x{:x})", 102 self.inner, 103 self.architecture_raw(), 104 self.implementation() 105 ) 106 } 107 } 108 109 // PBUS 110 111 register! { 112 base: NovaRegisters; 113 114 pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} 115 } 116 117 // PGC6 register space. 118 // 119 // `GC6` is a GPU low-power state where VRAM is in self-refresh and the GPU is powered down (except 120 // for power rails needed to keep self-refresh working and important registers and hardware 121 // blocks). 122 // 123 // These scratch registers remain powered on even in a low-power state and have a designated group 124 // number. 125 126 register! { 127 base: NovaRegisters; 128 129 /// Boot Sequence Interface (BSI) register used to determine 130 /// if GSP reload/resume has completed during the boot process. 131 pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { 132 26:26 boot_stage_3_handoff => bool; 133 } 134 135 /// Privilege level mask register. It dictates whether the host CPU has privilege to access the 136 /// `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 137 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK(u32) @ 0x00118128 { 138 /// Set after FWSEC lowers its protection level. 139 0:0 read_protection_level0 => bool; 140 } 141 142 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 143 /// first element. Be conservative until we know the actual size or need to use more registers. 144 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(u32)[1] @ 0x00118234 {} 145 146 /// Scratch group 05 register 0 used as GFW boot progress indicator. 147 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT(u32) 148 => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0] { 149 /// Progress of GFW boot (0xff means completed). 150 7:0 progress; 151 } 152 153 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_42(u32) @ 0x001183a4 { 154 31:0 value; 155 } 156 157 /// Scratch group 42 register used as framebuffer size. 158 pub(crate) NV_USABLE_FB_SIZE_IN_MB(u32) => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 { 159 /// Usable framebuffer size, in megabytes. 160 31:0 value; 161 } 162 } 163 164 impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { 165 /// Returns `true` if GFW boot is completed. 166 pub(crate) fn completed(self) -> bool { 167 self.progress() == 0xff 168 } 169 } 170 171 impl NV_USABLE_FB_SIZE_IN_MB { 172 /// Returns the usable framebuffer size, in bytes. 173 pub(crate) fn usable_fb_size(self) -> u64 { 174 u64::from(self.value()) * u64::SZ_1M 175 } 176 } 177 178 // FUSE 179 180 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; 181 182 register! { 183 base: NovaRegisters; 184 185 pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 { 186 15:0 data => u16; 187 } 188 189 pub(crate) NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 { 190 15:0 data => u16; 191 } 192 193 pub(crate) NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 { 194 15:0 data => u16; 195 } 196 } 197 198 // PFALCON 199 200 register! { 201 base: PFalconRegisters; 202 203 pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ 0x00000004 { 204 6:6 swgen0 => bool; 205 4:4 halt => bool; 206 } 207 208 pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ 0x00000040 { 209 31:0 value => u32; 210 } 211 212 pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ 0x00000044 { 213 31:0 value => u32; 214 } 215 216 /// Used to store version information about the firmware running 217 /// on the Falcon processor. 218 pub(crate) NV_PFALCON_FALCON_OS(u32) @ 0x00000080 { 219 31:0 value => u32; 220 } 221 222 pub(crate) NV_PFALCON_FALCON_RM(u32) @ 0x00000084 { 223 31:0 value => u32; 224 } 225 226 pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ 0x000000f4 { 227 /// Signal indicating that reset is completed (GA102+). 228 31:31 reset_ready => bool; 229 /// RISC-V branch privilege lockdown bit. 230 13:13 riscv_br_priv_lockdown => bool; 231 /// Set to 0 after memory scrubbing is completed. 232 12:12 mem_scrubbing => bool; 233 10:10 riscv => bool; 234 } 235 236 pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ 0x00000100 { 237 6:6 alias_en => bool; 238 4:4 halted => bool; 239 1:1 startcpu => bool; 240 } 241 242 pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ 0x00000104 { 243 31:0 value => u32; 244 } 245 246 pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ 0x0000010c { 247 7:7 secure_stat => bool; 248 6:3 dmaq_num; 249 2:2 imem_scrubbing => bool; 250 1:1 dmem_scrubbing => bool; 251 0:0 require_ctx => bool; 252 } 253 254 pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ 0x00000110 { 255 31:0 base => u32; 256 } 257 258 pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ 0x00000114 { 259 23:0 offs; 260 } 261 262 pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ 0x00000118 { 263 16:16 set_dmtag; 264 14:12 ctxdma; 265 10:8 size ?=> DmaTrfCmdSize; 266 5:5 is_write => bool; 267 4:4 imem => bool; 268 3:2 sec; 269 1:1 idle => bool; 270 0:0 full => bool; 271 } 272 273 pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ 0x0000011c { 274 31:0 offs => u32; 275 } 276 277 pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ 0x00000128 { 278 8:0 base; 279 } 280 281 pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ 0x0000012c { 282 /// Core revision subversion. 283 7:6 core_rev_subversion => FalconCoreRevSubversion; 284 /// Security model. 285 5:4 security_model ?=> FalconSecurityModel; 286 /// Core revision. 287 3:0 core_rev ?=> FalconCoreRev; 288 } 289 290 pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ 0x00000130 { 291 1:1 startcpu => bool; 292 } 293 294 /// IMEM access control register. Up to 4 ports are available for IMEM access. 295 pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ 0x00000180 { 296 /// Access secure IMEM. 297 28:28 secure => bool; 298 /// Auto-increment on write. 299 24:24 aincw => bool; 300 /// IMEM block and word offset. 301 15:0 offs; 302 } 303 304 /// IMEM data register. Reading/writing this register accesses IMEM at the address 305 /// specified by the corresponding IMEMC register. 306 pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ 0x00000184 { 307 31:0 data; 308 } 309 310 /// IMEM tag register. Used to set the tag for the current IMEM block. 311 pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ 0x00000188 { 312 15:0 tag; 313 } 314 315 /// DMEM access control register. Up to 8 ports are available for DMEM access. 316 pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ 0x000001c0 { 317 /// Auto-increment on write. 318 24:24 aincw => bool; 319 /// DMEM block and word offset. 320 15:0 offs; 321 } 322 323 /// DMEM data register. Reading/writing this register accesses DMEM at the address 324 /// specified by the corresponding DMEMC register. 325 pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ 0x000001c4 { 326 31:0 data; 327 } 328 329 /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the 330 /// falcon instance. 331 pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ 0x000003c0 { 332 0:0 reset => bool; 333 } 334 335 pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ 0x00000600 { 336 2:2 mem_type => FalconFbifMemType; 337 1:0 target ?=> FalconFbifTarget; 338 } 339 340 pub(crate) NV_PFALCON_FBIF_CTL(u32) @ 0x00000624 { 341 7:7 allow_phys_no_ctx => bool; 342 } 343 344 // Falcon EMEM PIO registers (used by FSP on Hopper/Blackwell). 345 // These provide the falcon external memory communication interface. 346 347 pub(crate) NV_PFALCON_FALCON_EMEMC(u32) @ 0x00000ac0 { 348 /// EMEM byte offset (4-byte aligned) within the block. 349 7:2 offs; 350 /// EMEM block to access. 351 15:8 blk; 352 /// Auto-increment the offset after each write. 353 24:24 aincw => bool; 354 /// Auto-increment the offset after each read. 355 25:25 aincr => bool; 356 } 357 358 pub(crate) NV_PFALCON_FALCON_EMEMD(u32) @ 0x00000ac4 { 359 31:0 data => u32; 360 } 361 } 362 363 impl NV_PFALCON_FALCON_DMACTL { 364 /// Returns `true` if memory scrubbing is completed. 365 pub(crate) fn mem_scrubbing_done(self) -> bool { 366 !self.dmem_scrubbing() && !self.imem_scrubbing() 367 } 368 } 369 370 impl NV_PFALCON_FALCON_DMATRFCMD { 371 /// Programs the `imem` and `sec` fields for the given FalconMem 372 pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 373 let this = self.with_imem(mem != FalconMem::Dmem); 374 375 match mem { 376 FalconMem::ImemSecure => this.with_const_sec::<1>(), 377 _ => this.with_const_sec::<0>(), 378 } 379 } 380 } 381 382 impl NV_PFALCON_FALCON_ENGINE { 383 /// Resets the falcon 384 pub(crate) fn reset_engine(pfalcon: Mmio<'_, PFalconRegisters>) { 385 pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(true)); 386 387 // TIMEOUT: falcon engine should not take more than 10us to reset. 388 time::delay::fsleep(time::Delta::from_micros(10)); 389 390 pfalcon.update(NV_PFALCON_FALCON_ENGINE, |r| r.with_reset(false)); 391 } 392 } 393 394 impl NV_PFALCON_FALCON_HWCFG2 { 395 /// Returns `true` if memory scrubbing is completed. 396 pub(crate) fn mem_scrubbing_done(self) -> bool { 397 !self.mem_scrubbing() 398 } 399 } 400 401 /* PFALCON2 */ 402 403 register! { 404 base: PFalcon2Registers; 405 406 pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ 0x00000180 { 407 7:0 algo ?=> FalconModSelAlgo; 408 } 409 410 pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ 0x00000198 { 411 7:0 ucode_id => u8; 412 } 413 414 pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ 0x0000019c { 415 31:0 value => u32; 416 } 417 418 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 419 /// first element. Be conservative until we know the actual size or need to use more registers. 420 pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ 0x00000210 { 421 31:0 value => u32; 422 } 423 } 424 425 // PRISCV 426 427 register! { 428 base: PFalcon2Registers; 429 430 /// RISC-V status register for debug (Turing and GA100 only). 431 /// Reflects current RISC-V core status. 432 pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ 0x00000240 { 433 /// RISC-V core active/inactive status. 434 0:0 active_stat => bool; 435 } 436 437 /// GA102 and later. 438 pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ 0x00000388 { 439 7:7 active_stat => bool; 440 4:4 halted => bool; 441 } 442 443 /// GA102 and later. 444 pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ 0x00000668 { 445 8:8 br_fetch => bool; 446 4:4 core_select => PeregrineCoreSelect; 447 0:0 valid => bool; 448 } 449 } 450 451 // FSP (Foundation Security Processor) queue registers for Hopper/Blackwell Chain of Trust. 452 // These registers manage falcon EMEM communication queues. 453 454 register! { 455 base: NovaRegisters; 456 457 pub(crate) NV_PFSP_QUEUE_HEAD(u32)[8] @ 0x008f2c00 { 458 31:0 address => u32; 459 } 460 461 pub(crate) NV_PFSP_QUEUE_TAIL(u32)[8] @ 0x008f2c04 { 462 31:0 address => u32; 463 } 464 465 pub(crate) NV_PFSP_MSGQ_HEAD(u32)[8] @ 0x008f2c80 { 466 31:0 val => u32; 467 } 468 469 pub(crate) NV_PFSP_MSGQ_TAIL(u32)[8] @ 0x008f2c84 { 470 31:0 val => u32; 471 } 472 } 473 474 // The modules below provide registers that are not identical on all supported chips. They should 475 // only be used in HAL modules. 476 477 pub(crate) mod gm107 { 478 use kernel::io::register; 479 480 use crate::driver::NovaRegisters; 481 482 // FUSE 483 484 register! { 485 base: NovaRegisters; 486 487 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 { 488 0:0 display_disabled => bool; 489 } 490 } 491 } 492 493 pub(crate) mod ga100 { 494 use kernel::io::register; 495 496 use crate::driver::NovaRegisters; 497 498 // FUSE 499 500 register! { 501 base: NovaRegisters; 502 503 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 { 504 0:0 display_disabled => bool; 505 } 506 } 507 } 508 509 pub(crate) const NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS: u32 = 0xff; 510 511 pub(crate) mod gh100 { 512 use kernel::io::register; 513 514 use crate::driver::NovaRegisters; 515 516 // PTHERM 517 518 register! { 519 base: NovaRegisters; 520 521 pub(crate) NV_THERM_I2CS_SCRATCH(u32) @ 0x000200bc { 522 31:0 data; 523 } 524 525 // Alias to `NV_THERM_I2CS_SCRATCH` when used to check for FSP boot completion. 526 pub(crate) NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE(u32) => NV_THERM_I2CS_SCRATCH { 527 31:0 fsp_boot_complete; 528 } 529 } 530 } 531 532 pub(crate) mod gb202 { 533 use kernel::io::register; 534 535 use crate::driver::NovaRegisters; 536 537 // PTHERM 538 539 register! { 540 base: NovaRegisters; 541 542 pub(crate) NV_THERM_I2CS_SCRATCH(u32) @ 0x00ad00bc { 543 31:0 data; 544 } 545 546 // Alias to `NV_THERM_I2CS_SCRATCH` when used to check for FSP boot completion. 547 pub(crate) NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE(u32) => NV_THERM_I2CS_SCRATCH { 548 31:0 fsp_boot_complete; 549 } 550 } 551 } 552