1 // SPDX-License-Identifier: GPL-2.0 2 3 use kernel::{ 4 io::{ 5 register, 6 register::WithBase, 7 Io, // 8 }, 9 prelude::*, 10 time, // 11 }; 12 13 use crate::{ 14 driver::Bar0, 15 falcon::{ 16 DmaTrfCmdSize, 17 FalconCoreRev, 18 FalconCoreRevSubversion, 19 FalconEngine, 20 FalconFbifMemType, 21 FalconFbifTarget, 22 FalconMem, 23 FalconModSelAlgo, 24 FalconSecurityModel, 25 PFalcon2Base, 26 PFalconBase, 27 PeregrineCoreSelect, // 28 }, 29 gpu::{ 30 Architecture, 31 Chipset, // 32 }, 33 num::FromSafeCast, 34 }; 35 36 // PMC 37 38 register! { 39 /// Basic revision information about the GPU. 40 pub(crate) NV_PMC_BOOT_0(u32) @ 0x00000000 { 41 /// Lower bits of the architecture. 42 28:24 architecture_0; 43 /// Implementation version of the architecture. 44 23:20 implementation; 45 /// MSB of the architecture. 46 8:8 architecture_1; 47 /// Major revision of the chip. 48 7:4 major_revision; 49 /// Minor revision of the chip. 50 3:0 minor_revision; 51 } 52 53 /// Extended architecture information. 54 pub(crate) NV_PMC_BOOT_42(u32) @ 0x00000a00 { 55 /// Architecture value. 56 29:24 architecture ?=> Architecture; 57 /// Implementation version of the architecture. 58 23:20 implementation; 59 /// Major revision of the chip. 60 19:16 major_revision; 61 /// Minor revision of the chip. 62 15:12 minor_revision; 63 } 64 } 65 66 impl NV_PMC_BOOT_0 { 67 pub(crate) fn is_older_than_fermi(self) -> bool { 68 // From https://github.com/NVIDIA/open-gpu-doc/tree/master/manuals : 69 const NV_PMC_BOOT_0_ARCHITECTURE_GF100: u32 = 0xc; 70 71 // Older chips left arch1 zeroed out. That, combined with an arch0 value that is less than 72 // GF100, means "older than Fermi". 73 self.architecture_1() == 0 && self.architecture_0() < NV_PMC_BOOT_0_ARCHITECTURE_GF100 74 } 75 } 76 77 impl NV_PMC_BOOT_42 { 78 /// Combines `architecture` and `implementation` to obtain a code unique to the chipset. 79 pub(crate) fn chipset(self) -> Result<Chipset> { 80 self.architecture() 81 .map(|arch| { 82 ((arch as u32) << Self::IMPLEMENTATION_RANGE.len()) 83 | u32::from(self.implementation()) 84 }) 85 .and_then(Chipset::try_from) 86 } 87 88 /// Returns the raw architecture value from the register. 89 fn architecture_raw(self) -> u8 { 90 ((self.into_raw() >> Self::ARCHITECTURE_RANGE.start()) 91 & ((1 << Self::ARCHITECTURE_RANGE.len()) - 1)) as u8 92 } 93 } 94 95 impl kernel::fmt::Display for NV_PMC_BOOT_42 { 96 fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) -> kernel::fmt::Result { 97 write!( 98 f, 99 "boot42 = 0x{:08x} (architecture 0x{:x}, implementation 0x{:x})", 100 self.inner, 101 self.architecture_raw(), 102 self.implementation() 103 ) 104 } 105 } 106 107 // PBUS 108 109 register! { 110 pub(crate) NV_PBUS_SW_SCRATCH(u32)[64] @ 0x00001400 {} 111 112 /// Scratch register 0xe used as FRTS firmware error code. 113 pub(crate) NV_PBUS_SW_SCRATCH_0E_FRTS_ERR(u32) => NV_PBUS_SW_SCRATCH[0xe] { 114 31:16 frts_err_code; 115 } 116 } 117 118 // PFB 119 120 register! { 121 /// Low bits of the physical system memory address used by the GPU to perform sysmembar 122 /// operations (see [`crate::fb::SysmemFlush`]). 123 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR(u32) @ 0x00100c10 { 124 31:0 adr_39_08; 125 } 126 127 /// High bits of the physical system memory address used by the GPU to perform sysmembar 128 /// operations (see [`crate::fb::SysmemFlush`]). 129 pub(crate) NV_PFB_NISO_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00100c40 { 130 23:0 adr_63_40; 131 } 132 133 pub(crate) NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE(u32) @ 0x00100ce0 { 134 30:30 ecc_mode_enabled => bool; 135 9:4 lower_mag; 136 3:0 lower_scale; 137 } 138 139 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_LO(u32) @ 0x001fa824 { 140 /// Bits 12..40 of the lower (inclusive) bound of the WPR2 region. 141 31:4 lo_val; 142 } 143 144 pub(crate) NV_PFB_PRI_MMU_WPR2_ADDR_HI(u32) @ 0x001fa828 { 145 /// Bits 12..40 of the higher (exclusive) bound of the WPR2 region. 146 31:4 hi_val; 147 } 148 } 149 150 impl NV_PFB_PRI_MMU_LOCAL_MEMORY_RANGE { 151 /// Returns the usable framebuffer size, in bytes. 152 pub(crate) fn usable_fb_size(self) -> u64 { 153 let size = (u64::from(self.lower_mag()) << u64::from(self.lower_scale())) 154 * u64::from_safe_cast(kernel::sizes::SZ_1M); 155 156 if self.ecc_mode_enabled() { 157 // Remove the amount of memory reserved for ECC (one per 16 units). 158 size / 16 * 15 159 } else { 160 size 161 } 162 } 163 } 164 165 impl NV_PFB_PRI_MMU_WPR2_ADDR_LO { 166 /// Returns the lower (inclusive) bound of the WPR2 region. 167 pub(crate) fn lower_bound(self) -> u64 { 168 u64::from(self.lo_val()) << 12 169 } 170 } 171 172 impl NV_PFB_PRI_MMU_WPR2_ADDR_HI { 173 /// Returns the higher (exclusive) bound of the WPR2 region. 174 /// 175 /// A value of zero means the WPR2 region is not set. 176 pub(crate) fn higher_bound(self) -> u64 { 177 u64::from(self.hi_val()) << 12 178 } 179 } 180 181 // PGSP 182 183 register! { 184 pub(crate) NV_PGSP_QUEUE_HEAD(u32) @ 0x00110c00 { 185 31:0 address; 186 } 187 } 188 189 // PGC6 register space. 190 // 191 // `GC6` is a GPU low-power state where VRAM is in self-refresh and the GPU is powered down (except 192 // for power rails needed to keep self-refresh working and important registers and hardware 193 // blocks). 194 // 195 // These scratch registers remain powered on even in a low-power state and have a designated group 196 // number. 197 198 register! { 199 /// Boot Sequence Interface (BSI) register used to determine 200 /// if GSP reload/resume has completed during the boot process. 201 pub(crate) NV_PGC6_BSI_SECURE_SCRATCH_14(u32) @ 0x001180f8 { 202 26:26 boot_stage_3_handoff => bool; 203 } 204 205 /// Privilege level mask register. It dictates whether the host CPU has privilege to access the 206 /// `PGC6_AON_SECURE_SCRATCH_GROUP_05` register (which it needs to read GFW_BOOT). 207 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK(u32) @ 0x00118128 { 208 /// Set after FWSEC lowers its protection level. 209 0:0 read_protection_level0 => bool; 210 } 211 212 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 213 /// first element. Be conservative until we know the actual size or need to use more registers. 214 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05(u32)[1] @ 0x00118234 {} 215 216 /// Scratch group 05 register 0 used as GFW boot progress indicator. 217 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT(u32) 218 => NV_PGC6_AON_SECURE_SCRATCH_GROUP_05[0] { 219 /// Progress of GFW boot (0xff means completed). 220 7:0 progress; 221 } 222 223 pub(crate) NV_PGC6_AON_SECURE_SCRATCH_GROUP_42(u32) @ 0x001183a4 { 224 31:0 value; 225 } 226 227 /// Scratch group 42 register used as framebuffer size. 228 pub(crate) NV_USABLE_FB_SIZE_IN_MB(u32) => NV_PGC6_AON_SECURE_SCRATCH_GROUP_42 { 229 /// Usable framebuffer size, in megabytes. 230 31:0 value; 231 } 232 } 233 234 impl NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT { 235 /// Returns `true` if GFW boot is completed. 236 pub(crate) fn completed(self) -> bool { 237 self.progress() == 0xff 238 } 239 } 240 241 impl NV_USABLE_FB_SIZE_IN_MB { 242 /// Returns the usable framebuffer size, in bytes. 243 pub(crate) fn usable_fb_size(self) -> u64 { 244 u64::from(self.value()) * u64::from_safe_cast(kernel::sizes::SZ_1M) 245 } 246 } 247 248 // PDISP 249 250 register! { 251 pub(crate) NV_PDISP_VGA_WORKSPACE_BASE(u32) @ 0x00625f04 { 252 /// VGA workspace base address divided by 0x10000. 253 31:8 addr; 254 /// Set if the `addr` field is valid. 255 3:3 status_valid => bool; 256 } 257 } 258 259 impl NV_PDISP_VGA_WORKSPACE_BASE { 260 /// Returns the base address of the VGA workspace, or `None` if none exists. 261 pub(crate) fn vga_workspace_addr(self) -> Option<u64> { 262 if self.status_valid() { 263 Some(u64::from(self.addr()) << 16) 264 } else { 265 None 266 } 267 } 268 } 269 270 // FUSE 271 272 pub(crate) const NV_FUSE_OPT_FPF_SIZE: usize = 16; 273 274 register! { 275 pub(crate) NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824100 { 276 15:0 data => u16; 277 } 278 279 pub(crate) NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x00824140 { 280 15:0 data => u16; 281 } 282 283 pub(crate) NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION(u32)[NV_FUSE_OPT_FPF_SIZE] @ 0x008241c0 { 284 15:0 data => u16; 285 } 286 } 287 288 // PFALCON 289 290 register! { 291 pub(crate) NV_PFALCON_FALCON_IRQSCLR(u32) @ PFalconBase + 0x00000004 { 292 6:6 swgen0 => bool; 293 4:4 halt => bool; 294 } 295 296 pub(crate) NV_PFALCON_FALCON_MAILBOX0(u32) @ PFalconBase + 0x00000040 { 297 31:0 value => u32; 298 } 299 300 pub(crate) NV_PFALCON_FALCON_MAILBOX1(u32) @ PFalconBase + 0x00000044 { 301 31:0 value => u32; 302 } 303 304 /// Used to store version information about the firmware running 305 /// on the Falcon processor. 306 pub(crate) NV_PFALCON_FALCON_OS(u32) @ PFalconBase + 0x00000080 { 307 31:0 value => u32; 308 } 309 310 pub(crate) NV_PFALCON_FALCON_RM(u32) @ PFalconBase + 0x00000084 { 311 31:0 value => u32; 312 } 313 314 pub(crate) NV_PFALCON_FALCON_HWCFG2(u32) @ PFalconBase + 0x000000f4 { 315 /// Signal indicating that reset is completed (GA102+). 316 31:31 reset_ready => bool; 317 /// Set to 0 after memory scrubbing is completed. 318 12:12 mem_scrubbing => bool; 319 10:10 riscv => bool; 320 } 321 322 pub(crate) NV_PFALCON_FALCON_CPUCTL(u32) @ PFalconBase + 0x00000100 { 323 6:6 alias_en => bool; 324 4:4 halted => bool; 325 1:1 startcpu => bool; 326 } 327 328 pub(crate) NV_PFALCON_FALCON_BOOTVEC(u32) @ PFalconBase + 0x00000104 { 329 31:0 value => u32; 330 } 331 332 pub(crate) NV_PFALCON_FALCON_DMACTL(u32) @ PFalconBase + 0x0000010c { 333 7:7 secure_stat => bool; 334 6:3 dmaq_num; 335 2:2 imem_scrubbing => bool; 336 1:1 dmem_scrubbing => bool; 337 0:0 require_ctx => bool; 338 } 339 340 pub(crate) NV_PFALCON_FALCON_DMATRFBASE(u32) @ PFalconBase + 0x00000110 { 341 31:0 base => u32; 342 } 343 344 pub(crate) NV_PFALCON_FALCON_DMATRFMOFFS(u32) @ PFalconBase + 0x00000114 { 345 23:0 offs; 346 } 347 348 pub(crate) NV_PFALCON_FALCON_DMATRFCMD(u32) @ PFalconBase + 0x00000118 { 349 16:16 set_dmtag; 350 14:12 ctxdma; 351 10:8 size ?=> DmaTrfCmdSize; 352 5:5 is_write => bool; 353 4:4 imem => bool; 354 3:2 sec; 355 1:1 idle => bool; 356 0:0 full => bool; 357 } 358 359 pub(crate) NV_PFALCON_FALCON_DMATRFFBOFFS(u32) @ PFalconBase + 0x0000011c { 360 31:0 offs => u32; 361 } 362 363 pub(crate) NV_PFALCON_FALCON_DMATRFBASE1(u32) @ PFalconBase + 0x00000128 { 364 8:0 base; 365 } 366 367 pub(crate) NV_PFALCON_FALCON_HWCFG1(u32) @ PFalconBase + 0x0000012c { 368 /// Core revision subversion. 369 7:6 core_rev_subversion => FalconCoreRevSubversion; 370 /// Security model. 371 5:4 security_model ?=> FalconSecurityModel; 372 /// Core revision. 373 3:0 core_rev ?=> FalconCoreRev; 374 } 375 376 pub(crate) NV_PFALCON_FALCON_CPUCTL_ALIAS(u32) @ PFalconBase + 0x00000130 { 377 1:1 startcpu => bool; 378 } 379 380 /// IMEM access control register. Up to 4 ports are available for IMEM access. 381 pub(crate) NV_PFALCON_FALCON_IMEMC(u32)[4, stride = 16] @ PFalconBase + 0x00000180 { 382 /// Access secure IMEM. 383 28:28 secure => bool; 384 /// Auto-increment on write. 385 24:24 aincw => bool; 386 /// IMEM block and word offset. 387 15:0 offs; 388 } 389 390 /// IMEM data register. Reading/writing this register accesses IMEM at the address 391 /// specified by the corresponding IMEMC register. 392 pub(crate) NV_PFALCON_FALCON_IMEMD(u32)[4, stride = 16] @ PFalconBase + 0x00000184 { 393 31:0 data; 394 } 395 396 /// IMEM tag register. Used to set the tag for the current IMEM block. 397 pub(crate) NV_PFALCON_FALCON_IMEMT(u32)[4, stride = 16] @ PFalconBase + 0x00000188 { 398 15:0 tag; 399 } 400 401 /// DMEM access control register. Up to 8 ports are available for DMEM access. 402 pub(crate) NV_PFALCON_FALCON_DMEMC(u32)[8, stride = 8] @ PFalconBase + 0x000001c0 { 403 /// Auto-increment on write. 404 24:24 aincw => bool; 405 /// DMEM block and word offset. 406 15:0 offs; 407 } 408 409 /// DMEM data register. Reading/writing this register accesses DMEM at the address 410 /// specified by the corresponding DMEMC register. 411 pub(crate) NV_PFALCON_FALCON_DMEMD(u32)[8, stride = 8] @ PFalconBase + 0x000001c4 { 412 31:0 data; 413 } 414 415 /// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the 416 /// falcon instance. 417 pub(crate) NV_PFALCON_FALCON_ENGINE(u32) @ PFalconBase + 0x000003c0 { 418 0:0 reset => bool; 419 } 420 421 pub(crate) NV_PFALCON_FBIF_TRANSCFG(u32)[8] @ PFalconBase + 0x00000600 { 422 2:2 mem_type => FalconFbifMemType; 423 1:0 target ?=> FalconFbifTarget; 424 } 425 426 pub(crate) NV_PFALCON_FBIF_CTL(u32) @ PFalconBase + 0x00000624 { 427 7:7 allow_phys_no_ctx => bool; 428 } 429 } 430 431 impl NV_PFALCON_FALCON_DMACTL { 432 /// Returns `true` if memory scrubbing is completed. 433 pub(crate) fn mem_scrubbing_done(self) -> bool { 434 !self.dmem_scrubbing() && !self.imem_scrubbing() 435 } 436 } 437 438 impl NV_PFALCON_FALCON_DMATRFCMD { 439 /// Programs the `imem` and `sec` fields for the given FalconMem 440 pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { 441 let this = self.with_imem(mem != FalconMem::Dmem); 442 443 match mem { 444 FalconMem::ImemSecure => this.with_const_sec::<1>(), 445 _ => this.with_const_sec::<0>(), 446 } 447 } 448 } 449 450 impl NV_PFALCON_FALCON_ENGINE { 451 /// Resets the falcon 452 pub(crate) fn reset_engine<E: FalconEngine>(bar: &Bar0) { 453 bar.update(Self::of::<E>(), |r| r.with_reset(true)); 454 455 // TIMEOUT: falcon engine should not take more than 10us to reset. 456 time::delay::fsleep(time::Delta::from_micros(10)); 457 458 bar.update(Self::of::<E>(), |r| r.with_reset(false)); 459 } 460 } 461 462 impl NV_PFALCON_FALCON_HWCFG2 { 463 /// Returns `true` if memory scrubbing is completed. 464 pub(crate) fn mem_scrubbing_done(self) -> bool { 465 !self.mem_scrubbing() 466 } 467 } 468 469 /* PFALCON2 */ 470 471 register! { 472 pub(crate) NV_PFALCON2_FALCON_MOD_SEL(u32) @ PFalcon2Base + 0x00000180 { 473 7:0 algo ?=> FalconModSelAlgo; 474 } 475 476 pub(crate) NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID(u32) @ PFalcon2Base + 0x00000198 { 477 7:0 ucode_id => u8; 478 } 479 480 pub(crate) NV_PFALCON2_FALCON_BROM_ENGIDMASK(u32) @ PFalcon2Base + 0x0000019c { 481 31:0 value => u32; 482 } 483 484 /// OpenRM defines this as a register array, but doesn't specify its size and only uses its 485 /// first element. Be conservative until we know the actual size or need to use more registers. 486 pub(crate) NV_PFALCON2_FALCON_BROM_PARAADDR(u32)[1] @ PFalcon2Base + 0x00000210 { 487 31:0 value => u32; 488 } 489 } 490 491 // PRISCV 492 493 register! { 494 /// RISC-V status register for debug (Turing and GA100 only). 495 /// Reflects current RISC-V core status. 496 pub(crate) NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS(u32) @ PFalcon2Base + 0x00000240 { 497 /// RISC-V core active/inactive status. 498 0:0 active_stat => bool; 499 } 500 501 /// GA102 and later. 502 pub(crate) NV_PRISCV_RISCV_CPUCTL(u32) @ PFalcon2Base + 0x00000388 { 503 7:7 active_stat => bool; 504 0:0 halted => bool; 505 } 506 507 /// GA102 and later. 508 pub(crate) NV_PRISCV_RISCV_BCR_CTRL(u32) @ PFalcon2Base + 0x00000668 { 509 8:8 br_fetch => bool; 510 4:4 core_select => PeregrineCoreSelect; 511 0:0 valid => bool; 512 } 513 } 514 515 // The modules below provide registers that are not identical on all supported chips. They should 516 // only be used in HAL modules. 517 518 pub(crate) mod gm107 { 519 use kernel::io::register; 520 521 // FUSE 522 523 register! { 524 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00021c04 { 525 0:0 display_disabled => bool; 526 } 527 } 528 } 529 530 pub(crate) mod ga100 { 531 use kernel::io::register; 532 533 // FUSE 534 535 register! { 536 pub(crate) NV_FUSE_STATUS_OPT_DISPLAY(u32) @ 0x00820c04 { 537 0:0 display_disabled => bool; 538 } 539 } 540 } 541