1 // SPDX-License-Identifier: GPL-2.0 2 3 //! GPU Firmware (`GFW`) support, a.k.a `devinit`. 4 //! 5 //! Upon reset, the GPU runs some firmware code from the BIOS to setup its core parameters. Most of 6 //! the GPU is considered unusable until this step is completed, so we must wait on it before 7 //! performing driver initialization. 8 //! 9 //! A clarification about devinit terminology: devinit is a sequence of register read/writes after 10 //! reset that performs tasks such as: 11 //! 1. Programming VRAM memory controller timings. 12 //! 2. Power sequencing. 13 //! 3. Clock and PLL configuration. 14 //! 4. Thermal management. 15 //! 16 //! devinit itself is a 'script' which is interpreted by an interpreter program typically running 17 //! on the PMU microcontroller. 18 //! 19 //! Note that the devinit sequence also needs to run during suspend/resume. 20 21 use kernel::io::poll::read_poll_timeout; 22 use kernel::prelude::*; 23 use kernel::time::Delta; 24 25 use crate::driver::Bar0; 26 use crate::regs; 27 28 /// Wait for the `GFW` (GPU firmware) boot completion signal (`GFW_BOOT`), or a 4 seconds timeout. 29 /// 30 /// Upon GPU reset, several microcontrollers (such as PMU, SEC2, GSP etc) run some firmware code to 31 /// setup its core parameters. Most of the GPU is considered unusable until this step is completed, 32 /// so it must be waited on very early during driver initialization. 33 /// 34 /// The `GFW` code includes several components that need to execute before the driver loads. These 35 /// components are located in the VBIOS ROM and executed in a sequence on these different 36 /// microcontrollers. The devinit sequence typically runs on the PMU, and the FWSEC runs on the 37 /// GSP. 38 /// 39 /// This function waits for a signal indicating that core initialization is complete. Before this 40 /// signal is received, little can be done with the GPU. This signal is set by the FWSEC running on 41 /// the GSP in Heavy-secured mode. 42 pub(crate) fn wait_gfw_boot_completion(bar: &Bar0) -> Result { 43 // Before accessing the completion status in `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05`, we must 44 // first check `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK`. This is because 45 // `NV_PGC6_AON_SECURE_SCRATCH_GROUP_05` becomes accessible only after the secure firmware 46 // (FWSEC) lowers the privilege level to allow CPU (LS/Light-secured) access. We can only 47 // safely read the status register from CPU (LS/Light-secured) once the mask indicates 48 // that the privilege level has been lowered. 49 // 50 // TIMEOUT: arbitrarily large value. GFW starts running immediately after the GPU is put out of 51 // reset, and should complete in less time than that. 52 read_poll_timeout( 53 || { 54 Ok( 55 // Check that FWSEC has lowered its protection level before reading the GFW_BOOT 56 // status. 57 regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_PRIV_LEVEL_MASK::read(bar) 58 .read_protection_level0() 59 && regs::NV_PGC6_AON_SECURE_SCRATCH_GROUP_05_0_GFW_BOOT::read(bar).completed(), 60 ) 61 }, 62 |&gfw_booted| gfw_booted, 63 Delta::from_millis(1), 64 Delta::from_secs(4), 65 ) 66 .map(|_| ()) 67 } 68