1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <linux/iopoll.h> 9 #include <drm/drm_managed.h> 10 11 #include <generated/xe_wa_oob.h> 12 13 #include "abi/guc_actions_abi.h" 14 #include "abi/guc_errors_abi.h" 15 #include "regs/xe_gt_regs.h" 16 #include "regs/xe_gtt_defs.h" 17 #include "regs/xe_guc_regs.h" 18 #include "regs/xe_irq_regs.h" 19 #include "xe_bo.h" 20 #include "xe_configfs.h" 21 #include "xe_device.h" 22 #include "xe_force_wake.h" 23 #include "xe_gt.h" 24 #include "xe_gt_printk.h" 25 #include "xe_gt_sriov_vf.h" 26 #include "xe_gt_throttle.h" 27 #include "xe_guc_ads.h" 28 #include "xe_guc_buf.h" 29 #include "xe_guc_capture.h" 30 #include "xe_guc_ct.h" 31 #include "xe_guc_db_mgr.h" 32 #include "xe_guc_engine_activity.h" 33 #include "xe_guc_hwconfig.h" 34 #include "xe_guc_klv_helpers.h" 35 #include "xe_guc_log.h" 36 #include "xe_guc_pc.h" 37 #include "xe_guc_relay.h" 38 #include "xe_guc_submit.h" 39 #include "xe_memirq.h" 40 #include "xe_mmio.h" 41 #include "xe_platform_types.h" 42 #include "xe_sriov.h" 43 #include "xe_uc.h" 44 #include "xe_uc_fw.h" 45 #include "xe_wa.h" 46 #include "xe_wopcm.h" 47 48 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 49 struct xe_bo *bo) 50 { 51 struct xe_device *xe = guc_to_xe(guc); 52 u32 addr; 53 54 /* 55 * For most BOs, the address on the allocating tile is fine. However for 56 * some, e.g. G2G CTB, the address on a specific tile is required as it 57 * might be different for each tile. So, just always ask for the address 58 * on the target GuC. 59 */ 60 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 61 62 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 63 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 64 xe_assert(xe, addr < GUC_GGTT_TOP); 65 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); 66 67 return addr; 68 } 69 70 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 71 { 72 u32 level = xe_guc_log_get_level(&guc->log); 73 u32 flags = 0; 74 75 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 76 flags |= GUC_LOG_DISABLED; 77 else 78 flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level)); 79 80 return flags; 81 } 82 83 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 84 { 85 struct xe_device *xe = guc_to_xe(guc); 86 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 87 88 if (!xe->info.skip_guc_pc) 89 flags |= GUC_CTL_ENABLE_SLPC; 90 91 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) 92 flags |= GUC_CTL_ENABLE_PSMI_LOGGING; 93 94 return flags; 95 } 96 97 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 98 { 99 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 100 u32 flags; 101 102 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 103 #define LOG_UNIT SZ_1M 104 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 105 #else 106 #define LOG_UNIT SZ_4K 107 #define LOG_FLAG 0 108 #endif 109 110 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 111 #define CAPTURE_UNIT SZ_1M 112 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 113 #else 114 #define CAPTURE_UNIT SZ_4K 115 #define CAPTURE_FLAG 0 116 #endif 117 118 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 119 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 120 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 121 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 122 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 123 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 124 125 flags = GUC_LOG_VALID | 126 GUC_LOG_NOTIFY_ON_HALF_FULL | 127 CAPTURE_FLAG | 128 LOG_FLAG | 129 FIELD_PREP(GUC_LOG_CRASH, CRASH_BUFFER_SIZE / LOG_UNIT - 1) | 130 FIELD_PREP(GUC_LOG_DEBUG, DEBUG_BUFFER_SIZE / LOG_UNIT - 1) | 131 FIELD_PREP(GUC_LOG_CAPTURE, CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) | 132 FIELD_PREP(GUC_LOG_BUF_ADDR, offset); 133 134 #undef LOG_UNIT 135 #undef LOG_FLAG 136 #undef CAPTURE_UNIT 137 #undef CAPTURE_FLAG 138 139 return flags; 140 } 141 142 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 143 { 144 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 145 u32 flags = FIELD_PREP(GUC_ADS_ADDR, ads); 146 147 return flags; 148 } 149 150 static bool needs_wa_dual_queue(struct xe_gt *gt) 151 { 152 /* 153 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 154 * on RCS and CCSes with different address spaces, which on DG2 is 155 * required as a WA for an HW bug. 156 */ 157 if (XE_GT_WA(gt, 22011391025)) 158 return true; 159 160 /* 161 * On newer platforms, the HW has been updated to not allow parallel 162 * execution of different address spaces, so the RCS/CCS will stall the 163 * context switch if one of the other RCS/CCSes is busy with a different 164 * address space. While functionally correct, having a submission 165 * stalled on the HW limits the GuC ability to shuffle things around and 166 * can cause complications if the non-stalled submission runs for a long 167 * time, because the GuC doesn't know that the stalled submission isn't 168 * actually running and might declare it as hung. Therefore, we enable 169 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 170 * to move management back to the GuC. 171 */ 172 if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 173 return true; 174 175 return false; 176 } 177 178 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 179 { 180 struct xe_device *xe = guc_to_xe(guc); 181 struct xe_gt *gt = guc_to_gt(guc); 182 u32 flags = 0; 183 184 if (XE_GT_WA(gt, 22012773006)) 185 flags |= GUC_WA_POLLCS; 186 187 if (XE_GT_WA(gt, 14014475959)) 188 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 189 190 if (needs_wa_dual_queue(gt)) 191 flags |= GUC_WA_DUAL_QUEUE; 192 193 /* 194 * Wa_22011802037: FIXME - there's more to be done than simply setting 195 * this flag: make sure each CS is stopped when preparing for GT reset 196 * and wait for pending MI_FW. 197 */ 198 if (GRAPHICS_VERx100(xe) < 1270) 199 flags |= GUC_WA_PRE_PARSER; 200 201 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) 202 flags |= GUC_WA_CONTEXT_ISOLATION; 203 204 if (XE_GT_WA(gt, 18020744125) && 205 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 206 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 207 208 if (XE_GT_WA(gt, 1509372804)) 209 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 210 211 if (XE_GT_WA(gt, 14018913170)) 212 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 213 214 if (XE_GT_WA(gt, 16023683509)) 215 flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6; 216 217 return flags; 218 } 219 220 static u32 guc_ctl_devid(struct xe_guc *guc) 221 { 222 struct xe_device *xe = guc_to_xe(guc); 223 224 return (((u32)xe->info.devid) << 16) | xe->info.revid; 225 } 226 227 static void guc_print_params(struct xe_guc *guc) 228 { 229 struct xe_gt *gt = guc_to_gt(guc); 230 u32 *params = guc->params; 231 int i; 232 233 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 234 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 235 236 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 237 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 238 } 239 240 static void guc_init_params(struct xe_guc *guc) 241 { 242 u32 *params = guc->params; 243 244 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 245 params[GUC_CTL_FEATURE] = 0; 246 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 247 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 248 params[GUC_CTL_WA] = 0; 249 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 250 251 guc_print_params(guc); 252 } 253 254 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 255 { 256 u32 *params = guc->params; 257 258 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 259 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 260 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 261 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 262 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 263 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 264 265 guc_print_params(guc); 266 } 267 268 /* 269 * Initialize the GuC parameter block before starting the firmware 270 * transfer. These parameters are read by the firmware on startup 271 * and cannot be changed thereafter. 272 */ 273 static void guc_write_params(struct xe_guc *guc) 274 { 275 struct xe_gt *gt = guc_to_gt(guc); 276 int i; 277 278 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 279 280 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 281 282 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 283 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 284 } 285 286 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 287 u32 desc_addr, u32 buff_addr, u32 size) 288 { 289 struct xe_gt *gt = guc_to_gt(guc); 290 struct xe_device *xe = gt_to_xe(gt); 291 u32 action[] = { 292 XE_GUC_ACTION_REGISTER_G2G, 293 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 294 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 295 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 296 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 297 desc_addr, 298 buff_addr, 299 }; 300 301 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 302 xe_assert(xe, !(size % SZ_4K)); 303 304 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 305 } 306 307 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 308 { 309 struct xe_gt *gt = guc_to_gt(guc); 310 struct xe_device *xe = gt_to_xe(gt); 311 u32 action[] = { 312 XE_GUC_ACTION_DEREGISTER_G2G, 313 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 314 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 315 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 316 }; 317 318 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 319 320 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 321 } 322 323 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 324 325 #define G2G_BUFFER_SIZE (SZ_4K) 326 #define G2G_DESC_SIZE (64) 327 #define G2G_DESC_AREA_SIZE (SZ_4K) 328 329 /* 330 * Generate a unique id for each bi-directional CTB for each pair of 331 * near and far tiles/devices. The id can then be used as an index into 332 * a single allocation that is sub-divided into multiple CTBs. 333 * 334 * For example, with two devices per tile and two tiles, the table should 335 * look like: 336 * Far <tile>.<dev> 337 * 0.0 0.1 1.0 1.1 338 * N 0.0 --/-- 00/01 02/03 04/05 339 * e 0.1 01/00 --/-- 06/07 08/09 340 * a 1.0 03/02 07/06 --/-- 10/11 341 * r 1.1 05/04 09/08 11/10 --/-- 342 * 343 * Where each entry is Rx/Tx channel id. 344 * 345 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 346 * be reading from channel #11 and writing to channel #10. Whereas, 347 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 348 */ 349 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 350 u32 type, u32 max_inst, bool have_dev) 351 { 352 u32 near = near_tile, far = far_tile; 353 u32 idx = 0, x, y, direction; 354 int i; 355 356 if (have_dev) { 357 near = (near << 1) | near_dev; 358 far = (far << 1) | far_dev; 359 } 360 361 /* No need to send to one's self */ 362 if (far == near) 363 return -1; 364 365 if (far > near) { 366 /* Top right table half */ 367 x = far; 368 y = near; 369 370 /* T/R is 'forwards' direction */ 371 direction = type; 372 } else { 373 /* Bottom left table half */ 374 x = near; 375 y = far; 376 377 /* B/L is 'backwards' direction */ 378 direction = (1 - type); 379 } 380 381 /* Count the rows prior to the target */ 382 for (i = y; i > 0; i--) 383 idx += max_inst - i; 384 385 /* Count this row up to the target */ 386 idx += (x - 1 - y); 387 388 /* Slots are in Rx/Tx pairs */ 389 idx *= 2; 390 391 /* Pick Rx/Tx direction */ 392 idx += direction; 393 394 return idx; 395 } 396 397 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 398 { 399 struct xe_gt *near_gt = guc_to_gt(near_guc); 400 struct xe_device *xe = gt_to_xe(near_gt); 401 struct xe_bo *g2g_bo; 402 u32 near_tile = gt_to_tile(near_gt)->id; 403 u32 near_dev = G2G_DEV(near_gt); 404 u32 far_tile = gt_to_tile(far_gt)->id; 405 u32 far_dev = G2G_DEV(far_gt); 406 u32 max = xe->info.gt_count; 407 u32 base, desc, buf; 408 int slot; 409 410 /* G2G is not allowed between different cards */ 411 xe_assert(xe, xe == gt_to_xe(far_gt)); 412 413 g2g_bo = near_guc->g2g.bo; 414 xe_assert(xe, g2g_bo); 415 416 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 417 xe_assert(xe, slot >= 0); 418 419 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 420 desc = base + slot * G2G_DESC_SIZE; 421 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 422 423 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 424 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(g2g_bo)); 425 426 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 427 desc, buf, G2G_BUFFER_SIZE); 428 } 429 430 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 431 { 432 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 433 } 434 435 static u32 guc_g2g_size(struct xe_guc *guc) 436 { 437 struct xe_gt *gt = guc_to_gt(guc); 438 struct xe_device *xe = gt_to_xe(gt); 439 unsigned int count = xe->info.gt_count; 440 u32 num_channels = (count * (count - 1)) / 2; 441 442 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 443 444 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 445 } 446 447 static bool xe_guc_g2g_wanted(struct xe_device *xe) 448 { 449 /* Can't do GuC to GuC communication if there is only one GuC */ 450 if (xe->info.gt_count <= 1) 451 return false; 452 453 /* No current user */ 454 return false; 455 } 456 457 static int guc_g2g_alloc(struct xe_guc *guc) 458 { 459 struct xe_gt *gt = guc_to_gt(guc); 460 struct xe_device *xe = gt_to_xe(gt); 461 struct xe_tile *tile = gt_to_tile(gt); 462 struct xe_bo *bo; 463 u32 g2g_size; 464 465 if (guc->g2g.bo) 466 return 0; 467 468 if (gt->info.id != 0) { 469 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 470 struct xe_guc *root_guc = &root_gt->uc.guc; 471 struct xe_bo *bo; 472 473 bo = xe_bo_get(root_guc->g2g.bo); 474 if (!bo) 475 return -ENODEV; 476 477 guc->g2g.bo = bo; 478 guc->g2g.owned = false; 479 return 0; 480 } 481 482 g2g_size = guc_g2g_size(guc); 483 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 484 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 485 XE_BO_FLAG_GGTT | 486 XE_BO_FLAG_GGTT_ALL | 487 XE_BO_FLAG_GGTT_INVALIDATE | 488 XE_BO_FLAG_PINNED_NORESTORE); 489 if (IS_ERR(bo)) 490 return PTR_ERR(bo); 491 492 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 493 guc->g2g.bo = bo; 494 guc->g2g.owned = true; 495 496 return 0; 497 } 498 499 static void guc_g2g_fini(struct xe_guc *guc) 500 { 501 if (!guc->g2g.bo) 502 return; 503 504 /* Unpinning the owned object is handled by generic shutdown */ 505 if (!guc->g2g.owned) 506 xe_bo_put(guc->g2g.bo); 507 508 guc->g2g.bo = NULL; 509 } 510 511 static int guc_g2g_start(struct xe_guc *guc) 512 { 513 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 514 struct xe_device *xe = gt_to_xe(gt); 515 unsigned int i, j; 516 int t, err; 517 bool have_dev; 518 519 if (!guc->g2g.bo) { 520 int ret; 521 522 ret = guc_g2g_alloc(guc); 523 if (ret) 524 return ret; 525 } 526 527 /* GuC interface will need extending if more GT device types are ever created. */ 528 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 529 530 /* Channel numbering depends on whether there are multiple GTs per tile */ 531 have_dev = xe->info.gt_count > xe->info.tile_count; 532 533 for_each_gt(far_gt, xe, i) { 534 u32 far_tile, far_dev; 535 536 if (far_gt->info.id == gt->info.id) 537 continue; 538 539 far_tile = gt_to_tile(far_gt)->id; 540 far_dev = G2G_DEV(far_gt); 541 542 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 543 err = guc_g2g_register(guc, far_gt, t, have_dev); 544 if (err) { 545 while (--t >= 0) 546 guc_g2g_deregister(guc, far_tile, far_dev, t); 547 goto err_deregister; 548 } 549 } 550 } 551 552 return 0; 553 554 err_deregister: 555 for_each_gt(far_gt, xe, j) { 556 u32 tile, dev; 557 558 if (far_gt->info.id == gt->info.id) 559 continue; 560 561 if (j >= i) 562 break; 563 564 tile = gt_to_tile(far_gt)->id; 565 dev = G2G_DEV(far_gt); 566 567 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 568 guc_g2g_deregister(guc, tile, dev, t); 569 } 570 571 return err; 572 } 573 574 static int __guc_opt_in_features_enable(struct xe_guc *guc, u64 addr, u32 num_dwords) 575 { 576 u32 action[] = { 577 XE_GUC_ACTION_OPT_IN_FEATURE_KLV, 578 lower_32_bits(addr), 579 upper_32_bits(addr), 580 num_dwords 581 }; 582 583 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 584 } 585 586 static bool supports_dynamic_ics(struct xe_guc *guc) 587 { 588 struct xe_device *xe = guc_to_xe(guc); 589 struct xe_gt *gt = guc_to_gt(guc); 590 591 /* Dynamic ICS is available for PVC and Xe2 and newer platforms. */ 592 if (xe->info.platform != XE_PVC && GRAPHICS_VER(xe) < 20) 593 return false; 594 595 /* 596 * The feature is currently not compatible with multi-lrc, so the GuC 597 * does not support it at all on the media engines (which are the main 598 * users of mlrc). On the primary GT side, to avoid it being used in 599 * conjunction with mlrc, we only enable it if we are in single CCS 600 * mode. 601 */ 602 if (xe_gt_is_media_type(gt) || gt->ccs_mode > 1) 603 return false; 604 605 /* 606 * Dynamic ICS requires GuC v70.40.1, which maps to compatibility 607 * version v1.18.4. 608 */ 609 return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 4); 610 } 611 612 #define OPT_IN_MAX_DWORDS 16 613 int xe_guc_opt_in_features_enable(struct xe_guc *guc) 614 { 615 struct xe_device *xe = guc_to_xe(guc); 616 CLASS(xe_guc_buf, buf)(&guc->buf, OPT_IN_MAX_DWORDS); 617 u32 count = 0; 618 u32 *klvs; 619 int ret; 620 621 if (!xe_guc_buf_is_valid(buf)) 622 return -ENOBUFS; 623 624 klvs = xe_guc_buf_cpu_ptr(buf); 625 626 /* 627 * The extra CAT error type opt-in was added in GuC v70.17.0, which maps 628 * to compatibility version v1.7.0. 629 * Note that the GuC allows enabling this KLV even on platforms that do 630 * not support the extra type; in such case the returned type variable 631 * will be set to a known invalid value which we can check against. 632 */ 633 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 7, 0)) 634 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_EXT_CAT_ERR_TYPE); 635 636 if (supports_dynamic_ics(guc)) 637 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH); 638 639 if (count) { 640 xe_assert(xe, count <= OPT_IN_MAX_DWORDS); 641 642 ret = __guc_opt_in_features_enable(guc, xe_guc_buf_flush(buf), count); 643 if (ret < 0) { 644 xe_gt_err(guc_to_gt(guc), 645 "failed to enable GuC opt-in features: %pe\n", 646 ERR_PTR(ret)); 647 return ret; 648 } 649 } 650 651 return 0; 652 } 653 654 static void guc_fini_hw(void *arg) 655 { 656 struct xe_guc *guc = arg; 657 struct xe_gt *gt = guc_to_gt(guc); 658 unsigned int fw_ref; 659 660 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 661 xe_uc_sanitize_reset(&guc_to_gt(guc)->uc); 662 xe_force_wake_put(gt_to_fw(gt), fw_ref); 663 664 guc_g2g_fini(guc); 665 } 666 667 /** 668 * xe_guc_comm_init_early - early initialization of GuC communication 669 * @guc: the &xe_guc to initialize 670 * 671 * Must be called prior to first MMIO communication with GuC firmware. 672 */ 673 void xe_guc_comm_init_early(struct xe_guc *guc) 674 { 675 struct xe_gt *gt = guc_to_gt(guc); 676 677 if (xe_gt_is_media_type(gt)) 678 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 679 else 680 guc->notify_reg = GUC_HOST_INTERRUPT; 681 } 682 683 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 684 { 685 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 686 struct xe_device *xe = guc_to_xe(guc); 687 int ret; 688 689 if (!IS_DGFX(guc_to_xe(guc))) 690 return 0; 691 692 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 693 if (ret) 694 return ret; 695 696 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 697 if (ret) 698 return ret; 699 700 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 701 if (ret) 702 return ret; 703 704 return 0; 705 } 706 707 static int vf_guc_init_noalloc(struct xe_guc *guc) 708 { 709 struct xe_gt *gt = guc_to_gt(guc); 710 int err; 711 712 err = xe_gt_sriov_vf_bootstrap(gt); 713 if (err) 714 return err; 715 716 err = xe_gt_sriov_vf_query_config(gt); 717 if (err) 718 return err; 719 720 return 0; 721 } 722 723 int xe_guc_init_noalloc(struct xe_guc *guc) 724 { 725 struct xe_device *xe = guc_to_xe(guc); 726 struct xe_gt *gt = guc_to_gt(guc); 727 int ret; 728 729 xe_guc_comm_init_early(guc); 730 731 ret = xe_guc_ct_init_noalloc(&guc->ct); 732 if (ret) 733 goto out; 734 735 ret = xe_guc_relay_init(&guc->relay); 736 if (ret) 737 goto out; 738 739 if (IS_SRIOV_VF(xe)) { 740 ret = vf_guc_init_noalloc(guc); 741 if (ret) 742 goto out; 743 } 744 745 return 0; 746 747 out: 748 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 749 return ret; 750 } 751 752 int xe_guc_init(struct xe_guc *guc) 753 { 754 struct xe_device *xe = guc_to_xe(guc); 755 struct xe_gt *gt = guc_to_gt(guc); 756 int ret; 757 758 guc->fw.type = XE_UC_FW_TYPE_GUC; 759 ret = xe_uc_fw_init(&guc->fw); 760 if (ret) 761 return ret; 762 763 if (!xe_uc_fw_is_enabled(&guc->fw)) 764 return 0; 765 766 if (IS_SRIOV_VF(xe)) { 767 ret = xe_guc_ct_init(&guc->ct); 768 if (ret) 769 goto out; 770 return 0; 771 } 772 773 ret = xe_guc_log_init(&guc->log); 774 if (ret) 775 goto out; 776 777 ret = xe_guc_capture_init(guc); 778 if (ret) 779 goto out; 780 781 ret = xe_guc_ads_init(&guc->ads); 782 if (ret) 783 goto out; 784 785 ret = xe_guc_ct_init(&guc->ct); 786 if (ret) 787 goto out; 788 789 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 790 791 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 792 if (ret) 793 goto out; 794 795 guc_init_params(guc); 796 797 return 0; 798 799 out: 800 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 801 return ret; 802 } 803 804 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 805 { 806 int err; 807 808 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 809 if (err) 810 return err; 811 812 err = xe_guc_buf_cache_init(&guc->buf); 813 if (err) 814 return err; 815 816 /* XXX xe_guc_db_mgr_init not needed for now */ 817 818 return 0; 819 } 820 821 /** 822 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 823 * @guc: The GuC object 824 * 825 * Return: 0 on success, negative error code on error. 826 */ 827 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 828 { 829 int ret; 830 831 if (IS_SRIOV_VF(guc_to_xe(guc))) 832 return vf_guc_init_post_hwconfig(guc); 833 834 ret = xe_guc_realloc_post_hwconfig(guc); 835 if (ret) 836 return ret; 837 838 ret = xe_guc_ct_init_post_hwconfig(&guc->ct); 839 if (ret) 840 return ret; 841 842 guc_init_params_post_hwconfig(guc); 843 844 ret = xe_guc_submit_init(guc, ~0); 845 if (ret) 846 return ret; 847 848 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 849 if (ret) 850 return ret; 851 852 ret = xe_guc_pc_init(&guc->pc); 853 if (ret) 854 return ret; 855 856 ret = xe_guc_engine_activity_init(guc); 857 if (ret) 858 return ret; 859 860 ret = xe_guc_buf_cache_init(&guc->buf); 861 if (ret) 862 return ret; 863 864 return xe_guc_ads_init_post_hwconfig(&guc->ads); 865 } 866 867 int xe_guc_post_load_init(struct xe_guc *guc) 868 { 869 int ret; 870 871 xe_guc_ads_populate_post_load(&guc->ads); 872 873 ret = xe_guc_opt_in_features_enable(guc); 874 if (ret) 875 return ret; 876 877 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 878 ret = guc_g2g_start(guc); 879 if (ret) 880 return ret; 881 } 882 883 return xe_guc_submit_enable(guc); 884 } 885 886 int xe_guc_reset(struct xe_guc *guc) 887 { 888 struct xe_gt *gt = guc_to_gt(guc); 889 struct xe_mmio *mmio = >->mmio; 890 u32 guc_status, gdrst; 891 int ret; 892 893 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 894 895 if (IS_SRIOV_VF(gt_to_xe(gt))) 896 return xe_gt_sriov_vf_bootstrap(gt); 897 898 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 899 900 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 901 if (ret) { 902 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 903 goto err_out; 904 } 905 906 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 907 if (!(guc_status & GS_MIA_IN_RESET)) { 908 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 909 guc_status); 910 ret = -EIO; 911 goto err_out; 912 } 913 914 return 0; 915 916 err_out: 917 918 return ret; 919 } 920 921 static void guc_prepare_xfer(struct xe_guc *guc) 922 { 923 struct xe_gt *gt = guc_to_gt(guc); 924 struct xe_mmio *mmio = >->mmio; 925 struct xe_device *xe = guc_to_xe(guc); 926 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 927 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 928 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 929 GUC_ENABLE_MIA_CLOCK_GATING; 930 931 if (GRAPHICS_VERx100(xe) < 1250) 932 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 933 GUC_ENABLE_MIA_CACHING; 934 935 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 936 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 937 938 /* Must program this register before loading the ucode with DMA */ 939 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 940 941 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 942 943 /* Make sure GuC receives ARAT interrupts */ 944 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 945 } 946 947 /* 948 * Supporting MMIO & in memory RSA 949 */ 950 static int guc_xfer_rsa(struct xe_guc *guc) 951 { 952 struct xe_gt *gt = guc_to_gt(guc); 953 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 954 size_t copied; 955 int i; 956 957 if (guc->fw.rsa_size > 256) { 958 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 959 xe_uc_fw_rsa_offset(&guc->fw); 960 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 961 return 0; 962 } 963 964 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 965 if (copied < sizeof(rsa)) 966 return -ENOMEM; 967 968 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 969 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 970 971 return 0; 972 } 973 974 /* 975 * Wait for the GuC to start up. 976 * 977 * Measurements indicate this should take no more than 20ms (assuming the GT 978 * clock is at maximum frequency). However, thermal throttling and other issues 979 * can prevent the clock hitting max and thus making the load take significantly 980 * longer. Allow up to 3s as a safety margin in normal builds. For 981 * CONFIG_DRM_XE_DEBUG allow up to 10s to account for slower execution, issues 982 * in PCODE, driver, fan, etc. 983 * 984 * Keep checking the GUC_STATUS every 10ms with a debug message every 100 985 * attempts as a "I'm slow, but alive" message. Regardless, if it takes more 986 * than 200ms, emit a warning. 987 */ 988 989 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 990 #define GUC_LOAD_TIMEOUT_SEC 20 991 #else 992 #define GUC_LOAD_TIMEOUT_SEC 3 993 #endif 994 #define GUC_LOAD_TIME_WARN_MSEC 200 995 996 static void print_load_status_err(struct xe_gt *gt, u32 status) 997 { 998 struct xe_mmio *mmio = >->mmio; 999 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1000 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1001 1002 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1003 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1004 bootrom, ukernel, 1005 REG_FIELD_GET(GS_MIA_MASK, status), 1006 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1007 1008 switch (bootrom) { 1009 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1010 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1011 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1012 break; 1013 case XE_BOOTROM_STATUS_RSA_FAILED: 1014 xe_gt_err(gt, "firmware signature verification failed\n"); 1015 break; 1016 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1017 xe_gt_err(gt, "firmware production part check failure\n"); 1018 break; 1019 } 1020 1021 switch (ukernel) { 1022 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1023 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1024 break; 1025 case XE_GUC_LOAD_STATUS_EXCEPTION: 1026 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1027 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1028 break; 1029 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1030 xe_gt_err(gt, "illegal init/ADS data\n"); 1031 break; 1032 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1033 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1034 break; 1035 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1036 xe_gt_err(gt, "illegal workaround KLV data\n"); 1037 break; 1038 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1039 xe_gt_err(gt, "illegal feature flag specified\n"); 1040 break; 1041 } 1042 } 1043 1044 /* 1045 * Check GUC_STATUS looking for known terminal states (either completion or 1046 * failure) of either the microkernel status field or the boot ROM status field. 1047 * 1048 * Returns 1 for successful completion, -1 for failure and 0 for any 1049 * intermediate state. 1050 */ 1051 static int guc_load_done(struct xe_gt *gt, u32 *status, u32 *tries) 1052 { 1053 u32 ukernel, bootrom; 1054 1055 *status = xe_mmio_read32(>->mmio, GUC_STATUS); 1056 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status); 1057 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status); 1058 1059 switch (ukernel) { 1060 case XE_GUC_LOAD_STATUS_READY: 1061 return 1; 1062 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 1063 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 1064 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 1065 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 1066 case XE_GUC_LOAD_STATUS_BOOTROM_VERSION_MISMATCH: 1067 case XE_GUC_LOAD_STATUS_DPC_ERROR: 1068 case XE_GUC_LOAD_STATUS_EXCEPTION: 1069 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1070 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 1071 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1072 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1073 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1074 return -1; 1075 } 1076 1077 switch (bootrom) { 1078 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1079 case XE_BOOTROM_STATUS_RSA_FAILED: 1080 case XE_BOOTROM_STATUS_PAVPC_FAILED: 1081 case XE_BOOTROM_STATUS_WOPCM_FAILED: 1082 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 1083 case XE_BOOTROM_STATUS_JUMP_FAILED: 1084 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 1085 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 1086 case XE_BOOTROM_STATUS_EXCEPTION: 1087 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1088 return -1; 1089 } 1090 1091 if (++*tries >= 100) { 1092 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1093 1094 *tries = 0; 1095 xe_gt_dbg(gt, "GuC load still in progress, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 1096 xe_guc_pc_get_act_freq(guc_pc), 1097 xe_guc_pc_get_cur_freq_fw(guc_pc), 1098 *status, ukernel, bootrom); 1099 } 1100 1101 return 0; 1102 } 1103 1104 static int guc_wait_ucode(struct xe_guc *guc) 1105 { 1106 struct xe_gt *gt = guc_to_gt(guc); 1107 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1108 u32 before_freq, act_freq, cur_freq; 1109 u32 status = 0, tries = 0; 1110 ktime_t before; 1111 u64 delta_ms; 1112 int ret; 1113 1114 before_freq = xe_guc_pc_get_act_freq(guc_pc); 1115 before = ktime_get(); 1116 1117 ret = poll_timeout_us(ret = guc_load_done(gt, &status, &tries), ret, 1118 10 * USEC_PER_MSEC, 1119 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false); 1120 1121 delta_ms = ktime_to_ms(ktime_sub(ktime_get(), before)); 1122 act_freq = xe_guc_pc_get_act_freq(guc_pc); 1123 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc); 1124 1125 if (ret) { 1126 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n", 1127 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1128 xe_guc_pc_get_cur_freq_fw(guc_pc)); 1129 print_load_status_err(gt, status); 1130 1131 return -EPROTO; 1132 } 1133 1134 if (delta_ms > GUC_LOAD_TIME_WARN_MSEC) { 1135 xe_gt_warn(gt, "GuC load: excessive init time: %lldms! [status = 0x%08X]\n", 1136 delta_ms, status); 1137 xe_gt_warn(gt, "GuC load: excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1138 act_freq, cur_freq, before_freq, 1139 xe_gt_throttle_get_limit_reasons(gt)); 1140 } else { 1141 xe_gt_dbg(gt, "GuC load: init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X\n", 1142 delta_ms, act_freq, cur_freq, before_freq, status); 1143 } 1144 1145 return 0; 1146 } 1147 ALLOW_ERROR_INJECTION(guc_wait_ucode, ERRNO); 1148 1149 static int __xe_guc_upload(struct xe_guc *guc) 1150 { 1151 int ret; 1152 1153 /* Raise GT freq to speed up HuC/GuC load */ 1154 xe_guc_pc_raise_unslice(&guc->pc); 1155 1156 guc_write_params(guc); 1157 guc_prepare_xfer(guc); 1158 1159 /* 1160 * Note that GuC needs the CSS header plus uKernel code to be copied 1161 * by the DMA engine in one operation, whereas the RSA signature is 1162 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1163 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1164 * size > 256). The RSA size and therefore the way we provide it to the 1165 * HW is fixed for each platform and hard-coded in the bootrom. 1166 */ 1167 ret = guc_xfer_rsa(guc); 1168 if (ret) 1169 goto out; 1170 /* 1171 * Current uCode expects the code to be loaded at 8k; locations below 1172 * this are used for the stack. 1173 */ 1174 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1175 if (ret) 1176 goto out; 1177 1178 /* Wait for authentication */ 1179 ret = guc_wait_ucode(guc); 1180 if (ret) 1181 goto out; 1182 1183 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1184 return 0; 1185 1186 out: 1187 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1188 return ret; 1189 } 1190 1191 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1192 { 1193 struct xe_gt *gt = guc_to_gt(guc); 1194 int ret; 1195 1196 ret = xe_guc_hwconfig_init(guc); 1197 if (ret) 1198 return ret; 1199 1200 ret = xe_guc_enable_communication(guc); 1201 if (ret) 1202 return ret; 1203 1204 ret = xe_gt_sriov_vf_connect(gt); 1205 if (ret) 1206 goto err_out; 1207 1208 ret = xe_gt_sriov_vf_query_runtime(gt); 1209 if (ret) 1210 goto err_out; 1211 1212 return 0; 1213 1214 err_out: 1215 xe_guc_sanitize(guc); 1216 return ret; 1217 } 1218 1219 /** 1220 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1221 * @guc: The GuC object 1222 * 1223 * This function uploads a minimal GuC that does not support submissions but 1224 * in a state where the hwconfig table can be read. Next, it reads and parses 1225 * the hwconfig table so it can be used for subsequent steps in the driver load. 1226 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1227 * 1228 * Return: 0 on success, negative error code on error. 1229 */ 1230 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1231 { 1232 int ret; 1233 1234 if (IS_SRIOV_VF(guc_to_xe(guc))) 1235 return vf_guc_min_load_for_hwconfig(guc); 1236 1237 xe_guc_ads_populate_minimal(&guc->ads); 1238 1239 xe_guc_pc_init_early(&guc->pc); 1240 1241 ret = __xe_guc_upload(guc); 1242 if (ret) 1243 return ret; 1244 1245 ret = xe_guc_hwconfig_init(guc); 1246 if (ret) 1247 return ret; 1248 1249 ret = xe_guc_enable_communication(guc); 1250 if (ret) 1251 return ret; 1252 1253 return 0; 1254 } 1255 1256 int xe_guc_upload(struct xe_guc *guc) 1257 { 1258 xe_guc_ads_populate(&guc->ads); 1259 1260 return __xe_guc_upload(guc); 1261 } 1262 1263 static void guc_handle_mmio_msg(struct xe_guc *guc) 1264 { 1265 struct xe_gt *gt = guc_to_gt(guc); 1266 u32 msg; 1267 1268 if (IS_SRIOV_VF(guc_to_xe(guc))) 1269 return; 1270 1271 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1272 1273 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1274 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1275 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1276 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1277 1278 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1279 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1280 1281 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1282 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1283 } 1284 1285 static void guc_enable_irq(struct xe_guc *guc) 1286 { 1287 struct xe_gt *gt = guc_to_gt(guc); 1288 u32 events = xe_gt_is_media_type(gt) ? 1289 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1290 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1291 1292 /* Primary GuC and media GuC share a single enable bit */ 1293 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1294 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1295 1296 /* 1297 * There are separate mask bits for primary and media GuCs, so use 1298 * a RMW operation to avoid clobbering the other GuC's setting. 1299 */ 1300 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1301 } 1302 1303 int xe_guc_enable_communication(struct xe_guc *guc) 1304 { 1305 struct xe_device *xe = guc_to_xe(guc); 1306 int err; 1307 1308 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1309 struct xe_gt *gt = guc_to_gt(guc); 1310 struct xe_tile *tile = gt_to_tile(gt); 1311 1312 err = xe_memirq_init_guc(&tile->memirq, guc); 1313 if (err) 1314 return err; 1315 } else { 1316 guc_enable_irq(guc); 1317 } 1318 1319 err = xe_guc_ct_enable(&guc->ct); 1320 if (err) 1321 return err; 1322 1323 guc_handle_mmio_msg(guc); 1324 1325 return 0; 1326 } 1327 1328 int xe_guc_suspend(struct xe_guc *guc) 1329 { 1330 struct xe_gt *gt = guc_to_gt(guc); 1331 u32 action[] = { 1332 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1333 }; 1334 int ret; 1335 1336 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1337 if (ret) { 1338 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1339 return ret; 1340 } 1341 1342 xe_guc_sanitize(guc); 1343 return 0; 1344 } 1345 1346 void xe_guc_notify(struct xe_guc *guc) 1347 { 1348 struct xe_gt *gt = guc_to_gt(guc); 1349 const u32 default_notify_data = 0; 1350 1351 /* 1352 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1353 * additional payload data to the GuC but this capability is not 1354 * used by the firmware yet. Use default value in the meantime. 1355 */ 1356 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1357 } 1358 1359 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1360 { 1361 u32 action[] = { 1362 XE_GUC_ACTION_AUTHENTICATE_HUC, 1363 rsa_addr 1364 }; 1365 1366 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1367 } 1368 1369 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1370 u32 len, u32 *response_buf) 1371 { 1372 struct xe_device *xe = guc_to_xe(guc); 1373 struct xe_gt *gt = guc_to_gt(guc); 1374 struct xe_mmio *mmio = >->mmio; 1375 u32 header, reply; 1376 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1377 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1378 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1379 bool lost = false; 1380 int ret; 1381 int i; 1382 1383 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1384 1385 xe_assert(xe, len); 1386 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1387 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1388 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1389 GUC_HXG_ORIGIN_HOST); 1390 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1391 GUC_HXG_TYPE_REQUEST); 1392 1393 retry: 1394 /* Not in critical data-path, just do if else for GT type */ 1395 if (xe_gt_is_media_type(gt)) { 1396 for (i = 0; i < len; ++i) 1397 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1398 request[i]); 1399 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1400 } else { 1401 for (i = 0; i < len; ++i) 1402 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1403 request[i]); 1404 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1405 } 1406 1407 xe_guc_notify(guc); 1408 1409 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1410 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1411 50000, &reply, false); 1412 if (ret) { 1413 /* scratch registers might be cleared during FLR, try once more */ 1414 if (!reply && !lost) { 1415 xe_gt_dbg(gt, "GuC mmio request %#x: lost, trying again\n", request[0]); 1416 lost = true; 1417 goto retry; 1418 } 1419 timeout: 1420 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1421 request[0], reply); 1422 return ret; 1423 } 1424 1425 header = xe_mmio_read32(mmio, reply_reg); 1426 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1427 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1428 /* 1429 * Once we got a BUSY reply we must wait again for the final 1430 * response but this time we can't use ORIGIN mask anymore. 1431 * To spot a right change in the reply, we take advantage that 1432 * response SUCCESS and FAILURE differ only by the single bit 1433 * and all other bits are set and can be used as a new mask. 1434 */ 1435 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1436 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1437 1438 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1439 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1440 1441 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1442 2000000, &header, false); 1443 1444 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1445 GUC_HXG_ORIGIN_GUC)) 1446 goto proto; 1447 if (unlikely(ret)) { 1448 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1449 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1450 goto proto; 1451 goto timeout; 1452 } 1453 } 1454 1455 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1456 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1457 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1458 1459 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1460 request[0], reason); 1461 goto retry; 1462 } 1463 1464 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1465 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1466 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1467 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1468 1469 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1470 request[0], error, hint); 1471 return -ENXIO; 1472 } 1473 1474 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1475 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1476 proto: 1477 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1478 request[0], header); 1479 return -EPROTO; 1480 } 1481 1482 /* Just copy entire possible message response */ 1483 if (response_buf) { 1484 response_buf[0] = header; 1485 1486 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1487 reply_reg.addr += sizeof(u32); 1488 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1489 } 1490 } 1491 1492 /* Use data from the GuC response as our return value */ 1493 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1494 } 1495 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1496 1497 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1498 { 1499 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1500 } 1501 1502 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1503 { 1504 struct xe_device *xe = guc_to_xe(guc); 1505 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1506 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1507 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1508 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1509 GUC_ACTION_HOST2GUC_SELF_CFG), 1510 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1511 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1512 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1513 lower_32_bits(val)), 1514 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1515 upper_32_bits(val)), 1516 }; 1517 int ret; 1518 1519 xe_assert(xe, len <= 2); 1520 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1521 1522 /* Self config must go over MMIO */ 1523 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1524 1525 if (unlikely(ret < 0)) 1526 return ret; 1527 if (unlikely(ret > 1)) 1528 return -EPROTO; 1529 if (unlikely(!ret)) 1530 return -ENOKEY; 1531 1532 return 0; 1533 } 1534 1535 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1536 { 1537 return guc_self_cfg(guc, key, 1, val); 1538 } 1539 1540 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1541 { 1542 return guc_self_cfg(guc, key, 2, val); 1543 } 1544 1545 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1546 { 1547 struct xe_gt *gt = guc_to_gt(guc); 1548 1549 if (IS_SRIOV_VF(gt_to_xe(gt))) 1550 xe_gt_sriov_vf_migrated_event_handler(gt); 1551 } 1552 1553 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1554 { 1555 if (iir & GUC_INTR_GUC2HOST) 1556 xe_guc_ct_irq_handler(&guc->ct); 1557 1558 if (iir & GUC_INTR_SW_INT_0) 1559 xe_guc_sw_0_irq_handler(guc); 1560 } 1561 1562 void xe_guc_sanitize(struct xe_guc *guc) 1563 { 1564 xe_uc_fw_sanitize(&guc->fw); 1565 xe_guc_ct_disable(&guc->ct); 1566 xe_guc_submit_disable(guc); 1567 } 1568 1569 int xe_guc_reset_prepare(struct xe_guc *guc) 1570 { 1571 return xe_guc_submit_reset_prepare(guc); 1572 } 1573 1574 void xe_guc_reset_wait(struct xe_guc *guc) 1575 { 1576 xe_guc_submit_reset_wait(guc); 1577 } 1578 1579 void xe_guc_stop_prepare(struct xe_guc *guc) 1580 { 1581 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1582 int err; 1583 1584 err = xe_guc_pc_stop(&guc->pc); 1585 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1586 ERR_PTR(err)); 1587 } 1588 } 1589 1590 void xe_guc_stop(struct xe_guc *guc) 1591 { 1592 xe_guc_ct_stop(&guc->ct); 1593 1594 xe_guc_submit_stop(guc); 1595 } 1596 1597 int xe_guc_start(struct xe_guc *guc) 1598 { 1599 return xe_guc_submit_start(guc); 1600 } 1601 1602 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1603 { 1604 struct xe_gt *gt = guc_to_gt(guc); 1605 unsigned int fw_ref; 1606 u32 status; 1607 int i; 1608 1609 xe_uc_fw_print(&guc->fw, p); 1610 1611 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1612 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1613 if (!fw_ref) 1614 return; 1615 1616 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1617 1618 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1619 drm_printf(p, "\tBootrom status = 0x%x\n", 1620 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1621 drm_printf(p, "\tuKernel status = 0x%x\n", 1622 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1623 drm_printf(p, "\tMIA Core status = 0x%x\n", 1624 REG_FIELD_GET(GS_MIA_MASK, status)); 1625 drm_printf(p, "\tLog level = %d\n", 1626 xe_guc_log_get_level(&guc->log)); 1627 1628 drm_puts(p, "\nScratch registers:\n"); 1629 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1630 drm_printf(p, "\t%2d: \t0x%x\n", 1631 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1632 } 1633 1634 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1635 } 1636 1637 drm_puts(p, "\n"); 1638 xe_guc_ct_print(&guc->ct, p, false); 1639 1640 drm_puts(p, "\n"); 1641 xe_guc_submit_print(guc, p); 1642 } 1643 1644 /** 1645 * xe_guc_declare_wedged() - Declare GuC wedged 1646 * @guc: the GuC object 1647 * 1648 * Wedge the GuC which stops all submission, saves desired debug state, and 1649 * cleans up anything which could timeout. 1650 */ 1651 void xe_guc_declare_wedged(struct xe_guc *guc) 1652 { 1653 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1654 1655 xe_guc_reset_prepare(guc); 1656 xe_guc_ct_stop(&guc->ct); 1657 xe_guc_submit_wedge(guc); 1658 } 1659 1660 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1661 #include "tests/xe_guc_g2g_test.c" 1662 #endif 1663