1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "abi/guc_actions_abi.h" 13 #include "abi/guc_errors_abi.h" 14 #include "regs/xe_gt_regs.h" 15 #include "regs/xe_gtt_defs.h" 16 #include "regs/xe_guc_regs.h" 17 #include "regs/xe_irq_regs.h" 18 #include "xe_bo.h" 19 #include "xe_device.h" 20 #include "xe_force_wake.h" 21 #include "xe_gt.h" 22 #include "xe_gt_printk.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_gt_throttle.h" 25 #include "xe_guc_ads.h" 26 #include "xe_guc_buf.h" 27 #include "xe_guc_capture.h" 28 #include "xe_guc_ct.h" 29 #include "xe_guc_db_mgr.h" 30 #include "xe_guc_engine_activity.h" 31 #include "xe_guc_hwconfig.h" 32 #include "xe_guc_log.h" 33 #include "xe_guc_pc.h" 34 #include "xe_guc_relay.h" 35 #include "xe_guc_submit.h" 36 #include "xe_memirq.h" 37 #include "xe_mmio.h" 38 #include "xe_platform_types.h" 39 #include "xe_sriov.h" 40 #include "xe_uc.h" 41 #include "xe_uc_fw.h" 42 #include "xe_wa.h" 43 #include "xe_wopcm.h" 44 45 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 46 struct xe_bo *bo) 47 { 48 struct xe_device *xe = guc_to_xe(guc); 49 u32 addr; 50 51 /* 52 * For most BOs, the address on the allocating tile is fine. However for 53 * some, e.g. G2G CTB, the address on a specific tile is required as it 54 * might be different for each tile. So, just always ask for the address 55 * on the target GuC. 56 */ 57 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 58 59 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 60 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 61 xe_assert(xe, addr < GUC_GGTT_TOP); 62 xe_assert(xe, bo->size <= GUC_GGTT_TOP - addr); 63 64 return addr; 65 } 66 67 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 68 { 69 u32 level = xe_guc_log_get_level(&guc->log); 70 u32 flags = 0; 71 72 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 73 flags |= GUC_LOG_DISABLED; 74 else 75 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 76 GUC_LOG_VERBOSITY_SHIFT; 77 78 return flags; 79 } 80 81 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 82 { 83 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 84 85 if (!guc_to_xe(guc)->info.skip_guc_pc) 86 flags |= GUC_CTL_ENABLE_SLPC; 87 88 return flags; 89 } 90 91 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 92 { 93 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 94 u32 flags; 95 96 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 97 #define LOG_UNIT SZ_1M 98 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 99 #else 100 #define LOG_UNIT SZ_4K 101 #define LOG_FLAG 0 102 #endif 103 104 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 105 #define CAPTURE_UNIT SZ_1M 106 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 107 #else 108 #define CAPTURE_UNIT SZ_4K 109 #define CAPTURE_FLAG 0 110 #endif 111 112 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 113 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 114 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 115 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 116 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 117 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 118 119 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 120 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 121 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 122 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 123 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 124 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 125 126 flags = GUC_LOG_VALID | 127 GUC_LOG_NOTIFY_ON_HALF_FULL | 128 CAPTURE_FLAG | 129 LOG_FLAG | 130 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 131 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 132 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << 133 GUC_LOG_CAPTURE_SHIFT) | 134 (offset << GUC_LOG_BUF_ADDR_SHIFT); 135 136 #undef LOG_UNIT 137 #undef LOG_FLAG 138 #undef CAPTURE_UNIT 139 #undef CAPTURE_FLAG 140 141 return flags; 142 } 143 144 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 145 { 146 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 147 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 148 149 return flags; 150 } 151 152 static bool needs_wa_dual_queue(struct xe_gt *gt) 153 { 154 /* 155 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 156 * on RCS and CCSes with different address spaces, which on DG2 is 157 * required as a WA for an HW bug. 158 */ 159 if (XE_WA(gt, 22011391025)) 160 return true; 161 162 /* 163 * On newer platforms, the HW has been updated to not allow parallel 164 * execution of different address spaces, so the RCS/CCS will stall the 165 * context switch if one of the other RCS/CCSes is busy with a different 166 * address space. While functionally correct, having a submission 167 * stalled on the HW limits the GuC ability to shuffle things around and 168 * can cause complications if the non-stalled submission runs for a long 169 * time, because the GuC doesn't know that the stalled submission isn't 170 * actually running and might declare it as hung. Therefore, we enable 171 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 172 * to move management back to the GuC. 173 */ 174 if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 175 return true; 176 177 return false; 178 } 179 180 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 181 { 182 struct xe_device *xe = guc_to_xe(guc); 183 struct xe_gt *gt = guc_to_gt(guc); 184 u32 flags = 0; 185 186 if (XE_WA(gt, 22012773006)) 187 flags |= GUC_WA_POLLCS; 188 189 if (XE_WA(gt, 14014475959)) 190 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 191 192 if (needs_wa_dual_queue(gt)) 193 flags |= GUC_WA_DUAL_QUEUE; 194 195 /* 196 * Wa_22011802037: FIXME - there's more to be done than simply setting 197 * this flag: make sure each CS is stopped when preparing for GT reset 198 * and wait for pending MI_FW. 199 */ 200 if (GRAPHICS_VERx100(xe) < 1270) 201 flags |= GUC_WA_PRE_PARSER; 202 203 if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685)) 204 flags |= GUC_WA_CONTEXT_ISOLATION; 205 206 if (XE_WA(gt, 18020744125) && 207 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 208 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 209 210 if (XE_WA(gt, 1509372804)) 211 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 212 213 if (XE_WA(gt, 14018913170)) 214 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 215 216 return flags; 217 } 218 219 static u32 guc_ctl_devid(struct xe_guc *guc) 220 { 221 struct xe_device *xe = guc_to_xe(guc); 222 223 return (((u32)xe->info.devid) << 16) | xe->info.revid; 224 } 225 226 static void guc_print_params(struct xe_guc *guc) 227 { 228 struct xe_gt *gt = guc_to_gt(guc); 229 u32 *params = guc->params; 230 int i; 231 232 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 233 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 234 235 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 236 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 237 } 238 239 static void guc_init_params(struct xe_guc *guc) 240 { 241 u32 *params = guc->params; 242 243 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 244 params[GUC_CTL_FEATURE] = 0; 245 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 246 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 247 params[GUC_CTL_WA] = 0; 248 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 249 250 guc_print_params(guc); 251 } 252 253 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 254 { 255 u32 *params = guc->params; 256 257 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 258 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 259 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 260 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 261 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 262 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 263 264 guc_print_params(guc); 265 } 266 267 /* 268 * Initialize the GuC parameter block before starting the firmware 269 * transfer. These parameters are read by the firmware on startup 270 * and cannot be changed thereafter. 271 */ 272 static void guc_write_params(struct xe_guc *guc) 273 { 274 struct xe_gt *gt = guc_to_gt(guc); 275 int i; 276 277 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 278 279 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 280 281 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 282 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 283 } 284 285 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 286 u32 desc_addr, u32 buff_addr, u32 size) 287 { 288 struct xe_gt *gt = guc_to_gt(guc); 289 struct xe_device *xe = gt_to_xe(gt); 290 u32 action[] = { 291 XE_GUC_ACTION_REGISTER_G2G, 292 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 293 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 294 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 295 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 296 desc_addr, 297 buff_addr, 298 }; 299 300 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 301 xe_assert(xe, !(size % SZ_4K)); 302 303 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 304 } 305 306 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 307 { 308 struct xe_gt *gt = guc_to_gt(guc); 309 struct xe_device *xe = gt_to_xe(gt); 310 u32 action[] = { 311 XE_GUC_ACTION_DEREGISTER_G2G, 312 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 313 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 314 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 315 }; 316 317 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 318 319 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 320 } 321 322 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 323 324 #define G2G_BUFFER_SIZE (SZ_4K) 325 #define G2G_DESC_SIZE (64) 326 #define G2G_DESC_AREA_SIZE (SZ_4K) 327 328 /* 329 * Generate a unique id for each bi-directional CTB for each pair of 330 * near and far tiles/devices. The id can then be used as an index into 331 * a single allocation that is sub-divided into multiple CTBs. 332 * 333 * For example, with two devices per tile and two tiles, the table should 334 * look like: 335 * Far <tile>.<dev> 336 * 0.0 0.1 1.0 1.1 337 * N 0.0 --/-- 00/01 02/03 04/05 338 * e 0.1 01/00 --/-- 06/07 08/09 339 * a 1.0 03/02 07/06 --/-- 10/11 340 * r 1.1 05/04 09/08 11/10 --/-- 341 * 342 * Where each entry is Rx/Tx channel id. 343 * 344 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 345 * be reading from channel #11 and writing to channel #10. Whereas, 346 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 347 */ 348 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 349 u32 type, u32 max_inst, bool have_dev) 350 { 351 u32 near = near_tile, far = far_tile; 352 u32 idx = 0, x, y, direction; 353 int i; 354 355 if (have_dev) { 356 near = (near << 1) | near_dev; 357 far = (far << 1) | far_dev; 358 } 359 360 /* No need to send to one's self */ 361 if (far == near) 362 return -1; 363 364 if (far > near) { 365 /* Top right table half */ 366 x = far; 367 y = near; 368 369 /* T/R is 'forwards' direction */ 370 direction = type; 371 } else { 372 /* Bottom left table half */ 373 x = near; 374 y = far; 375 376 /* B/L is 'backwards' direction */ 377 direction = (1 - type); 378 } 379 380 /* Count the rows prior to the target */ 381 for (i = y; i > 0; i--) 382 idx += max_inst - i; 383 384 /* Count this row up to the target */ 385 idx += (x - 1 - y); 386 387 /* Slots are in Rx/Tx pairs */ 388 idx *= 2; 389 390 /* Pick Rx/Tx direction */ 391 idx += direction; 392 393 return idx; 394 } 395 396 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 397 { 398 struct xe_gt *near_gt = guc_to_gt(near_guc); 399 struct xe_device *xe = gt_to_xe(near_gt); 400 struct xe_bo *g2g_bo; 401 u32 near_tile = gt_to_tile(near_gt)->id; 402 u32 near_dev = G2G_DEV(near_gt); 403 u32 far_tile = gt_to_tile(far_gt)->id; 404 u32 far_dev = G2G_DEV(far_gt); 405 u32 max = xe->info.gt_count; 406 u32 base, desc, buf; 407 int slot; 408 409 /* G2G is not allowed between different cards */ 410 xe_assert(xe, xe == gt_to_xe(far_gt)); 411 412 g2g_bo = near_guc->g2g.bo; 413 xe_assert(xe, g2g_bo); 414 415 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 416 xe_assert(xe, slot >= 0); 417 418 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 419 desc = base + slot * G2G_DESC_SIZE; 420 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 421 422 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 423 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= g2g_bo->size); 424 425 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 426 desc, buf, G2G_BUFFER_SIZE); 427 } 428 429 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 430 { 431 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 432 } 433 434 static u32 guc_g2g_size(struct xe_guc *guc) 435 { 436 struct xe_gt *gt = guc_to_gt(guc); 437 struct xe_device *xe = gt_to_xe(gt); 438 unsigned int count = xe->info.gt_count; 439 u32 num_channels = (count * (count - 1)) / 2; 440 441 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 442 443 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 444 } 445 446 static bool xe_guc_g2g_wanted(struct xe_device *xe) 447 { 448 /* Can't do GuC to GuC communication if there is only one GuC */ 449 if (xe->info.gt_count <= 1) 450 return false; 451 452 /* No current user */ 453 return false; 454 } 455 456 static int guc_g2g_alloc(struct xe_guc *guc) 457 { 458 struct xe_gt *gt = guc_to_gt(guc); 459 struct xe_device *xe = gt_to_xe(gt); 460 struct xe_tile *tile = gt_to_tile(gt); 461 struct xe_bo *bo; 462 u32 g2g_size; 463 464 if (guc->g2g.bo) 465 return 0; 466 467 if (gt->info.id != 0) { 468 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 469 struct xe_guc *root_guc = &root_gt->uc.guc; 470 struct xe_bo *bo; 471 472 bo = xe_bo_get(root_guc->g2g.bo); 473 if (!bo) 474 return -ENODEV; 475 476 guc->g2g.bo = bo; 477 guc->g2g.owned = false; 478 return 0; 479 } 480 481 g2g_size = guc_g2g_size(guc); 482 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 483 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 484 XE_BO_FLAG_GGTT | 485 XE_BO_FLAG_GGTT_ALL | 486 XE_BO_FLAG_GGTT_INVALIDATE | 487 XE_BO_FLAG_PINNED_NORESTORE); 488 if (IS_ERR(bo)) 489 return PTR_ERR(bo); 490 491 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 492 guc->g2g.bo = bo; 493 guc->g2g.owned = true; 494 495 return 0; 496 } 497 498 static void guc_g2g_fini(struct xe_guc *guc) 499 { 500 if (!guc->g2g.bo) 501 return; 502 503 /* Unpinning the owned object is handled by generic shutdown */ 504 if (!guc->g2g.owned) 505 xe_bo_put(guc->g2g.bo); 506 507 guc->g2g.bo = NULL; 508 } 509 510 static int guc_g2g_start(struct xe_guc *guc) 511 { 512 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 513 struct xe_device *xe = gt_to_xe(gt); 514 unsigned int i, j; 515 int t, err; 516 bool have_dev; 517 518 if (!guc->g2g.bo) { 519 int ret; 520 521 ret = guc_g2g_alloc(guc); 522 if (ret) 523 return ret; 524 } 525 526 /* GuC interface will need extending if more GT device types are ever created. */ 527 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 528 529 /* Channel numbering depends on whether there are multiple GTs per tile */ 530 have_dev = xe->info.gt_count > xe->info.tile_count; 531 532 for_each_gt(far_gt, xe, i) { 533 u32 far_tile, far_dev; 534 535 if (far_gt->info.id == gt->info.id) 536 continue; 537 538 far_tile = gt_to_tile(far_gt)->id; 539 far_dev = G2G_DEV(far_gt); 540 541 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 542 err = guc_g2g_register(guc, far_gt, t, have_dev); 543 if (err) { 544 while (--t >= 0) 545 guc_g2g_deregister(guc, far_tile, far_dev, t); 546 goto err_deregister; 547 } 548 } 549 } 550 551 return 0; 552 553 err_deregister: 554 for_each_gt(far_gt, xe, j) { 555 u32 tile, dev; 556 557 if (far_gt->info.id == gt->info.id) 558 continue; 559 560 if (j >= i) 561 break; 562 563 tile = gt_to_tile(far_gt)->id; 564 dev = G2G_DEV(far_gt); 565 566 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 567 guc_g2g_deregister(guc, tile, dev, t); 568 } 569 570 return err; 571 } 572 573 static void guc_fini_hw(void *arg) 574 { 575 struct xe_guc *guc = arg; 576 struct xe_gt *gt = guc_to_gt(guc); 577 unsigned int fw_ref; 578 579 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 580 xe_uc_fini_hw(&guc_to_gt(guc)->uc); 581 xe_force_wake_put(gt_to_fw(gt), fw_ref); 582 583 guc_g2g_fini(guc); 584 } 585 586 /** 587 * xe_guc_comm_init_early - early initialization of GuC communication 588 * @guc: the &xe_guc to initialize 589 * 590 * Must be called prior to first MMIO communication with GuC firmware. 591 */ 592 void xe_guc_comm_init_early(struct xe_guc *guc) 593 { 594 struct xe_gt *gt = guc_to_gt(guc); 595 596 if (xe_gt_is_media_type(gt)) 597 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 598 else 599 guc->notify_reg = GUC_HOST_INTERRUPT; 600 } 601 602 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 603 { 604 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 605 struct xe_device *xe = guc_to_xe(guc); 606 int ret; 607 608 if (!IS_DGFX(guc_to_xe(guc))) 609 return 0; 610 611 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 612 if (ret) 613 return ret; 614 615 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 616 if (ret) 617 return ret; 618 619 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 620 if (ret) 621 return ret; 622 623 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo); 624 if (ret) 625 return ret; 626 627 return 0; 628 } 629 630 static int vf_guc_init(struct xe_guc *guc) 631 { 632 int err; 633 634 xe_guc_comm_init_early(guc); 635 636 err = xe_guc_ct_init(&guc->ct); 637 if (err) 638 return err; 639 640 err = xe_guc_relay_init(&guc->relay); 641 if (err) 642 return err; 643 644 return 0; 645 } 646 647 int xe_guc_init(struct xe_guc *guc) 648 { 649 struct xe_device *xe = guc_to_xe(guc); 650 struct xe_gt *gt = guc_to_gt(guc); 651 int ret; 652 653 guc->fw.type = XE_UC_FW_TYPE_GUC; 654 ret = xe_uc_fw_init(&guc->fw); 655 if (ret) 656 goto out; 657 658 if (!xe_uc_fw_is_enabled(&guc->fw)) 659 return 0; 660 661 if (IS_SRIOV_VF(xe)) { 662 ret = vf_guc_init(guc); 663 if (ret) 664 goto out; 665 return 0; 666 } 667 668 ret = xe_guc_log_init(&guc->log); 669 if (ret) 670 goto out; 671 672 ret = xe_guc_capture_init(guc); 673 if (ret) 674 goto out; 675 676 ret = xe_guc_ads_init(&guc->ads); 677 if (ret) 678 goto out; 679 680 ret = xe_guc_ct_init(&guc->ct); 681 if (ret) 682 goto out; 683 684 ret = xe_guc_relay_init(&guc->relay); 685 if (ret) 686 goto out; 687 688 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 689 690 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 691 if (ret) 692 goto out; 693 694 guc_init_params(guc); 695 696 xe_guc_comm_init_early(guc); 697 698 return 0; 699 700 out: 701 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 702 return ret; 703 } 704 705 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 706 { 707 int err; 708 709 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 710 if (err) 711 return err; 712 713 /* XXX xe_guc_db_mgr_init not needed for now */ 714 715 return 0; 716 } 717 718 /** 719 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 720 * @guc: The GuC object 721 * 722 * Return: 0 on success, negative error code on error. 723 */ 724 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 725 { 726 int ret; 727 728 if (IS_SRIOV_VF(guc_to_xe(guc))) 729 return vf_guc_init_post_hwconfig(guc); 730 731 ret = xe_guc_realloc_post_hwconfig(guc); 732 if (ret) 733 return ret; 734 735 guc_init_params_post_hwconfig(guc); 736 737 ret = xe_guc_submit_init(guc, ~0); 738 if (ret) 739 return ret; 740 741 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 742 if (ret) 743 return ret; 744 745 ret = xe_guc_pc_init(&guc->pc); 746 if (ret) 747 return ret; 748 749 ret = xe_guc_engine_activity_init(guc); 750 if (ret) 751 return ret; 752 753 ret = xe_guc_buf_cache_init(&guc->buf); 754 if (ret) 755 return ret; 756 757 return xe_guc_ads_init_post_hwconfig(&guc->ads); 758 } 759 760 int xe_guc_post_load_init(struct xe_guc *guc) 761 { 762 int ret; 763 764 xe_guc_ads_populate_post_load(&guc->ads); 765 766 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 767 ret = guc_g2g_start(guc); 768 if (ret) 769 return ret; 770 } 771 772 guc->submission_state.enabled = true; 773 774 return 0; 775 } 776 777 int xe_guc_reset(struct xe_guc *guc) 778 { 779 struct xe_gt *gt = guc_to_gt(guc); 780 struct xe_mmio *mmio = >->mmio; 781 u32 guc_status, gdrst; 782 int ret; 783 784 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 785 786 if (IS_SRIOV_VF(gt_to_xe(gt))) 787 return xe_gt_sriov_vf_bootstrap(gt); 788 789 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 790 791 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 792 if (ret) { 793 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 794 goto err_out; 795 } 796 797 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 798 if (!(guc_status & GS_MIA_IN_RESET)) { 799 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 800 guc_status); 801 ret = -EIO; 802 goto err_out; 803 } 804 805 return 0; 806 807 err_out: 808 809 return ret; 810 } 811 812 static void guc_prepare_xfer(struct xe_guc *guc) 813 { 814 struct xe_gt *gt = guc_to_gt(guc); 815 struct xe_mmio *mmio = >->mmio; 816 struct xe_device *xe = guc_to_xe(guc); 817 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 818 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 819 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 820 GUC_ENABLE_MIA_CLOCK_GATING; 821 822 if (GRAPHICS_VERx100(xe) < 1250) 823 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 824 GUC_ENABLE_MIA_CACHING; 825 826 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 827 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 828 829 /* Must program this register before loading the ucode with DMA */ 830 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 831 832 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 833 834 /* Make sure GuC receives ARAT interrupts */ 835 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 836 } 837 838 /* 839 * Supporting MMIO & in memory RSA 840 */ 841 static int guc_xfer_rsa(struct xe_guc *guc) 842 { 843 struct xe_gt *gt = guc_to_gt(guc); 844 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 845 size_t copied; 846 int i; 847 848 if (guc->fw.rsa_size > 256) { 849 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 850 xe_uc_fw_rsa_offset(&guc->fw); 851 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 852 return 0; 853 } 854 855 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 856 if (copied < sizeof(rsa)) 857 return -ENOMEM; 858 859 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 860 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 861 862 return 0; 863 } 864 865 /* 866 * Check a previously read GuC status register (GUC_STATUS) looking for 867 * known terminal states (either completion or failure) of either the 868 * microkernel status field or the boot ROM status field. Returns +1 for 869 * successful completion, -1 for failure and 0 for any intermediate state. 870 */ 871 static int guc_load_done(u32 status) 872 { 873 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); 874 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); 875 876 switch (uk_val) { 877 case XE_GUC_LOAD_STATUS_READY: 878 return 1; 879 880 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 881 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 882 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 883 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 884 case XE_GUC_LOAD_STATUS_DPC_ERROR: 885 case XE_GUC_LOAD_STATUS_EXCEPTION: 886 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 887 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 888 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 889 return -1; 890 } 891 892 switch (br_val) { 893 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 894 case XE_BOOTROM_STATUS_RSA_FAILED: 895 case XE_BOOTROM_STATUS_PAVPC_FAILED: 896 case XE_BOOTROM_STATUS_WOPCM_FAILED: 897 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 898 case XE_BOOTROM_STATUS_JUMP_FAILED: 899 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 900 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 901 case XE_BOOTROM_STATUS_EXCEPTION: 902 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 903 return -1; 904 } 905 906 return 0; 907 } 908 909 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) 910 { 911 u32 freq; 912 int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq); 913 914 return ret ? ret : freq; 915 } 916 917 /* 918 * Wait for the GuC to start up. 919 * 920 * Measurements indicate this should take no more than 20ms (assuming the GT 921 * clock is at maximum frequency). However, thermal throttling and other issues 922 * can prevent the clock hitting max and thus making the load take significantly 923 * longer. Allow up to 200ms as a safety margin for real world worst case situations. 924 * 925 * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can 926 * lead to even longer times. E.g. if the GT is clamped to minimum frequency then 927 * the load times can be in the seconds range. So the timeout is increased for debug 928 * builds to ensure that problems can be correctly analysed. For release builds, the 929 * timeout is kept short so that users don't wait forever to find out that there is a 930 * problem. In either case, if the load took longer than is reasonable even with some 931 * 'sensible' throttling, then flag a warning because something is not right. 932 * 933 * Note that there is a limit on how long an individual usleep_range() can wait for, 934 * hence longer waits require wrapping a shorter wait in a loop. 935 * 936 * Note that the only reason an end user should hit the shorter timeout is in case of 937 * extreme thermal throttling. And a system that is that hot during boot is probably 938 * dead anyway! 939 */ 940 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 941 #define GUC_LOAD_RETRY_LIMIT 20 942 #else 943 #define GUC_LOAD_RETRY_LIMIT 3 944 #endif 945 #define GUC_LOAD_TIME_WARN_MS 200 946 947 static void guc_wait_ucode(struct xe_guc *guc) 948 { 949 struct xe_gt *gt = guc_to_gt(guc); 950 struct xe_mmio *mmio = >->mmio; 951 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 952 ktime_t before, after, delta; 953 int load_done; 954 u32 status = 0; 955 int count = 0; 956 u64 delta_ms; 957 u32 before_freq; 958 959 before_freq = xe_guc_pc_get_act_freq(guc_pc); 960 before = ktime_get(); 961 /* 962 * Note, can't use any kind of timing information from the call to xe_mmio_wait. 963 * It could return a thousand intermediate stages at random times. Instead, must 964 * manually track the total time taken and locally implement the timeout. 965 */ 966 do { 967 u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK); 968 int ret; 969 970 /* 971 * Wait for any change (intermediate or terminal) in the status register. 972 * Note, the return value is a don't care. The only failure code is timeout 973 * but the timeouts need to be accumulated over all the intermediate partial 974 * timeouts rather than allowing a huge timeout each time. So basically, need 975 * to treat a timeout no different to a value change. 976 */ 977 ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK, 978 last_status, 1000 * 1000, &status, false); 979 if (ret < 0) 980 count++; 981 after = ktime_get(); 982 delta = ktime_sub(after, before); 983 delta_ms = ktime_to_ms(delta); 984 985 load_done = guc_load_done(status); 986 if (load_done != 0) 987 break; 988 989 if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000)) 990 break; 991 992 xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 993 count, xe_guc_pc_get_act_freq(guc_pc), 994 guc_pc_get_cur_freq(guc_pc), status, 995 REG_FIELD_GET(GS_BOOTROM_MASK, status), 996 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 997 } while (1); 998 999 if (load_done != 1) { 1000 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1001 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1002 1003 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n", 1004 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1005 guc_pc_get_cur_freq(guc_pc), load_done); 1006 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1007 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1008 bootrom, ukernel, 1009 REG_FIELD_GET(GS_MIA_MASK, status), 1010 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1011 1012 switch (bootrom) { 1013 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1014 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1015 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1016 break; 1017 1018 case XE_BOOTROM_STATUS_RSA_FAILED: 1019 xe_gt_err(gt, "firmware signature verification failed\n"); 1020 break; 1021 1022 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1023 xe_gt_err(gt, "firmware production part check failure\n"); 1024 break; 1025 } 1026 1027 switch (ukernel) { 1028 case XE_GUC_LOAD_STATUS_EXCEPTION: 1029 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1030 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1031 break; 1032 1033 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1034 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1035 break; 1036 1037 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1038 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1039 break; 1040 } 1041 1042 xe_device_declare_wedged(gt_to_xe(gt)); 1043 } else if (delta_ms > GUC_LOAD_TIME_WARN_MS) { 1044 xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n", 1045 delta_ms, status, count); 1046 xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1047 xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1048 before_freq, xe_gt_throttle_get_limit_reasons(gt)); 1049 } else { 1050 xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n", 1051 delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1052 before_freq, status, count); 1053 } 1054 } 1055 1056 static int __xe_guc_upload(struct xe_guc *guc) 1057 { 1058 int ret; 1059 1060 /* Raise GT freq to speed up HuC/GuC load */ 1061 xe_guc_pc_raise_unslice(&guc->pc); 1062 1063 guc_write_params(guc); 1064 guc_prepare_xfer(guc); 1065 1066 /* 1067 * Note that GuC needs the CSS header plus uKernel code to be copied 1068 * by the DMA engine in one operation, whereas the RSA signature is 1069 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1070 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1071 * size > 256). The RSA size and therefore the way we provide it to the 1072 * HW is fixed for each platform and hard-coded in the bootrom. 1073 */ 1074 ret = guc_xfer_rsa(guc); 1075 if (ret) 1076 goto out; 1077 /* 1078 * Current uCode expects the code to be loaded at 8k; locations below 1079 * this are used for the stack. 1080 */ 1081 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1082 if (ret) 1083 goto out; 1084 1085 /* Wait for authentication */ 1086 guc_wait_ucode(guc); 1087 1088 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1089 return 0; 1090 1091 out: 1092 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1093 return 0 /* FIXME: ret, don't want to stop load currently */; 1094 } 1095 1096 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1097 { 1098 struct xe_gt *gt = guc_to_gt(guc); 1099 int ret; 1100 1101 ret = xe_gt_sriov_vf_bootstrap(gt); 1102 if (ret) 1103 return ret; 1104 1105 ret = xe_gt_sriov_vf_query_config(gt); 1106 if (ret) 1107 return ret; 1108 1109 ret = xe_guc_hwconfig_init(guc); 1110 if (ret) 1111 return ret; 1112 1113 ret = xe_guc_enable_communication(guc); 1114 if (ret) 1115 return ret; 1116 1117 ret = xe_gt_sriov_vf_connect(gt); 1118 if (ret) 1119 return ret; 1120 1121 ret = xe_gt_sriov_vf_query_runtime(gt); 1122 if (ret) 1123 return ret; 1124 1125 return 0; 1126 } 1127 1128 /** 1129 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1130 * @guc: The GuC object 1131 * 1132 * This function uploads a minimal GuC that does not support submissions but 1133 * in a state where the hwconfig table can be read. Next, it reads and parses 1134 * the hwconfig table so it can be used for subsequent steps in the driver load. 1135 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1136 * 1137 * Return: 0 on success, negative error code on error. 1138 */ 1139 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1140 { 1141 int ret; 1142 1143 if (IS_SRIOV_VF(guc_to_xe(guc))) 1144 return vf_guc_min_load_for_hwconfig(guc); 1145 1146 xe_guc_ads_populate_minimal(&guc->ads); 1147 1148 xe_guc_pc_init_early(&guc->pc); 1149 1150 ret = __xe_guc_upload(guc); 1151 if (ret) 1152 return ret; 1153 1154 ret = xe_guc_hwconfig_init(guc); 1155 if (ret) 1156 return ret; 1157 1158 ret = xe_guc_enable_communication(guc); 1159 if (ret) 1160 return ret; 1161 1162 return 0; 1163 } 1164 1165 int xe_guc_upload(struct xe_guc *guc) 1166 { 1167 xe_guc_ads_populate(&guc->ads); 1168 1169 return __xe_guc_upload(guc); 1170 } 1171 1172 static void guc_handle_mmio_msg(struct xe_guc *guc) 1173 { 1174 struct xe_gt *gt = guc_to_gt(guc); 1175 u32 msg; 1176 1177 if (IS_SRIOV_VF(guc_to_xe(guc))) 1178 return; 1179 1180 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1181 1182 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1183 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1184 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1185 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1186 1187 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1188 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1189 1190 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1191 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1192 } 1193 1194 static void guc_enable_irq(struct xe_guc *guc) 1195 { 1196 struct xe_gt *gt = guc_to_gt(guc); 1197 u32 events = xe_gt_is_media_type(gt) ? 1198 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1199 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1200 1201 /* Primary GuC and media GuC share a single enable bit */ 1202 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1203 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1204 1205 /* 1206 * There are separate mask bits for primary and media GuCs, so use 1207 * a RMW operation to avoid clobbering the other GuC's setting. 1208 */ 1209 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1210 } 1211 1212 int xe_guc_enable_communication(struct xe_guc *guc) 1213 { 1214 struct xe_device *xe = guc_to_xe(guc); 1215 int err; 1216 1217 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1218 struct xe_gt *gt = guc_to_gt(guc); 1219 struct xe_tile *tile = gt_to_tile(gt); 1220 1221 err = xe_memirq_init_guc(&tile->memirq, guc); 1222 if (err) 1223 return err; 1224 } else { 1225 guc_enable_irq(guc); 1226 } 1227 1228 err = xe_guc_ct_enable(&guc->ct); 1229 if (err) 1230 return err; 1231 1232 guc_handle_mmio_msg(guc); 1233 1234 return 0; 1235 } 1236 1237 int xe_guc_suspend(struct xe_guc *guc) 1238 { 1239 struct xe_gt *gt = guc_to_gt(guc); 1240 u32 action[] = { 1241 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1242 }; 1243 int ret; 1244 1245 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1246 if (ret) { 1247 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1248 return ret; 1249 } 1250 1251 xe_guc_sanitize(guc); 1252 return 0; 1253 } 1254 1255 void xe_guc_notify(struct xe_guc *guc) 1256 { 1257 struct xe_gt *gt = guc_to_gt(guc); 1258 const u32 default_notify_data = 0; 1259 1260 /* 1261 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1262 * additional payload data to the GuC but this capability is not 1263 * used by the firmware yet. Use default value in the meantime. 1264 */ 1265 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1266 } 1267 1268 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1269 { 1270 u32 action[] = { 1271 XE_GUC_ACTION_AUTHENTICATE_HUC, 1272 rsa_addr 1273 }; 1274 1275 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1276 } 1277 1278 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1279 u32 len, u32 *response_buf) 1280 { 1281 struct xe_device *xe = guc_to_xe(guc); 1282 struct xe_gt *gt = guc_to_gt(guc); 1283 struct xe_mmio *mmio = >->mmio; 1284 u32 header, reply; 1285 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1286 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1287 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1288 int ret; 1289 int i; 1290 1291 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1292 1293 xe_assert(xe, len); 1294 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1295 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1296 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1297 GUC_HXG_ORIGIN_HOST); 1298 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1299 GUC_HXG_TYPE_REQUEST); 1300 1301 retry: 1302 /* Not in critical data-path, just do if else for GT type */ 1303 if (xe_gt_is_media_type(gt)) { 1304 for (i = 0; i < len; ++i) 1305 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1306 request[i]); 1307 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1308 } else { 1309 for (i = 0; i < len; ++i) 1310 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1311 request[i]); 1312 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1313 } 1314 1315 xe_guc_notify(guc); 1316 1317 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1318 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1319 50000, &reply, false); 1320 if (ret) { 1321 timeout: 1322 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1323 request[0], reply); 1324 return ret; 1325 } 1326 1327 header = xe_mmio_read32(mmio, reply_reg); 1328 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1329 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1330 /* 1331 * Once we got a BUSY reply we must wait again for the final 1332 * response but this time we can't use ORIGIN mask anymore. 1333 * To spot a right change in the reply, we take advantage that 1334 * response SUCCESS and FAILURE differ only by the single bit 1335 * and all other bits are set and can be used as a new mask. 1336 */ 1337 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1338 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1339 1340 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1341 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1342 1343 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1344 1000000, &header, false); 1345 1346 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1347 GUC_HXG_ORIGIN_GUC)) 1348 goto proto; 1349 if (unlikely(ret)) { 1350 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1351 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1352 goto proto; 1353 goto timeout; 1354 } 1355 } 1356 1357 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1358 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1359 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1360 1361 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1362 request[0], reason); 1363 goto retry; 1364 } 1365 1366 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1367 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1368 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1369 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1370 1371 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1372 request[0], error, hint); 1373 return -ENXIO; 1374 } 1375 1376 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1377 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1378 proto: 1379 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1380 request[0], header); 1381 return -EPROTO; 1382 } 1383 1384 /* Just copy entire possible message response */ 1385 if (response_buf) { 1386 response_buf[0] = header; 1387 1388 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1389 reply_reg.addr += sizeof(u32); 1390 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1391 } 1392 } 1393 1394 /* Use data from the GuC response as our return value */ 1395 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1396 } 1397 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1398 1399 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1400 { 1401 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1402 } 1403 1404 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1405 { 1406 struct xe_device *xe = guc_to_xe(guc); 1407 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1408 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1409 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1410 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1411 GUC_ACTION_HOST2GUC_SELF_CFG), 1412 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1413 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1414 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1415 lower_32_bits(val)), 1416 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1417 upper_32_bits(val)), 1418 }; 1419 int ret; 1420 1421 xe_assert(xe, len <= 2); 1422 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1423 1424 /* Self config must go over MMIO */ 1425 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1426 1427 if (unlikely(ret < 0)) 1428 return ret; 1429 if (unlikely(ret > 1)) 1430 return -EPROTO; 1431 if (unlikely(!ret)) 1432 return -ENOKEY; 1433 1434 return 0; 1435 } 1436 1437 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1438 { 1439 return guc_self_cfg(guc, key, 1, val); 1440 } 1441 1442 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1443 { 1444 return guc_self_cfg(guc, key, 2, val); 1445 } 1446 1447 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1448 { 1449 struct xe_gt *gt = guc_to_gt(guc); 1450 1451 if (IS_SRIOV_VF(gt_to_xe(gt))) 1452 xe_gt_sriov_vf_migrated_event_handler(gt); 1453 } 1454 1455 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1456 { 1457 if (iir & GUC_INTR_GUC2HOST) 1458 xe_guc_ct_irq_handler(&guc->ct); 1459 1460 if (iir & GUC_INTR_SW_INT_0) 1461 xe_guc_sw_0_irq_handler(guc); 1462 } 1463 1464 void xe_guc_sanitize(struct xe_guc *guc) 1465 { 1466 xe_uc_fw_sanitize(&guc->fw); 1467 xe_guc_ct_disable(&guc->ct); 1468 guc->submission_state.enabled = false; 1469 } 1470 1471 int xe_guc_reset_prepare(struct xe_guc *guc) 1472 { 1473 return xe_guc_submit_reset_prepare(guc); 1474 } 1475 1476 void xe_guc_reset_wait(struct xe_guc *guc) 1477 { 1478 xe_guc_submit_reset_wait(guc); 1479 } 1480 1481 void xe_guc_stop_prepare(struct xe_guc *guc) 1482 { 1483 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1484 int err; 1485 1486 err = xe_guc_pc_stop(&guc->pc); 1487 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1488 ERR_PTR(err)); 1489 } 1490 } 1491 1492 void xe_guc_stop(struct xe_guc *guc) 1493 { 1494 xe_guc_ct_stop(&guc->ct); 1495 1496 xe_guc_submit_stop(guc); 1497 } 1498 1499 int xe_guc_start(struct xe_guc *guc) 1500 { 1501 return xe_guc_submit_start(guc); 1502 } 1503 1504 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1505 { 1506 struct xe_gt *gt = guc_to_gt(guc); 1507 unsigned int fw_ref; 1508 u32 status; 1509 int i; 1510 1511 xe_uc_fw_print(&guc->fw, p); 1512 1513 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1514 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1515 if (!fw_ref) 1516 return; 1517 1518 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1519 1520 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1521 drm_printf(p, "\tBootrom status = 0x%x\n", 1522 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1523 drm_printf(p, "\tuKernel status = 0x%x\n", 1524 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1525 drm_printf(p, "\tMIA Core status = 0x%x\n", 1526 REG_FIELD_GET(GS_MIA_MASK, status)); 1527 drm_printf(p, "\tLog level = %d\n", 1528 xe_guc_log_get_level(&guc->log)); 1529 1530 drm_puts(p, "\nScratch registers:\n"); 1531 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1532 drm_printf(p, "\t%2d: \t0x%x\n", 1533 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1534 } 1535 1536 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1537 } 1538 1539 drm_puts(p, "\n"); 1540 xe_guc_ct_print(&guc->ct, p, false); 1541 1542 drm_puts(p, "\n"); 1543 xe_guc_submit_print(guc, p); 1544 } 1545 1546 /** 1547 * xe_guc_declare_wedged() - Declare GuC wedged 1548 * @guc: the GuC object 1549 * 1550 * Wedge the GuC which stops all submission, saves desired debug state, and 1551 * cleans up anything which could timeout. 1552 */ 1553 void xe_guc_declare_wedged(struct xe_guc *guc) 1554 { 1555 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1556 1557 xe_guc_reset_prepare(guc); 1558 xe_guc_ct_stop(&guc->ct); 1559 xe_guc_submit_wedge(guc); 1560 } 1561