1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "abi/guc_actions_abi.h" 13 #include "abi/guc_errors_abi.h" 14 #include "regs/xe_gt_regs.h" 15 #include "regs/xe_gtt_defs.h" 16 #include "regs/xe_guc_regs.h" 17 #include "regs/xe_irq_regs.h" 18 #include "xe_bo.h" 19 #include "xe_device.h" 20 #include "xe_force_wake.h" 21 #include "xe_gt.h" 22 #include "xe_gt_printk.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_gt_throttle.h" 25 #include "xe_guc_ads.h" 26 #include "xe_guc_buf.h" 27 #include "xe_guc_capture.h" 28 #include "xe_guc_ct.h" 29 #include "xe_guc_db_mgr.h" 30 #include "xe_guc_hwconfig.h" 31 #include "xe_guc_log.h" 32 #include "xe_guc_pc.h" 33 #include "xe_guc_relay.h" 34 #include "xe_guc_submit.h" 35 #include "xe_memirq.h" 36 #include "xe_mmio.h" 37 #include "xe_platform_types.h" 38 #include "xe_sriov.h" 39 #include "xe_uc.h" 40 #include "xe_uc_fw.h" 41 #include "xe_wa.h" 42 #include "xe_wopcm.h" 43 44 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 45 struct xe_bo *bo) 46 { 47 struct xe_device *xe = guc_to_xe(guc); 48 u32 addr; 49 50 /* 51 * For most BOs, the address on the allocating tile is fine. However for 52 * some, e.g. G2G CTB, the address on a specific tile is required as it 53 * might be different for each tile. So, just always ask for the address 54 * on the target GuC. 55 */ 56 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 57 58 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 59 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 60 xe_assert(xe, addr < GUC_GGTT_TOP); 61 xe_assert(xe, bo->size <= GUC_GGTT_TOP - addr); 62 63 return addr; 64 } 65 66 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 67 { 68 u32 level = xe_guc_log_get_level(&guc->log); 69 u32 flags = 0; 70 71 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 72 flags |= GUC_LOG_DISABLED; 73 else 74 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 75 GUC_LOG_VERBOSITY_SHIFT; 76 77 return flags; 78 } 79 80 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 81 { 82 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 83 84 if (!guc_to_xe(guc)->info.skip_guc_pc) 85 flags |= GUC_CTL_ENABLE_SLPC; 86 87 return flags; 88 } 89 90 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 91 { 92 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 93 u32 flags; 94 95 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 96 #define LOG_UNIT SZ_1M 97 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 98 #else 99 #define LOG_UNIT SZ_4K 100 #define LOG_FLAG 0 101 #endif 102 103 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 104 #define CAPTURE_UNIT SZ_1M 105 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 106 #else 107 #define CAPTURE_UNIT SZ_4K 108 #define CAPTURE_FLAG 0 109 #endif 110 111 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 112 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 113 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 114 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 115 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 116 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 117 118 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 119 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 120 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 121 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 122 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 123 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 124 125 flags = GUC_LOG_VALID | 126 GUC_LOG_NOTIFY_ON_HALF_FULL | 127 CAPTURE_FLAG | 128 LOG_FLAG | 129 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 130 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 131 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << 132 GUC_LOG_CAPTURE_SHIFT) | 133 (offset << GUC_LOG_BUF_ADDR_SHIFT); 134 135 #undef LOG_UNIT 136 #undef LOG_FLAG 137 #undef CAPTURE_UNIT 138 #undef CAPTURE_FLAG 139 140 return flags; 141 } 142 143 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 144 { 145 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 146 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 147 148 return flags; 149 } 150 151 static bool needs_wa_dual_queue(struct xe_gt *gt) 152 { 153 /* 154 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 155 * on RCS and CCSes with different address spaces, which on DG2 is 156 * required as a WA for an HW bug. 157 */ 158 if (XE_WA(gt, 22011391025)) 159 return true; 160 161 /* 162 * On newer platforms, the HW has been updated to not allow parallel 163 * execution of different address spaces, so the RCS/CCS will stall the 164 * context switch if one of the other RCS/CCSes is busy with a different 165 * address space. While functionally correct, having a submission 166 * stalled on the HW limits the GuC ability to shuffle things around and 167 * can cause complications if the non-stalled submission runs for a long 168 * time, because the GuC doesn't know that the stalled submission isn't 169 * actually running and might declare it as hung. Therefore, we enable 170 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 171 * to move management back to the GuC. 172 */ 173 if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 174 return true; 175 176 return false; 177 } 178 179 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 180 { 181 struct xe_device *xe = guc_to_xe(guc); 182 struct xe_gt *gt = guc_to_gt(guc); 183 u32 flags = 0; 184 185 if (XE_WA(gt, 22012773006)) 186 flags |= GUC_WA_POLLCS; 187 188 if (XE_WA(gt, 14014475959)) 189 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 190 191 if (needs_wa_dual_queue(gt)) 192 flags |= GUC_WA_DUAL_QUEUE; 193 194 /* 195 * Wa_22011802037: FIXME - there's more to be done than simply setting 196 * this flag: make sure each CS is stopped when preparing for GT reset 197 * and wait for pending MI_FW. 198 */ 199 if (GRAPHICS_VERx100(xe) < 1270) 200 flags |= GUC_WA_PRE_PARSER; 201 202 if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685)) 203 flags |= GUC_WA_CONTEXT_ISOLATION; 204 205 if (XE_WA(gt, 18020744125) && 206 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 207 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 208 209 if (XE_WA(gt, 1509372804)) 210 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 211 212 if (XE_WA(gt, 14018913170)) 213 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 214 215 return flags; 216 } 217 218 static u32 guc_ctl_devid(struct xe_guc *guc) 219 { 220 struct xe_device *xe = guc_to_xe(guc); 221 222 return (((u32)xe->info.devid) << 16) | xe->info.revid; 223 } 224 225 static void guc_print_params(struct xe_guc *guc) 226 { 227 struct xe_gt *gt = guc_to_gt(guc); 228 u32 *params = guc->params; 229 int i; 230 231 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 232 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 233 234 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 235 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 236 } 237 238 static void guc_init_params(struct xe_guc *guc) 239 { 240 u32 *params = guc->params; 241 242 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 243 params[GUC_CTL_FEATURE] = 0; 244 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 245 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 246 params[GUC_CTL_WA] = 0; 247 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 248 249 guc_print_params(guc); 250 } 251 252 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 253 { 254 u32 *params = guc->params; 255 256 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 257 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 258 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 259 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 260 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 261 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 262 263 guc_print_params(guc); 264 } 265 266 /* 267 * Initialize the GuC parameter block before starting the firmware 268 * transfer. These parameters are read by the firmware on startup 269 * and cannot be changed thereafter. 270 */ 271 static void guc_write_params(struct xe_guc *guc) 272 { 273 struct xe_gt *gt = guc_to_gt(guc); 274 int i; 275 276 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 277 278 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 279 280 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 281 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 282 } 283 284 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 285 u32 desc_addr, u32 buff_addr, u32 size) 286 { 287 struct xe_gt *gt = guc_to_gt(guc); 288 struct xe_device *xe = gt_to_xe(gt); 289 u32 action[] = { 290 XE_GUC_ACTION_REGISTER_G2G, 291 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 292 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 293 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 294 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 295 desc_addr, 296 buff_addr, 297 }; 298 299 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 300 xe_assert(xe, !(size % SZ_4K)); 301 302 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 303 } 304 305 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 306 { 307 struct xe_gt *gt = guc_to_gt(guc); 308 struct xe_device *xe = gt_to_xe(gt); 309 u32 action[] = { 310 XE_GUC_ACTION_DEREGISTER_G2G, 311 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 312 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 313 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 314 }; 315 316 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 317 318 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 319 } 320 321 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 322 323 #define G2G_BUFFER_SIZE (SZ_4K) 324 #define G2G_DESC_SIZE (64) 325 #define G2G_DESC_AREA_SIZE (SZ_4K) 326 327 /* 328 * Generate a unique id for each bi-directional CTB for each pair of 329 * near and far tiles/devices. The id can then be used as an index into 330 * a single allocation that is sub-divided into multiple CTBs. 331 * 332 * For example, with two devices per tile and two tiles, the table should 333 * look like: 334 * Far <tile>.<dev> 335 * 0.0 0.1 1.0 1.1 336 * N 0.0 --/-- 00/01 02/03 04/05 337 * e 0.1 01/00 --/-- 06/07 08/09 338 * a 1.0 03/02 07/06 --/-- 10/11 339 * r 1.1 05/04 09/08 11/10 --/-- 340 * 341 * Where each entry is Rx/Tx channel id. 342 * 343 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 344 * be reading from channel #11 and writing to channel #10. Whereas, 345 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 346 */ 347 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 348 u32 type, u32 max_inst, bool have_dev) 349 { 350 u32 near = near_tile, far = far_tile; 351 u32 idx = 0, x, y, direction; 352 int i; 353 354 if (have_dev) { 355 near = (near << 1) | near_dev; 356 far = (far << 1) | far_dev; 357 } 358 359 /* No need to send to one's self */ 360 if (far == near) 361 return -1; 362 363 if (far > near) { 364 /* Top right table half */ 365 x = far; 366 y = near; 367 368 /* T/R is 'forwards' direction */ 369 direction = type; 370 } else { 371 /* Bottom left table half */ 372 x = near; 373 y = far; 374 375 /* B/L is 'backwards' direction */ 376 direction = (1 - type); 377 } 378 379 /* Count the rows prior to the target */ 380 for (i = y; i > 0; i--) 381 idx += max_inst - i; 382 383 /* Count this row up to the target */ 384 idx += (x - 1 - y); 385 386 /* Slots are in Rx/Tx pairs */ 387 idx *= 2; 388 389 /* Pick Rx/Tx direction */ 390 idx += direction; 391 392 return idx; 393 } 394 395 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 396 { 397 struct xe_gt *near_gt = guc_to_gt(near_guc); 398 struct xe_device *xe = gt_to_xe(near_gt); 399 struct xe_bo *g2g_bo; 400 u32 near_tile = gt_to_tile(near_gt)->id; 401 u32 near_dev = G2G_DEV(near_gt); 402 u32 far_tile = gt_to_tile(far_gt)->id; 403 u32 far_dev = G2G_DEV(far_gt); 404 u32 max = xe->info.gt_count; 405 u32 base, desc, buf; 406 int slot; 407 408 /* G2G is not allowed between different cards */ 409 xe_assert(xe, xe == gt_to_xe(far_gt)); 410 411 g2g_bo = near_guc->g2g.bo; 412 xe_assert(xe, g2g_bo); 413 414 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 415 xe_assert(xe, slot >= 0); 416 417 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 418 desc = base + slot * G2G_DESC_SIZE; 419 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 420 421 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 422 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= g2g_bo->size); 423 424 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 425 desc, buf, G2G_BUFFER_SIZE); 426 } 427 428 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 429 { 430 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 431 } 432 433 static u32 guc_g2g_size(struct xe_guc *guc) 434 { 435 struct xe_gt *gt = guc_to_gt(guc); 436 struct xe_device *xe = gt_to_xe(gt); 437 unsigned int count = xe->info.gt_count; 438 u32 num_channels = (count * (count - 1)) / 2; 439 440 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 441 442 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 443 } 444 445 static bool xe_guc_g2g_wanted(struct xe_device *xe) 446 { 447 /* Can't do GuC to GuC communication if there is only one GuC */ 448 if (xe->info.gt_count <= 1) 449 return false; 450 451 /* No current user */ 452 return false; 453 } 454 455 static int guc_g2g_alloc(struct xe_guc *guc) 456 { 457 struct xe_gt *gt = guc_to_gt(guc); 458 struct xe_device *xe = gt_to_xe(gt); 459 struct xe_tile *tile = gt_to_tile(gt); 460 struct xe_bo *bo; 461 u32 g2g_size; 462 463 if (guc->g2g.bo) 464 return 0; 465 466 if (gt->info.id != 0) { 467 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 468 struct xe_guc *root_guc = &root_gt->uc.guc; 469 struct xe_bo *bo; 470 471 bo = xe_bo_get(root_guc->g2g.bo); 472 if (!bo) 473 return -ENODEV; 474 475 guc->g2g.bo = bo; 476 guc->g2g.owned = false; 477 return 0; 478 } 479 480 g2g_size = guc_g2g_size(guc); 481 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 482 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 483 XE_BO_FLAG_GGTT | 484 XE_BO_FLAG_GGTT_ALL | 485 XE_BO_FLAG_GGTT_INVALIDATE); 486 if (IS_ERR(bo)) 487 return PTR_ERR(bo); 488 489 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 490 guc->g2g.bo = bo; 491 guc->g2g.owned = true; 492 493 return 0; 494 } 495 496 static void guc_g2g_fini(struct xe_guc *guc) 497 { 498 if (!guc->g2g.bo) 499 return; 500 501 /* Unpinning the owned object is handled by generic shutdown */ 502 if (!guc->g2g.owned) 503 xe_bo_put(guc->g2g.bo); 504 505 guc->g2g.bo = NULL; 506 } 507 508 static int guc_g2g_start(struct xe_guc *guc) 509 { 510 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 511 struct xe_device *xe = gt_to_xe(gt); 512 unsigned int i, j; 513 int t, err; 514 bool have_dev; 515 516 if (!guc->g2g.bo) { 517 int ret; 518 519 ret = guc_g2g_alloc(guc); 520 if (ret) 521 return ret; 522 } 523 524 /* GuC interface will need extending if more GT device types are ever created. */ 525 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 526 527 /* Channel numbering depends on whether there are multiple GTs per tile */ 528 have_dev = xe->info.gt_count > xe->info.tile_count; 529 530 for_each_gt(far_gt, xe, i) { 531 u32 far_tile, far_dev; 532 533 if (far_gt->info.id == gt->info.id) 534 continue; 535 536 far_tile = gt_to_tile(far_gt)->id; 537 far_dev = G2G_DEV(far_gt); 538 539 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 540 err = guc_g2g_register(guc, far_gt, t, have_dev); 541 if (err) { 542 while (--t >= 0) 543 guc_g2g_deregister(guc, far_tile, far_dev, t); 544 goto err_deregister; 545 } 546 } 547 } 548 549 return 0; 550 551 err_deregister: 552 for_each_gt(far_gt, xe, j) { 553 u32 tile, dev; 554 555 if (far_gt->info.id == gt->info.id) 556 continue; 557 558 if (j >= i) 559 break; 560 561 tile = gt_to_tile(far_gt)->id; 562 dev = G2G_DEV(far_gt); 563 564 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 565 guc_g2g_deregister(guc, tile, dev, t); 566 } 567 568 return err; 569 } 570 571 static void guc_fini_hw(void *arg) 572 { 573 struct xe_guc *guc = arg; 574 struct xe_gt *gt = guc_to_gt(guc); 575 unsigned int fw_ref; 576 577 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 578 xe_uc_fini_hw(&guc_to_gt(guc)->uc); 579 xe_force_wake_put(gt_to_fw(gt), fw_ref); 580 581 guc_g2g_fini(guc); 582 } 583 584 /** 585 * xe_guc_comm_init_early - early initialization of GuC communication 586 * @guc: the &xe_guc to initialize 587 * 588 * Must be called prior to first MMIO communication with GuC firmware. 589 */ 590 void xe_guc_comm_init_early(struct xe_guc *guc) 591 { 592 struct xe_gt *gt = guc_to_gt(guc); 593 594 if (xe_gt_is_media_type(gt)) 595 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 596 else 597 guc->notify_reg = GUC_HOST_INTERRUPT; 598 } 599 600 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 601 { 602 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 603 struct xe_device *xe = guc_to_xe(guc); 604 int ret; 605 606 if (!IS_DGFX(guc_to_xe(guc))) 607 return 0; 608 609 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 610 if (ret) 611 return ret; 612 613 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 614 if (ret) 615 return ret; 616 617 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 618 if (ret) 619 return ret; 620 621 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo); 622 if (ret) 623 return ret; 624 625 return 0; 626 } 627 628 static int vf_guc_init(struct xe_guc *guc) 629 { 630 int err; 631 632 xe_guc_comm_init_early(guc); 633 634 err = xe_guc_ct_init(&guc->ct); 635 if (err) 636 return err; 637 638 err = xe_guc_relay_init(&guc->relay); 639 if (err) 640 return err; 641 642 return 0; 643 } 644 645 int xe_guc_init(struct xe_guc *guc) 646 { 647 struct xe_device *xe = guc_to_xe(guc); 648 struct xe_gt *gt = guc_to_gt(guc); 649 int ret; 650 651 guc->fw.type = XE_UC_FW_TYPE_GUC; 652 ret = xe_uc_fw_init(&guc->fw); 653 if (ret) 654 goto out; 655 656 if (!xe_uc_fw_is_enabled(&guc->fw)) 657 return 0; 658 659 if (IS_SRIOV_VF(xe)) { 660 ret = vf_guc_init(guc); 661 if (ret) 662 goto out; 663 return 0; 664 } 665 666 ret = xe_guc_log_init(&guc->log); 667 if (ret) 668 goto out; 669 670 ret = xe_guc_capture_init(guc); 671 if (ret) 672 goto out; 673 674 ret = xe_guc_ads_init(&guc->ads); 675 if (ret) 676 goto out; 677 678 ret = xe_guc_ct_init(&guc->ct); 679 if (ret) 680 goto out; 681 682 ret = xe_guc_relay_init(&guc->relay); 683 if (ret) 684 goto out; 685 686 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 687 688 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 689 if (ret) 690 goto out; 691 692 guc_init_params(guc); 693 694 xe_guc_comm_init_early(guc); 695 696 return 0; 697 698 out: 699 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 700 return ret; 701 } 702 703 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 704 { 705 int err; 706 707 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 708 if (err) 709 return err; 710 711 /* XXX xe_guc_db_mgr_init not needed for now */ 712 713 return 0; 714 } 715 716 /** 717 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 718 * @guc: The GuC object 719 * 720 * Return: 0 on success, negative error code on error. 721 */ 722 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 723 { 724 int ret; 725 726 if (IS_SRIOV_VF(guc_to_xe(guc))) 727 return vf_guc_init_post_hwconfig(guc); 728 729 ret = xe_guc_realloc_post_hwconfig(guc); 730 if (ret) 731 return ret; 732 733 guc_init_params_post_hwconfig(guc); 734 735 ret = xe_guc_submit_init(guc, ~0); 736 if (ret) 737 return ret; 738 739 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 740 if (ret) 741 return ret; 742 743 ret = xe_guc_pc_init(&guc->pc); 744 if (ret) 745 return ret; 746 747 ret = xe_guc_buf_cache_init(&guc->buf); 748 if (ret) 749 return ret; 750 751 return xe_guc_ads_init_post_hwconfig(&guc->ads); 752 } 753 754 int xe_guc_post_load_init(struct xe_guc *guc) 755 { 756 int ret; 757 758 xe_guc_ads_populate_post_load(&guc->ads); 759 760 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 761 ret = guc_g2g_start(guc); 762 if (ret) 763 return ret; 764 } 765 766 guc->submission_state.enabled = true; 767 768 return 0; 769 } 770 771 int xe_guc_reset(struct xe_guc *guc) 772 { 773 struct xe_gt *gt = guc_to_gt(guc); 774 struct xe_mmio *mmio = >->mmio; 775 u32 guc_status, gdrst; 776 int ret; 777 778 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 779 780 if (IS_SRIOV_VF(gt_to_xe(gt))) 781 return xe_gt_sriov_vf_bootstrap(gt); 782 783 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 784 785 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 786 if (ret) { 787 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 788 goto err_out; 789 } 790 791 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 792 if (!(guc_status & GS_MIA_IN_RESET)) { 793 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 794 guc_status); 795 ret = -EIO; 796 goto err_out; 797 } 798 799 return 0; 800 801 err_out: 802 803 return ret; 804 } 805 806 static void guc_prepare_xfer(struct xe_guc *guc) 807 { 808 struct xe_gt *gt = guc_to_gt(guc); 809 struct xe_mmio *mmio = >->mmio; 810 struct xe_device *xe = guc_to_xe(guc); 811 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 812 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 813 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 814 GUC_ENABLE_MIA_CLOCK_GATING; 815 816 if (GRAPHICS_VERx100(xe) < 1250) 817 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 818 GUC_ENABLE_MIA_CACHING; 819 820 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 821 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 822 823 /* Must program this register before loading the ucode with DMA */ 824 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 825 826 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 827 828 /* Make sure GuC receives ARAT interrupts */ 829 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 830 } 831 832 /* 833 * Supporting MMIO & in memory RSA 834 */ 835 static int guc_xfer_rsa(struct xe_guc *guc) 836 { 837 struct xe_gt *gt = guc_to_gt(guc); 838 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 839 size_t copied; 840 int i; 841 842 if (guc->fw.rsa_size > 256) { 843 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 844 xe_uc_fw_rsa_offset(&guc->fw); 845 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 846 return 0; 847 } 848 849 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 850 if (copied < sizeof(rsa)) 851 return -ENOMEM; 852 853 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 854 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 855 856 return 0; 857 } 858 859 /* 860 * Check a previously read GuC status register (GUC_STATUS) looking for 861 * known terminal states (either completion or failure) of either the 862 * microkernel status field or the boot ROM status field. Returns +1 for 863 * successful completion, -1 for failure and 0 for any intermediate state. 864 */ 865 static int guc_load_done(u32 status) 866 { 867 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); 868 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); 869 870 switch (uk_val) { 871 case XE_GUC_LOAD_STATUS_READY: 872 return 1; 873 874 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 875 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 876 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 877 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 878 case XE_GUC_LOAD_STATUS_DPC_ERROR: 879 case XE_GUC_LOAD_STATUS_EXCEPTION: 880 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 881 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 882 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 883 return -1; 884 } 885 886 switch (br_val) { 887 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 888 case XE_BOOTROM_STATUS_RSA_FAILED: 889 case XE_BOOTROM_STATUS_PAVPC_FAILED: 890 case XE_BOOTROM_STATUS_WOPCM_FAILED: 891 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 892 case XE_BOOTROM_STATUS_JUMP_FAILED: 893 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 894 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 895 case XE_BOOTROM_STATUS_EXCEPTION: 896 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 897 return -1; 898 } 899 900 return 0; 901 } 902 903 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) 904 { 905 u32 freq; 906 int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq); 907 908 return ret ? ret : freq; 909 } 910 911 /* 912 * Wait for the GuC to start up. 913 * 914 * Measurements indicate this should take no more than 20ms (assuming the GT 915 * clock is at maximum frequency). However, thermal throttling and other issues 916 * can prevent the clock hitting max and thus making the load take significantly 917 * longer. Allow up to 200ms as a safety margin for real world worst case situations. 918 * 919 * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can 920 * lead to even longer times. E.g. if the GT is clamped to minimum frequency then 921 * the load times can be in the seconds range. So the timeout is increased for debug 922 * builds to ensure that problems can be correctly analysed. For release builds, the 923 * timeout is kept short so that users don't wait forever to find out that there is a 924 * problem. In either case, if the load took longer than is reasonable even with some 925 * 'sensible' throttling, then flag a warning because something is not right. 926 * 927 * Note that there is a limit on how long an individual usleep_range() can wait for, 928 * hence longer waits require wrapping a shorter wait in a loop. 929 * 930 * Note that the only reason an end user should hit the shorter timeout is in case of 931 * extreme thermal throttling. And a system that is that hot during boot is probably 932 * dead anyway! 933 */ 934 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 935 #define GUC_LOAD_RETRY_LIMIT 20 936 #else 937 #define GUC_LOAD_RETRY_LIMIT 3 938 #endif 939 #define GUC_LOAD_TIME_WARN_MS 200 940 941 static void guc_wait_ucode(struct xe_guc *guc) 942 { 943 struct xe_gt *gt = guc_to_gt(guc); 944 struct xe_mmio *mmio = >->mmio; 945 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 946 ktime_t before, after, delta; 947 int load_done; 948 u32 status = 0; 949 int count = 0; 950 u64 delta_ms; 951 u32 before_freq; 952 953 before_freq = xe_guc_pc_get_act_freq(guc_pc); 954 before = ktime_get(); 955 /* 956 * Note, can't use any kind of timing information from the call to xe_mmio_wait. 957 * It could return a thousand intermediate stages at random times. Instead, must 958 * manually track the total time taken and locally implement the timeout. 959 */ 960 do { 961 u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK); 962 int ret; 963 964 /* 965 * Wait for any change (intermediate or terminal) in the status register. 966 * Note, the return value is a don't care. The only failure code is timeout 967 * but the timeouts need to be accumulated over all the intermediate partial 968 * timeouts rather than allowing a huge timeout each time. So basically, need 969 * to treat a timeout no different to a value change. 970 */ 971 ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK, 972 last_status, 1000 * 1000, &status, false); 973 if (ret < 0) 974 count++; 975 after = ktime_get(); 976 delta = ktime_sub(after, before); 977 delta_ms = ktime_to_ms(delta); 978 979 load_done = guc_load_done(status); 980 if (load_done != 0) 981 break; 982 983 if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000)) 984 break; 985 986 xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 987 count, xe_guc_pc_get_act_freq(guc_pc), 988 guc_pc_get_cur_freq(guc_pc), status, 989 REG_FIELD_GET(GS_BOOTROM_MASK, status), 990 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 991 } while (1); 992 993 if (load_done != 1) { 994 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 995 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 996 997 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n", 998 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 999 guc_pc_get_cur_freq(guc_pc), load_done); 1000 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1001 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1002 bootrom, ukernel, 1003 REG_FIELD_GET(GS_MIA_MASK, status), 1004 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1005 1006 switch (bootrom) { 1007 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1008 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1009 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1010 break; 1011 1012 case XE_BOOTROM_STATUS_RSA_FAILED: 1013 xe_gt_err(gt, "firmware signature verification failed\n"); 1014 break; 1015 1016 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1017 xe_gt_err(gt, "firmware production part check failure\n"); 1018 break; 1019 } 1020 1021 switch (ukernel) { 1022 case XE_GUC_LOAD_STATUS_EXCEPTION: 1023 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1024 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1025 break; 1026 1027 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1028 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1029 break; 1030 1031 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1032 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1033 break; 1034 } 1035 1036 xe_device_declare_wedged(gt_to_xe(gt)); 1037 } else if (delta_ms > GUC_LOAD_TIME_WARN_MS) { 1038 xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n", 1039 delta_ms, status, count); 1040 xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1041 xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1042 before_freq, xe_gt_throttle_get_limit_reasons(gt)); 1043 } else { 1044 xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n", 1045 delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1046 before_freq, status, count); 1047 } 1048 } 1049 1050 static int __xe_guc_upload(struct xe_guc *guc) 1051 { 1052 int ret; 1053 1054 /* Raise GT freq to speed up HuC/GuC load */ 1055 xe_guc_pc_raise_unslice(&guc->pc); 1056 1057 guc_write_params(guc); 1058 guc_prepare_xfer(guc); 1059 1060 /* 1061 * Note that GuC needs the CSS header plus uKernel code to be copied 1062 * by the DMA engine in one operation, whereas the RSA signature is 1063 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1064 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1065 * size > 256). The RSA size and therefore the way we provide it to the 1066 * HW is fixed for each platform and hard-coded in the bootrom. 1067 */ 1068 ret = guc_xfer_rsa(guc); 1069 if (ret) 1070 goto out; 1071 /* 1072 * Current uCode expects the code to be loaded at 8k; locations below 1073 * this are used for the stack. 1074 */ 1075 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1076 if (ret) 1077 goto out; 1078 1079 /* Wait for authentication */ 1080 guc_wait_ucode(guc); 1081 1082 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1083 return 0; 1084 1085 out: 1086 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1087 return 0 /* FIXME: ret, don't want to stop load currently */; 1088 } 1089 1090 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1091 { 1092 struct xe_gt *gt = guc_to_gt(guc); 1093 int ret; 1094 1095 ret = xe_gt_sriov_vf_bootstrap(gt); 1096 if (ret) 1097 return ret; 1098 1099 ret = xe_gt_sriov_vf_query_config(gt); 1100 if (ret) 1101 return ret; 1102 1103 ret = xe_guc_hwconfig_init(guc); 1104 if (ret) 1105 return ret; 1106 1107 ret = xe_guc_enable_communication(guc); 1108 if (ret) 1109 return ret; 1110 1111 ret = xe_gt_sriov_vf_connect(gt); 1112 if (ret) 1113 return ret; 1114 1115 ret = xe_gt_sriov_vf_query_runtime(gt); 1116 if (ret) 1117 return ret; 1118 1119 return 0; 1120 } 1121 1122 /** 1123 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1124 * @guc: The GuC object 1125 * 1126 * This function uploads a minimal GuC that does not support submissions but 1127 * in a state where the hwconfig table can be read. Next, it reads and parses 1128 * the hwconfig table so it can be used for subsequent steps in the driver load. 1129 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1130 * 1131 * Return: 0 on success, negative error code on error. 1132 */ 1133 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1134 { 1135 int ret; 1136 1137 if (IS_SRIOV_VF(guc_to_xe(guc))) 1138 return vf_guc_min_load_for_hwconfig(guc); 1139 1140 xe_guc_ads_populate_minimal(&guc->ads); 1141 1142 xe_guc_pc_init_early(&guc->pc); 1143 1144 ret = __xe_guc_upload(guc); 1145 if (ret) 1146 return ret; 1147 1148 ret = xe_guc_hwconfig_init(guc); 1149 if (ret) 1150 return ret; 1151 1152 ret = xe_guc_enable_communication(guc); 1153 if (ret) 1154 return ret; 1155 1156 return 0; 1157 } 1158 1159 int xe_guc_upload(struct xe_guc *guc) 1160 { 1161 xe_guc_ads_populate(&guc->ads); 1162 1163 return __xe_guc_upload(guc); 1164 } 1165 1166 static void guc_handle_mmio_msg(struct xe_guc *guc) 1167 { 1168 struct xe_gt *gt = guc_to_gt(guc); 1169 u32 msg; 1170 1171 if (IS_SRIOV_VF(guc_to_xe(guc))) 1172 return; 1173 1174 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1175 1176 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1177 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1178 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1179 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1180 1181 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1182 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1183 1184 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1185 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1186 } 1187 1188 static void guc_enable_irq(struct xe_guc *guc) 1189 { 1190 struct xe_gt *gt = guc_to_gt(guc); 1191 u32 events = xe_gt_is_media_type(gt) ? 1192 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1193 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1194 1195 /* Primary GuC and media GuC share a single enable bit */ 1196 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1197 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1198 1199 /* 1200 * There are separate mask bits for primary and media GuCs, so use 1201 * a RMW operation to avoid clobbering the other GuC's setting. 1202 */ 1203 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1204 } 1205 1206 int xe_guc_enable_communication(struct xe_guc *guc) 1207 { 1208 struct xe_device *xe = guc_to_xe(guc); 1209 int err; 1210 1211 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1212 struct xe_gt *gt = guc_to_gt(guc); 1213 struct xe_tile *tile = gt_to_tile(gt); 1214 1215 err = xe_memirq_init_guc(&tile->memirq, guc); 1216 if (err) 1217 return err; 1218 } else { 1219 guc_enable_irq(guc); 1220 } 1221 1222 err = xe_guc_ct_enable(&guc->ct); 1223 if (err) 1224 return err; 1225 1226 guc_handle_mmio_msg(guc); 1227 1228 return 0; 1229 } 1230 1231 int xe_guc_suspend(struct xe_guc *guc) 1232 { 1233 struct xe_gt *gt = guc_to_gt(guc); 1234 u32 action[] = { 1235 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1236 }; 1237 int ret; 1238 1239 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1240 if (ret) { 1241 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1242 return ret; 1243 } 1244 1245 xe_guc_sanitize(guc); 1246 return 0; 1247 } 1248 1249 void xe_guc_notify(struct xe_guc *guc) 1250 { 1251 struct xe_gt *gt = guc_to_gt(guc); 1252 const u32 default_notify_data = 0; 1253 1254 /* 1255 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1256 * additional payload data to the GuC but this capability is not 1257 * used by the firmware yet. Use default value in the meantime. 1258 */ 1259 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1260 } 1261 1262 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1263 { 1264 u32 action[] = { 1265 XE_GUC_ACTION_AUTHENTICATE_HUC, 1266 rsa_addr 1267 }; 1268 1269 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1270 } 1271 1272 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1273 u32 len, u32 *response_buf) 1274 { 1275 struct xe_device *xe = guc_to_xe(guc); 1276 struct xe_gt *gt = guc_to_gt(guc); 1277 struct xe_mmio *mmio = >->mmio; 1278 u32 header, reply; 1279 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1280 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1281 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1282 int ret; 1283 int i; 1284 1285 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1286 1287 xe_assert(xe, len); 1288 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1289 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1290 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1291 GUC_HXG_ORIGIN_HOST); 1292 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1293 GUC_HXG_TYPE_REQUEST); 1294 1295 retry: 1296 /* Not in critical data-path, just do if else for GT type */ 1297 if (xe_gt_is_media_type(gt)) { 1298 for (i = 0; i < len; ++i) 1299 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1300 request[i]); 1301 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1302 } else { 1303 for (i = 0; i < len; ++i) 1304 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1305 request[i]); 1306 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1307 } 1308 1309 xe_guc_notify(guc); 1310 1311 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1312 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1313 50000, &reply, false); 1314 if (ret) { 1315 timeout: 1316 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1317 request[0], reply); 1318 return ret; 1319 } 1320 1321 header = xe_mmio_read32(mmio, reply_reg); 1322 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1323 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1324 /* 1325 * Once we got a BUSY reply we must wait again for the final 1326 * response but this time we can't use ORIGIN mask anymore. 1327 * To spot a right change in the reply, we take advantage that 1328 * response SUCCESS and FAILURE differ only by the single bit 1329 * and all other bits are set and can be used as a new mask. 1330 */ 1331 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1332 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1333 1334 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1335 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1336 1337 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1338 1000000, &header, false); 1339 1340 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1341 GUC_HXG_ORIGIN_GUC)) 1342 goto proto; 1343 if (unlikely(ret)) { 1344 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1345 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1346 goto proto; 1347 goto timeout; 1348 } 1349 } 1350 1351 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1352 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1353 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1354 1355 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1356 request[0], reason); 1357 goto retry; 1358 } 1359 1360 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1361 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1362 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1363 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1364 1365 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1366 request[0], error, hint); 1367 return -ENXIO; 1368 } 1369 1370 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1371 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1372 proto: 1373 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1374 request[0], header); 1375 return -EPROTO; 1376 } 1377 1378 /* Just copy entire possible message response */ 1379 if (response_buf) { 1380 response_buf[0] = header; 1381 1382 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1383 reply_reg.addr += sizeof(u32); 1384 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1385 } 1386 } 1387 1388 /* Use data from the GuC response as our return value */ 1389 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1390 } 1391 1392 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1393 { 1394 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1395 } 1396 1397 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1398 { 1399 struct xe_device *xe = guc_to_xe(guc); 1400 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1401 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1402 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1403 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1404 GUC_ACTION_HOST2GUC_SELF_CFG), 1405 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1406 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1407 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1408 lower_32_bits(val)), 1409 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1410 upper_32_bits(val)), 1411 }; 1412 int ret; 1413 1414 xe_assert(xe, len <= 2); 1415 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1416 1417 /* Self config must go over MMIO */ 1418 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1419 1420 if (unlikely(ret < 0)) 1421 return ret; 1422 if (unlikely(ret > 1)) 1423 return -EPROTO; 1424 if (unlikely(!ret)) 1425 return -ENOKEY; 1426 1427 return 0; 1428 } 1429 1430 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1431 { 1432 return guc_self_cfg(guc, key, 1, val); 1433 } 1434 1435 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1436 { 1437 return guc_self_cfg(guc, key, 2, val); 1438 } 1439 1440 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1441 { 1442 struct xe_gt *gt = guc_to_gt(guc); 1443 1444 if (IS_SRIOV_VF(gt_to_xe(gt))) 1445 xe_gt_sriov_vf_migrated_event_handler(gt); 1446 } 1447 1448 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1449 { 1450 if (iir & GUC_INTR_GUC2HOST) 1451 xe_guc_ct_irq_handler(&guc->ct); 1452 1453 if (iir & GUC_INTR_SW_INT_0) 1454 xe_guc_sw_0_irq_handler(guc); 1455 } 1456 1457 void xe_guc_sanitize(struct xe_guc *guc) 1458 { 1459 xe_uc_fw_sanitize(&guc->fw); 1460 xe_guc_ct_disable(&guc->ct); 1461 guc->submission_state.enabled = false; 1462 } 1463 1464 int xe_guc_reset_prepare(struct xe_guc *guc) 1465 { 1466 return xe_guc_submit_reset_prepare(guc); 1467 } 1468 1469 void xe_guc_reset_wait(struct xe_guc *guc) 1470 { 1471 xe_guc_submit_reset_wait(guc); 1472 } 1473 1474 void xe_guc_stop_prepare(struct xe_guc *guc) 1475 { 1476 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1477 int err; 1478 1479 err = xe_guc_pc_stop(&guc->pc); 1480 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1481 ERR_PTR(err)); 1482 } 1483 } 1484 1485 void xe_guc_stop(struct xe_guc *guc) 1486 { 1487 xe_guc_ct_stop(&guc->ct); 1488 1489 xe_guc_submit_stop(guc); 1490 } 1491 1492 int xe_guc_start(struct xe_guc *guc) 1493 { 1494 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1495 int err; 1496 1497 err = xe_guc_pc_start(&guc->pc); 1498 xe_gt_WARN(guc_to_gt(guc), err, "Failed to start GuC PC: %pe\n", 1499 ERR_PTR(err)); 1500 } 1501 1502 return xe_guc_submit_start(guc); 1503 } 1504 1505 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1506 { 1507 struct xe_gt *gt = guc_to_gt(guc); 1508 unsigned int fw_ref; 1509 u32 status; 1510 int i; 1511 1512 xe_uc_fw_print(&guc->fw, p); 1513 1514 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1515 if (!fw_ref) 1516 return; 1517 1518 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1519 1520 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1521 drm_printf(p, "\tBootrom status = 0x%x\n", 1522 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1523 drm_printf(p, "\tuKernel status = 0x%x\n", 1524 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1525 drm_printf(p, "\tMIA Core status = 0x%x\n", 1526 REG_FIELD_GET(GS_MIA_MASK, status)); 1527 drm_printf(p, "\tLog level = %d\n", 1528 xe_guc_log_get_level(&guc->log)); 1529 1530 drm_puts(p, "\nScratch registers:\n"); 1531 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1532 drm_printf(p, "\t%2d: \t0x%x\n", 1533 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1534 } 1535 1536 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1537 1538 drm_puts(p, "\n"); 1539 xe_guc_ct_print(&guc->ct, p, false); 1540 1541 drm_puts(p, "\n"); 1542 xe_guc_submit_print(guc, p); 1543 } 1544 1545 /** 1546 * xe_guc_declare_wedged() - Declare GuC wedged 1547 * @guc: the GuC object 1548 * 1549 * Wedge the GuC which stops all submission, saves desired debug state, and 1550 * cleans up anything which could timeout. 1551 */ 1552 void xe_guc_declare_wedged(struct xe_guc *guc) 1553 { 1554 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1555 1556 xe_guc_reset_prepare(guc); 1557 xe_guc_ct_stop(&guc->ct); 1558 xe_guc_submit_wedge(guc); 1559 } 1560