1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "abi/guc_actions_abi.h" 13 #include "abi/guc_errors_abi.h" 14 #include "regs/xe_gt_regs.h" 15 #include "regs/xe_gtt_defs.h" 16 #include "regs/xe_guc_regs.h" 17 #include "regs/xe_irq_regs.h" 18 #include "xe_bo.h" 19 #include "xe_configfs.h" 20 #include "xe_device.h" 21 #include "xe_force_wake.h" 22 #include "xe_gt.h" 23 #include "xe_gt_printk.h" 24 #include "xe_gt_sriov_vf.h" 25 #include "xe_gt_throttle.h" 26 #include "xe_guc_ads.h" 27 #include "xe_guc_buf.h" 28 #include "xe_guc_capture.h" 29 #include "xe_guc_ct.h" 30 #include "xe_guc_db_mgr.h" 31 #include "xe_guc_engine_activity.h" 32 #include "xe_guc_hwconfig.h" 33 #include "xe_guc_klv_helpers.h" 34 #include "xe_guc_log.h" 35 #include "xe_guc_pc.h" 36 #include "xe_guc_relay.h" 37 #include "xe_guc_submit.h" 38 #include "xe_memirq.h" 39 #include "xe_mmio.h" 40 #include "xe_platform_types.h" 41 #include "xe_sriov.h" 42 #include "xe_uc.h" 43 #include "xe_uc_fw.h" 44 #include "xe_wa.h" 45 #include "xe_wopcm.h" 46 47 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 48 struct xe_bo *bo) 49 { 50 struct xe_device *xe = guc_to_xe(guc); 51 u32 addr; 52 53 /* 54 * For most BOs, the address on the allocating tile is fine. However for 55 * some, e.g. G2G CTB, the address on a specific tile is required as it 56 * might be different for each tile. So, just always ask for the address 57 * on the target GuC. 58 */ 59 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 60 61 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 62 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 63 xe_assert(xe, addr < GUC_GGTT_TOP); 64 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); 65 66 return addr; 67 } 68 69 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 70 { 71 u32 level = xe_guc_log_get_level(&guc->log); 72 u32 flags = 0; 73 74 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 75 flags |= GUC_LOG_DISABLED; 76 else 77 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 78 GUC_LOG_VERBOSITY_SHIFT; 79 80 return flags; 81 } 82 83 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 84 { 85 struct xe_device *xe = guc_to_xe(guc); 86 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 87 88 if (!xe->info.skip_guc_pc) 89 flags |= GUC_CTL_ENABLE_SLPC; 90 91 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) 92 flags |= GUC_CTL_ENABLE_PSMI_LOGGING; 93 94 return flags; 95 } 96 97 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 98 { 99 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 100 u32 flags; 101 102 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 103 #define LOG_UNIT SZ_1M 104 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 105 #else 106 #define LOG_UNIT SZ_4K 107 #define LOG_FLAG 0 108 #endif 109 110 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 111 #define CAPTURE_UNIT SZ_1M 112 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 113 #else 114 #define CAPTURE_UNIT SZ_4K 115 #define CAPTURE_FLAG 0 116 #endif 117 118 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 119 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 120 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 121 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 122 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 123 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 124 125 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 126 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 127 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 128 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 129 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 130 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 131 132 flags = GUC_LOG_VALID | 133 GUC_LOG_NOTIFY_ON_HALF_FULL | 134 CAPTURE_FLAG | 135 LOG_FLAG | 136 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 137 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 138 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << 139 GUC_LOG_CAPTURE_SHIFT) | 140 (offset << GUC_LOG_BUF_ADDR_SHIFT); 141 142 #undef LOG_UNIT 143 #undef LOG_FLAG 144 #undef CAPTURE_UNIT 145 #undef CAPTURE_FLAG 146 147 return flags; 148 } 149 150 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 151 { 152 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 153 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 154 155 return flags; 156 } 157 158 static bool needs_wa_dual_queue(struct xe_gt *gt) 159 { 160 /* 161 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 162 * on RCS and CCSes with different address spaces, which on DG2 is 163 * required as a WA for an HW bug. 164 */ 165 if (XE_GT_WA(gt, 22011391025)) 166 return true; 167 168 /* 169 * On newer platforms, the HW has been updated to not allow parallel 170 * execution of different address spaces, so the RCS/CCS will stall the 171 * context switch if one of the other RCS/CCSes is busy with a different 172 * address space. While functionally correct, having a submission 173 * stalled on the HW limits the GuC ability to shuffle things around and 174 * can cause complications if the non-stalled submission runs for a long 175 * time, because the GuC doesn't know that the stalled submission isn't 176 * actually running and might declare it as hung. Therefore, we enable 177 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 178 * to move management back to the GuC. 179 */ 180 if (CCS_MASK(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 181 return true; 182 183 return false; 184 } 185 186 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 187 { 188 struct xe_device *xe = guc_to_xe(guc); 189 struct xe_gt *gt = guc_to_gt(guc); 190 u32 flags = 0; 191 192 if (XE_GT_WA(gt, 22012773006)) 193 flags |= GUC_WA_POLLCS; 194 195 if (XE_GT_WA(gt, 14014475959)) 196 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 197 198 if (needs_wa_dual_queue(gt)) 199 flags |= GUC_WA_DUAL_QUEUE; 200 201 /* 202 * Wa_22011802037: FIXME - there's more to be done than simply setting 203 * this flag: make sure each CS is stopped when preparing for GT reset 204 * and wait for pending MI_FW. 205 */ 206 if (GRAPHICS_VERx100(xe) < 1270) 207 flags |= GUC_WA_PRE_PARSER; 208 209 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) 210 flags |= GUC_WA_CONTEXT_ISOLATION; 211 212 if (XE_GT_WA(gt, 18020744125) && 213 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 214 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 215 216 if (XE_GT_WA(gt, 1509372804)) 217 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 218 219 if (XE_GT_WA(gt, 14018913170)) 220 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 221 222 if (XE_GT_WA(gt, 16023683509)) 223 flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6; 224 225 return flags; 226 } 227 228 static u32 guc_ctl_devid(struct xe_guc *guc) 229 { 230 struct xe_device *xe = guc_to_xe(guc); 231 232 return (((u32)xe->info.devid) << 16) | xe->info.revid; 233 } 234 235 static void guc_print_params(struct xe_guc *guc) 236 { 237 struct xe_gt *gt = guc_to_gt(guc); 238 u32 *params = guc->params; 239 int i; 240 241 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 242 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 243 244 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 245 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 246 } 247 248 static void guc_init_params(struct xe_guc *guc) 249 { 250 u32 *params = guc->params; 251 252 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 253 params[GUC_CTL_FEATURE] = 0; 254 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 255 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 256 params[GUC_CTL_WA] = 0; 257 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 258 259 guc_print_params(guc); 260 } 261 262 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 263 { 264 u32 *params = guc->params; 265 266 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 267 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 268 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 269 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 270 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 271 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 272 273 guc_print_params(guc); 274 } 275 276 /* 277 * Initialize the GuC parameter block before starting the firmware 278 * transfer. These parameters are read by the firmware on startup 279 * and cannot be changed thereafter. 280 */ 281 static void guc_write_params(struct xe_guc *guc) 282 { 283 struct xe_gt *gt = guc_to_gt(guc); 284 int i; 285 286 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 287 288 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 289 290 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 291 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 292 } 293 294 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 295 u32 desc_addr, u32 buff_addr, u32 size) 296 { 297 struct xe_gt *gt = guc_to_gt(guc); 298 struct xe_device *xe = gt_to_xe(gt); 299 u32 action[] = { 300 XE_GUC_ACTION_REGISTER_G2G, 301 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 302 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 303 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 304 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 305 desc_addr, 306 buff_addr, 307 }; 308 309 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 310 xe_assert(xe, !(size % SZ_4K)); 311 312 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 313 } 314 315 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 316 { 317 struct xe_gt *gt = guc_to_gt(guc); 318 struct xe_device *xe = gt_to_xe(gt); 319 u32 action[] = { 320 XE_GUC_ACTION_DEREGISTER_G2G, 321 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 322 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 323 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 324 }; 325 326 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 327 328 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 329 } 330 331 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 332 333 #define G2G_BUFFER_SIZE (SZ_4K) 334 #define G2G_DESC_SIZE (64) 335 #define G2G_DESC_AREA_SIZE (SZ_4K) 336 337 /* 338 * Generate a unique id for each bi-directional CTB for each pair of 339 * near and far tiles/devices. The id can then be used as an index into 340 * a single allocation that is sub-divided into multiple CTBs. 341 * 342 * For example, with two devices per tile and two tiles, the table should 343 * look like: 344 * Far <tile>.<dev> 345 * 0.0 0.1 1.0 1.1 346 * N 0.0 --/-- 00/01 02/03 04/05 347 * e 0.1 01/00 --/-- 06/07 08/09 348 * a 1.0 03/02 07/06 --/-- 10/11 349 * r 1.1 05/04 09/08 11/10 --/-- 350 * 351 * Where each entry is Rx/Tx channel id. 352 * 353 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 354 * be reading from channel #11 and writing to channel #10. Whereas, 355 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 356 */ 357 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 358 u32 type, u32 max_inst, bool have_dev) 359 { 360 u32 near = near_tile, far = far_tile; 361 u32 idx = 0, x, y, direction; 362 int i; 363 364 if (have_dev) { 365 near = (near << 1) | near_dev; 366 far = (far << 1) | far_dev; 367 } 368 369 /* No need to send to one's self */ 370 if (far == near) 371 return -1; 372 373 if (far > near) { 374 /* Top right table half */ 375 x = far; 376 y = near; 377 378 /* T/R is 'forwards' direction */ 379 direction = type; 380 } else { 381 /* Bottom left table half */ 382 x = near; 383 y = far; 384 385 /* B/L is 'backwards' direction */ 386 direction = (1 - type); 387 } 388 389 /* Count the rows prior to the target */ 390 for (i = y; i > 0; i--) 391 idx += max_inst - i; 392 393 /* Count this row up to the target */ 394 idx += (x - 1 - y); 395 396 /* Slots are in Rx/Tx pairs */ 397 idx *= 2; 398 399 /* Pick Rx/Tx direction */ 400 idx += direction; 401 402 return idx; 403 } 404 405 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 406 { 407 struct xe_gt *near_gt = guc_to_gt(near_guc); 408 struct xe_device *xe = gt_to_xe(near_gt); 409 struct xe_bo *g2g_bo; 410 u32 near_tile = gt_to_tile(near_gt)->id; 411 u32 near_dev = G2G_DEV(near_gt); 412 u32 far_tile = gt_to_tile(far_gt)->id; 413 u32 far_dev = G2G_DEV(far_gt); 414 u32 max = xe->info.gt_count; 415 u32 base, desc, buf; 416 int slot; 417 418 /* G2G is not allowed between different cards */ 419 xe_assert(xe, xe == gt_to_xe(far_gt)); 420 421 g2g_bo = near_guc->g2g.bo; 422 xe_assert(xe, g2g_bo); 423 424 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 425 xe_assert(xe, slot >= 0); 426 427 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 428 desc = base + slot * G2G_DESC_SIZE; 429 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 430 431 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 432 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(g2g_bo)); 433 434 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 435 desc, buf, G2G_BUFFER_SIZE); 436 } 437 438 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 439 { 440 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 441 } 442 443 static u32 guc_g2g_size(struct xe_guc *guc) 444 { 445 struct xe_gt *gt = guc_to_gt(guc); 446 struct xe_device *xe = gt_to_xe(gt); 447 unsigned int count = xe->info.gt_count; 448 u32 num_channels = (count * (count - 1)) / 2; 449 450 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 451 452 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 453 } 454 455 static bool xe_guc_g2g_wanted(struct xe_device *xe) 456 { 457 /* Can't do GuC to GuC communication if there is only one GuC */ 458 if (xe->info.gt_count <= 1) 459 return false; 460 461 /* No current user */ 462 return false; 463 } 464 465 static int guc_g2g_alloc(struct xe_guc *guc) 466 { 467 struct xe_gt *gt = guc_to_gt(guc); 468 struct xe_device *xe = gt_to_xe(gt); 469 struct xe_tile *tile = gt_to_tile(gt); 470 struct xe_bo *bo; 471 u32 g2g_size; 472 473 if (guc->g2g.bo) 474 return 0; 475 476 if (gt->info.id != 0) { 477 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 478 struct xe_guc *root_guc = &root_gt->uc.guc; 479 struct xe_bo *bo; 480 481 bo = xe_bo_get(root_guc->g2g.bo); 482 if (!bo) 483 return -ENODEV; 484 485 guc->g2g.bo = bo; 486 guc->g2g.owned = false; 487 return 0; 488 } 489 490 g2g_size = guc_g2g_size(guc); 491 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 492 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 493 XE_BO_FLAG_GGTT | 494 XE_BO_FLAG_GGTT_ALL | 495 XE_BO_FLAG_GGTT_INVALIDATE | 496 XE_BO_FLAG_PINNED_NORESTORE); 497 if (IS_ERR(bo)) 498 return PTR_ERR(bo); 499 500 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 501 guc->g2g.bo = bo; 502 guc->g2g.owned = true; 503 504 return 0; 505 } 506 507 static void guc_g2g_fini(struct xe_guc *guc) 508 { 509 if (!guc->g2g.bo) 510 return; 511 512 /* Unpinning the owned object is handled by generic shutdown */ 513 if (!guc->g2g.owned) 514 xe_bo_put(guc->g2g.bo); 515 516 guc->g2g.bo = NULL; 517 } 518 519 static int guc_g2g_start(struct xe_guc *guc) 520 { 521 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 522 struct xe_device *xe = gt_to_xe(gt); 523 unsigned int i, j; 524 int t, err; 525 bool have_dev; 526 527 if (!guc->g2g.bo) { 528 int ret; 529 530 ret = guc_g2g_alloc(guc); 531 if (ret) 532 return ret; 533 } 534 535 /* GuC interface will need extending if more GT device types are ever created. */ 536 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 537 538 /* Channel numbering depends on whether there are multiple GTs per tile */ 539 have_dev = xe->info.gt_count > xe->info.tile_count; 540 541 for_each_gt(far_gt, xe, i) { 542 u32 far_tile, far_dev; 543 544 if (far_gt->info.id == gt->info.id) 545 continue; 546 547 far_tile = gt_to_tile(far_gt)->id; 548 far_dev = G2G_DEV(far_gt); 549 550 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 551 err = guc_g2g_register(guc, far_gt, t, have_dev); 552 if (err) { 553 while (--t >= 0) 554 guc_g2g_deregister(guc, far_tile, far_dev, t); 555 goto err_deregister; 556 } 557 } 558 } 559 560 return 0; 561 562 err_deregister: 563 for_each_gt(far_gt, xe, j) { 564 u32 tile, dev; 565 566 if (far_gt->info.id == gt->info.id) 567 continue; 568 569 if (j >= i) 570 break; 571 572 tile = gt_to_tile(far_gt)->id; 573 dev = G2G_DEV(far_gt); 574 575 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 576 guc_g2g_deregister(guc, tile, dev, t); 577 } 578 579 return err; 580 } 581 582 static int __guc_opt_in_features_enable(struct xe_guc *guc, u64 addr, u32 num_dwords) 583 { 584 u32 action[] = { 585 XE_GUC_ACTION_OPT_IN_FEATURE_KLV, 586 lower_32_bits(addr), 587 upper_32_bits(addr), 588 num_dwords 589 }; 590 591 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 592 } 593 594 static bool supports_dynamic_ics(struct xe_guc *guc) 595 { 596 struct xe_device *xe = guc_to_xe(guc); 597 struct xe_gt *gt = guc_to_gt(guc); 598 599 /* Dynamic ICS is available for PVC and Xe2 and newer platforms. */ 600 if (xe->info.platform != XE_PVC && GRAPHICS_VER(xe) < 20) 601 return false; 602 603 /* 604 * The feature is currently not compatible with multi-lrc, so the GuC 605 * does not support it at all on the media engines (which are the main 606 * users of mlrc). On the primary GT side, to avoid it being used in 607 * conjunction with mlrc, we only enable it if we are in single CCS 608 * mode. 609 */ 610 if (xe_gt_is_media_type(gt) || gt->ccs_mode > 1) 611 return false; 612 613 /* 614 * Dynamic ICS requires GuC v70.40.1, which maps to compatibility 615 * version v1.18.4. 616 */ 617 return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 4); 618 } 619 620 #define OPT_IN_MAX_DWORDS 16 621 int xe_guc_opt_in_features_enable(struct xe_guc *guc) 622 { 623 struct xe_device *xe = guc_to_xe(guc); 624 CLASS(xe_guc_buf, buf)(&guc->buf, OPT_IN_MAX_DWORDS); 625 u32 count = 0; 626 u32 *klvs; 627 int ret; 628 629 if (!xe_guc_buf_is_valid(buf)) 630 return -ENOBUFS; 631 632 klvs = xe_guc_buf_cpu_ptr(buf); 633 634 /* 635 * The extra CAT error type opt-in was added in GuC v70.17.0, which maps 636 * to compatibility version v1.7.0. 637 * Note that the GuC allows enabling this KLV even on platforms that do 638 * not support the extra type; in such case the returned type variable 639 * will be set to a known invalid value which we can check against. 640 */ 641 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 7, 0)) 642 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_EXT_CAT_ERR_TYPE); 643 644 if (supports_dynamic_ics(guc)) 645 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH); 646 647 if (count) { 648 xe_assert(xe, count <= OPT_IN_MAX_DWORDS); 649 650 ret = __guc_opt_in_features_enable(guc, xe_guc_buf_flush(buf), count); 651 if (ret < 0) { 652 xe_gt_err(guc_to_gt(guc), 653 "failed to enable GuC opt-in features: %pe\n", 654 ERR_PTR(ret)); 655 return ret; 656 } 657 } 658 659 return 0; 660 } 661 662 static void guc_fini_hw(void *arg) 663 { 664 struct xe_guc *guc = arg; 665 struct xe_gt *gt = guc_to_gt(guc); 666 unsigned int fw_ref; 667 668 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL); 669 xe_uc_sanitize_reset(&guc_to_gt(guc)->uc); 670 xe_force_wake_put(gt_to_fw(gt), fw_ref); 671 672 guc_g2g_fini(guc); 673 } 674 675 /** 676 * xe_guc_comm_init_early - early initialization of GuC communication 677 * @guc: the &xe_guc to initialize 678 * 679 * Must be called prior to first MMIO communication with GuC firmware. 680 */ 681 void xe_guc_comm_init_early(struct xe_guc *guc) 682 { 683 struct xe_gt *gt = guc_to_gt(guc); 684 685 if (xe_gt_is_media_type(gt)) 686 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 687 else 688 guc->notify_reg = GUC_HOST_INTERRUPT; 689 } 690 691 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 692 { 693 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 694 struct xe_device *xe = guc_to_xe(guc); 695 int ret; 696 697 if (!IS_DGFX(guc_to_xe(guc))) 698 return 0; 699 700 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 701 if (ret) 702 return ret; 703 704 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 705 if (ret) 706 return ret; 707 708 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 709 if (ret) 710 return ret; 711 712 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo); 713 if (ret) 714 return ret; 715 716 return 0; 717 } 718 719 static int vf_guc_init_noalloc(struct xe_guc *guc) 720 { 721 struct xe_gt *gt = guc_to_gt(guc); 722 int err; 723 724 err = xe_gt_sriov_vf_bootstrap(gt); 725 if (err) 726 return err; 727 728 err = xe_gt_sriov_vf_query_config(gt); 729 if (err) 730 return err; 731 732 return 0; 733 } 734 735 int xe_guc_init_noalloc(struct xe_guc *guc) 736 { 737 struct xe_device *xe = guc_to_xe(guc); 738 struct xe_gt *gt = guc_to_gt(guc); 739 int ret; 740 741 xe_guc_comm_init_early(guc); 742 743 ret = xe_guc_ct_init_noalloc(&guc->ct); 744 if (ret) 745 goto out; 746 747 ret = xe_guc_relay_init(&guc->relay); 748 if (ret) 749 goto out; 750 751 if (IS_SRIOV_VF(xe)) { 752 ret = vf_guc_init_noalloc(guc); 753 if (ret) 754 goto out; 755 } 756 757 return 0; 758 759 out: 760 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 761 return ret; 762 } 763 764 int xe_guc_init(struct xe_guc *guc) 765 { 766 struct xe_device *xe = guc_to_xe(guc); 767 struct xe_gt *gt = guc_to_gt(guc); 768 int ret; 769 770 guc->fw.type = XE_UC_FW_TYPE_GUC; 771 ret = xe_uc_fw_init(&guc->fw); 772 if (ret) 773 return ret; 774 775 if (!xe_uc_fw_is_enabled(&guc->fw)) 776 return 0; 777 778 if (IS_SRIOV_VF(xe)) { 779 ret = xe_guc_ct_init(&guc->ct); 780 if (ret) 781 goto out; 782 return 0; 783 } 784 785 ret = xe_guc_log_init(&guc->log); 786 if (ret) 787 goto out; 788 789 ret = xe_guc_capture_init(guc); 790 if (ret) 791 goto out; 792 793 ret = xe_guc_ads_init(&guc->ads); 794 if (ret) 795 goto out; 796 797 ret = xe_guc_ct_init(&guc->ct); 798 if (ret) 799 goto out; 800 801 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 802 803 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 804 if (ret) 805 goto out; 806 807 guc_init_params(guc); 808 809 return 0; 810 811 out: 812 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 813 return ret; 814 } 815 816 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 817 { 818 int err; 819 820 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 821 if (err) 822 return err; 823 824 err = xe_guc_buf_cache_init(&guc->buf); 825 if (err) 826 return err; 827 828 /* XXX xe_guc_db_mgr_init not needed for now */ 829 830 return 0; 831 } 832 833 /** 834 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 835 * @guc: The GuC object 836 * 837 * Return: 0 on success, negative error code on error. 838 */ 839 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 840 { 841 int ret; 842 843 if (IS_SRIOV_VF(guc_to_xe(guc))) 844 return vf_guc_init_post_hwconfig(guc); 845 846 ret = xe_guc_realloc_post_hwconfig(guc); 847 if (ret) 848 return ret; 849 850 guc_init_params_post_hwconfig(guc); 851 852 ret = xe_guc_submit_init(guc, ~0); 853 if (ret) 854 return ret; 855 856 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 857 if (ret) 858 return ret; 859 860 ret = xe_guc_pc_init(&guc->pc); 861 if (ret) 862 return ret; 863 864 ret = xe_guc_engine_activity_init(guc); 865 if (ret) 866 return ret; 867 868 ret = xe_guc_buf_cache_init(&guc->buf); 869 if (ret) 870 return ret; 871 872 return xe_guc_ads_init_post_hwconfig(&guc->ads); 873 } 874 875 int xe_guc_post_load_init(struct xe_guc *guc) 876 { 877 int ret; 878 879 xe_guc_ads_populate_post_load(&guc->ads); 880 881 ret = xe_guc_opt_in_features_enable(guc); 882 if (ret) 883 return ret; 884 885 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 886 ret = guc_g2g_start(guc); 887 if (ret) 888 return ret; 889 } 890 891 guc->submission_state.enabled = true; 892 893 return 0; 894 } 895 896 int xe_guc_reset(struct xe_guc *guc) 897 { 898 struct xe_gt *gt = guc_to_gt(guc); 899 struct xe_mmio *mmio = >->mmio; 900 u32 guc_status, gdrst; 901 int ret; 902 903 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 904 905 if (IS_SRIOV_VF(gt_to_xe(gt))) 906 return xe_gt_sriov_vf_bootstrap(gt); 907 908 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 909 910 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 911 if (ret) { 912 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 913 goto err_out; 914 } 915 916 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 917 if (!(guc_status & GS_MIA_IN_RESET)) { 918 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 919 guc_status); 920 ret = -EIO; 921 goto err_out; 922 } 923 924 return 0; 925 926 err_out: 927 928 return ret; 929 } 930 931 static void guc_prepare_xfer(struct xe_guc *guc) 932 { 933 struct xe_gt *gt = guc_to_gt(guc); 934 struct xe_mmio *mmio = >->mmio; 935 struct xe_device *xe = guc_to_xe(guc); 936 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 937 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 938 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 939 GUC_ENABLE_MIA_CLOCK_GATING; 940 941 if (GRAPHICS_VERx100(xe) < 1250) 942 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 943 GUC_ENABLE_MIA_CACHING; 944 945 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 946 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 947 948 /* Must program this register before loading the ucode with DMA */ 949 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 950 951 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 952 953 /* Make sure GuC receives ARAT interrupts */ 954 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 955 } 956 957 /* 958 * Supporting MMIO & in memory RSA 959 */ 960 static int guc_xfer_rsa(struct xe_guc *guc) 961 { 962 struct xe_gt *gt = guc_to_gt(guc); 963 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 964 size_t copied; 965 int i; 966 967 if (guc->fw.rsa_size > 256) { 968 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 969 xe_uc_fw_rsa_offset(&guc->fw); 970 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 971 return 0; 972 } 973 974 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 975 if (copied < sizeof(rsa)) 976 return -ENOMEM; 977 978 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 979 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 980 981 return 0; 982 } 983 984 /* 985 * Check a previously read GuC status register (GUC_STATUS) looking for 986 * known terminal states (either completion or failure) of either the 987 * microkernel status field or the boot ROM status field. Returns +1 for 988 * successful completion, -1 for failure and 0 for any intermediate state. 989 */ 990 static int guc_load_done(u32 status) 991 { 992 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); 993 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); 994 995 switch (uk_val) { 996 case XE_GUC_LOAD_STATUS_READY: 997 return 1; 998 999 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 1000 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 1001 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 1002 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 1003 case XE_GUC_LOAD_STATUS_BOOTROM_VERSION_MISMATCH: 1004 case XE_GUC_LOAD_STATUS_DPC_ERROR: 1005 case XE_GUC_LOAD_STATUS_EXCEPTION: 1006 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1007 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 1008 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1009 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1010 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1011 return -1; 1012 } 1013 1014 switch (br_val) { 1015 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1016 case XE_BOOTROM_STATUS_RSA_FAILED: 1017 case XE_BOOTROM_STATUS_PAVPC_FAILED: 1018 case XE_BOOTROM_STATUS_WOPCM_FAILED: 1019 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 1020 case XE_BOOTROM_STATUS_JUMP_FAILED: 1021 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 1022 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 1023 case XE_BOOTROM_STATUS_EXCEPTION: 1024 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1025 return -1; 1026 } 1027 1028 return 0; 1029 } 1030 1031 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) 1032 { 1033 u32 freq; 1034 int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq); 1035 1036 return ret ? ret : freq; 1037 } 1038 1039 /* 1040 * Wait for the GuC to start up. 1041 * 1042 * Measurements indicate this should take no more than 20ms (assuming the GT 1043 * clock is at maximum frequency). However, thermal throttling and other issues 1044 * can prevent the clock hitting max and thus making the load take significantly 1045 * longer. Allow up to 200ms as a safety margin for real world worst case situations. 1046 * 1047 * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can 1048 * lead to even longer times. E.g. if the GT is clamped to minimum frequency then 1049 * the load times can be in the seconds range. So the timeout is increased for debug 1050 * builds to ensure that problems can be correctly analysed. For release builds, the 1051 * timeout is kept short so that users don't wait forever to find out that there is a 1052 * problem. In either case, if the load took longer than is reasonable even with some 1053 * 'sensible' throttling, then flag a warning because something is not right. 1054 * 1055 * Note that there is a limit on how long an individual usleep_range() can wait for, 1056 * hence longer waits require wrapping a shorter wait in a loop. 1057 * 1058 * Note that the only reason an end user should hit the shorter timeout is in case of 1059 * extreme thermal throttling. And a system that is that hot during boot is probably 1060 * dead anyway! 1061 */ 1062 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 1063 #define GUC_LOAD_RETRY_LIMIT 20 1064 #else 1065 #define GUC_LOAD_RETRY_LIMIT 3 1066 #endif 1067 #define GUC_LOAD_TIME_WARN_MS 200 1068 1069 static void guc_wait_ucode(struct xe_guc *guc) 1070 { 1071 struct xe_gt *gt = guc_to_gt(guc); 1072 struct xe_mmio *mmio = >->mmio; 1073 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1074 ktime_t before, after, delta; 1075 int load_done; 1076 u32 status = 0; 1077 int count = 0; 1078 u64 delta_ms; 1079 u32 before_freq; 1080 1081 before_freq = xe_guc_pc_get_act_freq(guc_pc); 1082 before = ktime_get(); 1083 /* 1084 * Note, can't use any kind of timing information from the call to xe_mmio_wait. 1085 * It could return a thousand intermediate stages at random times. Instead, must 1086 * manually track the total time taken and locally implement the timeout. 1087 */ 1088 do { 1089 u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK); 1090 int ret; 1091 1092 /* 1093 * Wait for any change (intermediate or terminal) in the status register. 1094 * Note, the return value is a don't care. The only failure code is timeout 1095 * but the timeouts need to be accumulated over all the intermediate partial 1096 * timeouts rather than allowing a huge timeout each time. So basically, need 1097 * to treat a timeout no different to a value change. 1098 */ 1099 ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK, 1100 last_status, 1000 * 1000, &status, false); 1101 if (ret < 0) 1102 count++; 1103 after = ktime_get(); 1104 delta = ktime_sub(after, before); 1105 delta_ms = ktime_to_ms(delta); 1106 1107 load_done = guc_load_done(status); 1108 if (load_done != 0) 1109 break; 1110 1111 if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000)) 1112 break; 1113 1114 xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 1115 count, xe_guc_pc_get_act_freq(guc_pc), 1116 guc_pc_get_cur_freq(guc_pc), status, 1117 REG_FIELD_GET(GS_BOOTROM_MASK, status), 1118 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1119 } while (1); 1120 1121 if (load_done != 1) { 1122 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1123 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1124 1125 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n", 1126 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1127 guc_pc_get_cur_freq(guc_pc), load_done); 1128 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1129 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1130 bootrom, ukernel, 1131 REG_FIELD_GET(GS_MIA_MASK, status), 1132 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1133 1134 switch (bootrom) { 1135 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1136 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1137 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1138 break; 1139 1140 case XE_BOOTROM_STATUS_RSA_FAILED: 1141 xe_gt_err(gt, "firmware signature verification failed\n"); 1142 break; 1143 1144 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1145 xe_gt_err(gt, "firmware production part check failure\n"); 1146 break; 1147 } 1148 1149 switch (ukernel) { 1150 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1151 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1152 break; 1153 1154 case XE_GUC_LOAD_STATUS_EXCEPTION: 1155 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1156 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1157 break; 1158 1159 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1160 xe_gt_err(gt, "illegal init/ADS data\n"); 1161 break; 1162 1163 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1164 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1165 break; 1166 1167 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1168 xe_gt_err(gt, "illegal workaround KLV data\n"); 1169 break; 1170 1171 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1172 xe_gt_err(gt, "illegal feature flag specified\n"); 1173 break; 1174 } 1175 1176 xe_device_declare_wedged(gt_to_xe(gt)); 1177 } else if (delta_ms > GUC_LOAD_TIME_WARN_MS) { 1178 xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n", 1179 delta_ms, status, count); 1180 xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1181 xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1182 before_freq, xe_gt_throttle_get_limit_reasons(gt)); 1183 } else { 1184 xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n", 1185 delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 1186 before_freq, status, count); 1187 } 1188 } 1189 1190 static int __xe_guc_upload(struct xe_guc *guc) 1191 { 1192 int ret; 1193 1194 /* Raise GT freq to speed up HuC/GuC load */ 1195 xe_guc_pc_raise_unslice(&guc->pc); 1196 1197 guc_write_params(guc); 1198 guc_prepare_xfer(guc); 1199 1200 /* 1201 * Note that GuC needs the CSS header plus uKernel code to be copied 1202 * by the DMA engine in one operation, whereas the RSA signature is 1203 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1204 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1205 * size > 256). The RSA size and therefore the way we provide it to the 1206 * HW is fixed for each platform and hard-coded in the bootrom. 1207 */ 1208 ret = guc_xfer_rsa(guc); 1209 if (ret) 1210 goto out; 1211 /* 1212 * Current uCode expects the code to be loaded at 8k; locations below 1213 * this are used for the stack. 1214 */ 1215 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1216 if (ret) 1217 goto out; 1218 1219 /* Wait for authentication */ 1220 guc_wait_ucode(guc); 1221 1222 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1223 return 0; 1224 1225 out: 1226 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1227 return 0 /* FIXME: ret, don't want to stop load currently */; 1228 } 1229 1230 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1231 { 1232 struct xe_gt *gt = guc_to_gt(guc); 1233 int ret; 1234 1235 ret = xe_guc_hwconfig_init(guc); 1236 if (ret) 1237 return ret; 1238 1239 ret = xe_guc_enable_communication(guc); 1240 if (ret) 1241 return ret; 1242 1243 ret = xe_gt_sriov_vf_connect(gt); 1244 if (ret) 1245 goto err_out; 1246 1247 ret = xe_gt_sriov_vf_query_runtime(gt); 1248 if (ret) 1249 goto err_out; 1250 1251 return 0; 1252 1253 err_out: 1254 xe_guc_sanitize(guc); 1255 return ret; 1256 } 1257 1258 /** 1259 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1260 * @guc: The GuC object 1261 * 1262 * This function uploads a minimal GuC that does not support submissions but 1263 * in a state where the hwconfig table can be read. Next, it reads and parses 1264 * the hwconfig table so it can be used for subsequent steps in the driver load. 1265 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1266 * 1267 * Return: 0 on success, negative error code on error. 1268 */ 1269 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1270 { 1271 int ret; 1272 1273 if (IS_SRIOV_VF(guc_to_xe(guc))) 1274 return vf_guc_min_load_for_hwconfig(guc); 1275 1276 xe_guc_ads_populate_minimal(&guc->ads); 1277 1278 xe_guc_pc_init_early(&guc->pc); 1279 1280 ret = __xe_guc_upload(guc); 1281 if (ret) 1282 return ret; 1283 1284 ret = xe_guc_hwconfig_init(guc); 1285 if (ret) 1286 return ret; 1287 1288 ret = xe_guc_enable_communication(guc); 1289 if (ret) 1290 return ret; 1291 1292 return 0; 1293 } 1294 1295 int xe_guc_upload(struct xe_guc *guc) 1296 { 1297 xe_guc_ads_populate(&guc->ads); 1298 1299 return __xe_guc_upload(guc); 1300 } 1301 1302 static void guc_handle_mmio_msg(struct xe_guc *guc) 1303 { 1304 struct xe_gt *gt = guc_to_gt(guc); 1305 u32 msg; 1306 1307 if (IS_SRIOV_VF(guc_to_xe(guc))) 1308 return; 1309 1310 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1311 1312 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1313 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1314 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1315 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1316 1317 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1318 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1319 1320 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1321 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1322 } 1323 1324 static void guc_enable_irq(struct xe_guc *guc) 1325 { 1326 struct xe_gt *gt = guc_to_gt(guc); 1327 u32 events = xe_gt_is_media_type(gt) ? 1328 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1329 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1330 1331 /* Primary GuC and media GuC share a single enable bit */ 1332 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1333 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1334 1335 /* 1336 * There are separate mask bits for primary and media GuCs, so use 1337 * a RMW operation to avoid clobbering the other GuC's setting. 1338 */ 1339 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1340 } 1341 1342 int xe_guc_enable_communication(struct xe_guc *guc) 1343 { 1344 struct xe_device *xe = guc_to_xe(guc); 1345 int err; 1346 1347 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1348 struct xe_gt *gt = guc_to_gt(guc); 1349 struct xe_tile *tile = gt_to_tile(gt); 1350 1351 err = xe_memirq_init_guc(&tile->memirq, guc); 1352 if (err) 1353 return err; 1354 } else { 1355 guc_enable_irq(guc); 1356 } 1357 1358 err = xe_guc_ct_enable(&guc->ct); 1359 if (err) 1360 return err; 1361 1362 guc_handle_mmio_msg(guc); 1363 1364 return 0; 1365 } 1366 1367 int xe_guc_suspend(struct xe_guc *guc) 1368 { 1369 struct xe_gt *gt = guc_to_gt(guc); 1370 u32 action[] = { 1371 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1372 }; 1373 int ret; 1374 1375 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1376 if (ret) { 1377 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1378 return ret; 1379 } 1380 1381 xe_guc_sanitize(guc); 1382 return 0; 1383 } 1384 1385 void xe_guc_notify(struct xe_guc *guc) 1386 { 1387 struct xe_gt *gt = guc_to_gt(guc); 1388 const u32 default_notify_data = 0; 1389 1390 /* 1391 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1392 * additional payload data to the GuC but this capability is not 1393 * used by the firmware yet. Use default value in the meantime. 1394 */ 1395 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1396 } 1397 1398 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1399 { 1400 u32 action[] = { 1401 XE_GUC_ACTION_AUTHENTICATE_HUC, 1402 rsa_addr 1403 }; 1404 1405 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1406 } 1407 1408 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1409 u32 len, u32 *response_buf) 1410 { 1411 struct xe_device *xe = guc_to_xe(guc); 1412 struct xe_gt *gt = guc_to_gt(guc); 1413 struct xe_mmio *mmio = >->mmio; 1414 u32 header, reply; 1415 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1416 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1417 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1418 bool lost = false; 1419 int ret; 1420 int i; 1421 1422 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1423 1424 xe_assert(xe, len); 1425 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1426 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1427 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1428 GUC_HXG_ORIGIN_HOST); 1429 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1430 GUC_HXG_TYPE_REQUEST); 1431 1432 retry: 1433 /* Not in critical data-path, just do if else for GT type */ 1434 if (xe_gt_is_media_type(gt)) { 1435 for (i = 0; i < len; ++i) 1436 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1437 request[i]); 1438 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1439 } else { 1440 for (i = 0; i < len; ++i) 1441 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1442 request[i]); 1443 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1444 } 1445 1446 xe_guc_notify(guc); 1447 1448 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1449 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1450 50000, &reply, false); 1451 if (ret) { 1452 /* scratch registers might be cleared during FLR, try once more */ 1453 if (!reply && !lost) { 1454 xe_gt_dbg(gt, "GuC mmio request %#x: lost, trying again\n", request[0]); 1455 lost = true; 1456 goto retry; 1457 } 1458 timeout: 1459 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1460 request[0], reply); 1461 return ret; 1462 } 1463 1464 header = xe_mmio_read32(mmio, reply_reg); 1465 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1466 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1467 /* 1468 * Once we got a BUSY reply we must wait again for the final 1469 * response but this time we can't use ORIGIN mask anymore. 1470 * To spot a right change in the reply, we take advantage that 1471 * response SUCCESS and FAILURE differ only by the single bit 1472 * and all other bits are set and can be used as a new mask. 1473 */ 1474 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1475 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1476 1477 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1478 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1479 1480 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1481 1000000, &header, false); 1482 1483 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1484 GUC_HXG_ORIGIN_GUC)) 1485 goto proto; 1486 if (unlikely(ret)) { 1487 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1488 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1489 goto proto; 1490 goto timeout; 1491 } 1492 } 1493 1494 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1495 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1496 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1497 1498 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1499 request[0], reason); 1500 goto retry; 1501 } 1502 1503 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1504 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1505 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1506 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1507 1508 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1509 request[0], error, hint); 1510 return -ENXIO; 1511 } 1512 1513 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1514 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1515 proto: 1516 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1517 request[0], header); 1518 return -EPROTO; 1519 } 1520 1521 /* Just copy entire possible message response */ 1522 if (response_buf) { 1523 response_buf[0] = header; 1524 1525 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1526 reply_reg.addr += sizeof(u32); 1527 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1528 } 1529 } 1530 1531 /* Use data from the GuC response as our return value */ 1532 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1533 } 1534 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1535 1536 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1537 { 1538 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1539 } 1540 1541 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1542 { 1543 struct xe_device *xe = guc_to_xe(guc); 1544 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1545 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1546 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1547 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1548 GUC_ACTION_HOST2GUC_SELF_CFG), 1549 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1550 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1551 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1552 lower_32_bits(val)), 1553 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1554 upper_32_bits(val)), 1555 }; 1556 int ret; 1557 1558 xe_assert(xe, len <= 2); 1559 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1560 1561 /* Self config must go over MMIO */ 1562 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1563 1564 if (unlikely(ret < 0)) 1565 return ret; 1566 if (unlikely(ret > 1)) 1567 return -EPROTO; 1568 if (unlikely(!ret)) 1569 return -ENOKEY; 1570 1571 return 0; 1572 } 1573 1574 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1575 { 1576 return guc_self_cfg(guc, key, 1, val); 1577 } 1578 1579 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1580 { 1581 return guc_self_cfg(guc, key, 2, val); 1582 } 1583 1584 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1585 { 1586 struct xe_gt *gt = guc_to_gt(guc); 1587 1588 if (IS_SRIOV_VF(gt_to_xe(gt))) 1589 xe_gt_sriov_vf_migrated_event_handler(gt); 1590 } 1591 1592 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1593 { 1594 if (iir & GUC_INTR_GUC2HOST) 1595 xe_guc_ct_irq_handler(&guc->ct); 1596 1597 if (iir & GUC_INTR_SW_INT_0) 1598 xe_guc_sw_0_irq_handler(guc); 1599 } 1600 1601 void xe_guc_sanitize(struct xe_guc *guc) 1602 { 1603 xe_uc_fw_sanitize(&guc->fw); 1604 xe_guc_ct_disable(&guc->ct); 1605 guc->submission_state.enabled = false; 1606 } 1607 1608 int xe_guc_reset_prepare(struct xe_guc *guc) 1609 { 1610 return xe_guc_submit_reset_prepare(guc); 1611 } 1612 1613 void xe_guc_reset_wait(struct xe_guc *guc) 1614 { 1615 xe_guc_submit_reset_wait(guc); 1616 } 1617 1618 void xe_guc_stop_prepare(struct xe_guc *guc) 1619 { 1620 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1621 int err; 1622 1623 err = xe_guc_pc_stop(&guc->pc); 1624 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1625 ERR_PTR(err)); 1626 } 1627 } 1628 1629 void xe_guc_stop(struct xe_guc *guc) 1630 { 1631 xe_guc_ct_stop(&guc->ct); 1632 1633 xe_guc_submit_stop(guc); 1634 } 1635 1636 int xe_guc_start(struct xe_guc *guc) 1637 { 1638 return xe_guc_submit_start(guc); 1639 } 1640 1641 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1642 { 1643 struct xe_gt *gt = guc_to_gt(guc); 1644 unsigned int fw_ref; 1645 u32 status; 1646 int i; 1647 1648 xe_uc_fw_print(&guc->fw, p); 1649 1650 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1651 fw_ref = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1652 if (!fw_ref) 1653 return; 1654 1655 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1656 1657 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1658 drm_printf(p, "\tBootrom status = 0x%x\n", 1659 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1660 drm_printf(p, "\tuKernel status = 0x%x\n", 1661 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1662 drm_printf(p, "\tMIA Core status = 0x%x\n", 1663 REG_FIELD_GET(GS_MIA_MASK, status)); 1664 drm_printf(p, "\tLog level = %d\n", 1665 xe_guc_log_get_level(&guc->log)); 1666 1667 drm_puts(p, "\nScratch registers:\n"); 1668 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1669 drm_printf(p, "\t%2d: \t0x%x\n", 1670 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1671 } 1672 1673 xe_force_wake_put(gt_to_fw(gt), fw_ref); 1674 } 1675 1676 drm_puts(p, "\n"); 1677 xe_guc_ct_print(&guc->ct, p, false); 1678 1679 drm_puts(p, "\n"); 1680 xe_guc_submit_print(guc, p); 1681 } 1682 1683 /** 1684 * xe_guc_declare_wedged() - Declare GuC wedged 1685 * @guc: the GuC object 1686 * 1687 * Wedge the GuC which stops all submission, saves desired debug state, and 1688 * cleans up anything which could timeout. 1689 */ 1690 void xe_guc_declare_wedged(struct xe_guc *guc) 1691 { 1692 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1693 1694 xe_guc_reset_prepare(guc); 1695 xe_guc_ct_stop(&guc->ct); 1696 xe_guc_submit_wedge(guc); 1697 } 1698