1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "abi/guc_actions_abi.h" 13 #include "abi/guc_errors_abi.h" 14 #include "regs/xe_gt_regs.h" 15 #include "regs/xe_gtt_defs.h" 16 #include "regs/xe_guc_regs.h" 17 #include "regs/xe_irq_regs.h" 18 #include "xe_bo.h" 19 #include "xe_device.h" 20 #include "xe_force_wake.h" 21 #include "xe_gt.h" 22 #include "xe_gt_printk.h" 23 #include "xe_gt_sriov_vf.h" 24 #include "xe_gt_throttle.h" 25 #include "xe_guc_ads.h" 26 #include "xe_guc_capture.h" 27 #include "xe_guc_ct.h" 28 #include "xe_guc_db_mgr.h" 29 #include "xe_guc_hwconfig.h" 30 #include "xe_guc_log.h" 31 #include "xe_guc_pc.h" 32 #include "xe_guc_relay.h" 33 #include "xe_guc_submit.h" 34 #include "xe_memirq.h" 35 #include "xe_mmio.h" 36 #include "xe_platform_types.h" 37 #include "xe_sriov.h" 38 #include "xe_uc.h" 39 #include "xe_uc_fw.h" 40 #include "xe_wa.h" 41 #include "xe_wopcm.h" 42 43 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 44 struct xe_bo *bo) 45 { 46 struct xe_device *xe = guc_to_xe(guc); 47 u32 addr = xe_bo_ggtt_addr(bo); 48 49 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 50 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 51 xe_assert(xe, addr < GUC_GGTT_TOP); 52 xe_assert(xe, bo->size <= GUC_GGTT_TOP - addr); 53 54 return addr; 55 } 56 57 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 58 { 59 u32 level = xe_guc_log_get_level(&guc->log); 60 u32 flags = 0; 61 62 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 63 flags |= GUC_LOG_DISABLED; 64 else 65 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 66 GUC_LOG_VERBOSITY_SHIFT; 67 68 return flags; 69 } 70 71 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 72 { 73 u32 flags = 0; 74 75 if (!guc_to_xe(guc)->info.skip_guc_pc) 76 flags |= GUC_CTL_ENABLE_SLPC; 77 78 return flags; 79 } 80 81 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 82 { 83 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 84 u32 flags; 85 86 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 87 #define LOG_UNIT SZ_1M 88 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 89 #else 90 #define LOG_UNIT SZ_4K 91 #define LOG_FLAG 0 92 #endif 93 94 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 95 #define CAPTURE_UNIT SZ_1M 96 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 97 #else 98 #define CAPTURE_UNIT SZ_4K 99 #define CAPTURE_FLAG 0 100 #endif 101 102 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 103 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 104 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 105 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 106 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 107 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 108 109 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 110 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 111 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 112 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 113 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 114 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 115 116 flags = GUC_LOG_VALID | 117 GUC_LOG_NOTIFY_ON_HALF_FULL | 118 CAPTURE_FLAG | 119 LOG_FLAG | 120 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 121 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 122 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << 123 GUC_LOG_CAPTURE_SHIFT) | 124 (offset << GUC_LOG_BUF_ADDR_SHIFT); 125 126 #undef LOG_UNIT 127 #undef LOG_FLAG 128 #undef CAPTURE_UNIT 129 #undef CAPTURE_FLAG 130 131 return flags; 132 } 133 134 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 135 { 136 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 137 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 138 139 return flags; 140 } 141 142 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 143 { 144 struct xe_device *xe = guc_to_xe(guc); 145 struct xe_gt *gt = guc_to_gt(guc); 146 u32 flags = 0; 147 148 if (XE_WA(gt, 22012773006)) 149 flags |= GUC_WA_POLLCS; 150 151 if (XE_WA(gt, 14014475959)) 152 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 153 154 if (XE_WA(gt, 22011391025)) 155 flags |= GUC_WA_DUAL_QUEUE; 156 157 /* 158 * Wa_22011802037: FIXME - there's more to be done than simply setting 159 * this flag: make sure each CS is stopped when preparing for GT reset 160 * and wait for pending MI_FW. 161 */ 162 if (GRAPHICS_VERx100(xe) < 1270) 163 flags |= GUC_WA_PRE_PARSER; 164 165 if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685)) 166 flags |= GUC_WA_CONTEXT_ISOLATION; 167 168 if (XE_WA(gt, 18020744125) && 169 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 170 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 171 172 if (XE_WA(gt, 1509372804)) 173 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 174 175 if (XE_WA(gt, 14018913170)) 176 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 177 178 return flags; 179 } 180 181 static u32 guc_ctl_devid(struct xe_guc *guc) 182 { 183 struct xe_device *xe = guc_to_xe(guc); 184 185 return (((u32)xe->info.devid) << 16) | xe->info.revid; 186 } 187 188 static void guc_print_params(struct xe_guc *guc) 189 { 190 struct xe_gt *gt = guc_to_gt(guc); 191 u32 *params = guc->params; 192 int i; 193 194 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 195 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 196 197 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 198 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 199 } 200 201 static void guc_init_params(struct xe_guc *guc) 202 { 203 u32 *params = guc->params; 204 205 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 206 params[GUC_CTL_FEATURE] = 0; 207 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 208 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 209 params[GUC_CTL_WA] = 0; 210 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 211 212 guc_print_params(guc); 213 } 214 215 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 216 { 217 u32 *params = guc->params; 218 219 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 220 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 221 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 222 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 223 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 224 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 225 226 guc_print_params(guc); 227 } 228 229 /* 230 * Initialize the GuC parameter block before starting the firmware 231 * transfer. These parameters are read by the firmware on startup 232 * and cannot be changed thereafter. 233 */ 234 static void guc_write_params(struct xe_guc *guc) 235 { 236 struct xe_gt *gt = guc_to_gt(guc); 237 int i; 238 239 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 240 241 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 242 243 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 244 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 245 } 246 247 static void guc_fini_hw(void *arg) 248 { 249 struct xe_guc *guc = arg; 250 struct xe_gt *gt = guc_to_gt(guc); 251 252 xe_gt_WARN_ON(gt, xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 253 xe_uc_fini_hw(&guc_to_gt(guc)->uc); 254 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 255 } 256 257 /** 258 * xe_guc_comm_init_early - early initialization of GuC communication 259 * @guc: the &xe_guc to initialize 260 * 261 * Must be called prior to first MMIO communication with GuC firmware. 262 */ 263 void xe_guc_comm_init_early(struct xe_guc *guc) 264 { 265 struct xe_gt *gt = guc_to_gt(guc); 266 267 if (xe_gt_is_media_type(gt)) 268 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 269 else 270 guc->notify_reg = GUC_HOST_INTERRUPT; 271 } 272 273 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 274 { 275 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 276 struct xe_device *xe = guc_to_xe(guc); 277 int ret; 278 279 if (!IS_DGFX(guc_to_xe(guc))) 280 return 0; 281 282 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 283 if (ret) 284 return ret; 285 286 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 287 if (ret) 288 return ret; 289 290 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 291 if (ret) 292 return ret; 293 294 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo); 295 if (ret) 296 return ret; 297 298 return 0; 299 } 300 301 static int vf_guc_init(struct xe_guc *guc) 302 { 303 int err; 304 305 xe_guc_comm_init_early(guc); 306 307 err = xe_guc_ct_init(&guc->ct); 308 if (err) 309 return err; 310 311 err = xe_guc_relay_init(&guc->relay); 312 if (err) 313 return err; 314 315 return 0; 316 } 317 318 int xe_guc_init(struct xe_guc *guc) 319 { 320 struct xe_device *xe = guc_to_xe(guc); 321 struct xe_gt *gt = guc_to_gt(guc); 322 int ret; 323 324 guc->fw.type = XE_UC_FW_TYPE_GUC; 325 ret = xe_uc_fw_init(&guc->fw); 326 if (ret) 327 goto out; 328 329 if (!xe_uc_fw_is_enabled(&guc->fw)) 330 return 0; 331 332 if (IS_SRIOV_VF(xe)) { 333 ret = vf_guc_init(guc); 334 if (ret) 335 goto out; 336 return 0; 337 } 338 339 ret = xe_guc_log_init(&guc->log); 340 if (ret) 341 goto out; 342 343 ret = xe_guc_capture_init(guc); 344 if (ret) 345 goto out; 346 347 ret = xe_guc_ads_init(&guc->ads); 348 if (ret) 349 goto out; 350 351 ret = xe_guc_ct_init(&guc->ct); 352 if (ret) 353 goto out; 354 355 ret = xe_guc_relay_init(&guc->relay); 356 if (ret) 357 goto out; 358 359 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 360 361 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 362 if (ret) 363 goto out; 364 365 guc_init_params(guc); 366 367 xe_guc_comm_init_early(guc); 368 369 return 0; 370 371 out: 372 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 373 return ret; 374 } 375 376 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 377 { 378 int err; 379 380 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 381 if (err) 382 return err; 383 384 /* XXX xe_guc_db_mgr_init not needed for now */ 385 386 return 0; 387 } 388 389 /** 390 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 391 * @guc: The GuC object 392 * 393 * Return: 0 on success, negative error code on error. 394 */ 395 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 396 { 397 int ret; 398 399 if (IS_SRIOV_VF(guc_to_xe(guc))) 400 return vf_guc_init_post_hwconfig(guc); 401 402 ret = xe_guc_realloc_post_hwconfig(guc); 403 if (ret) 404 return ret; 405 406 guc_init_params_post_hwconfig(guc); 407 408 ret = xe_guc_submit_init(guc, ~0); 409 if (ret) 410 return ret; 411 412 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 413 if (ret) 414 return ret; 415 416 ret = xe_guc_pc_init(&guc->pc); 417 if (ret) 418 return ret; 419 420 return xe_guc_ads_init_post_hwconfig(&guc->ads); 421 } 422 423 int xe_guc_post_load_init(struct xe_guc *guc) 424 { 425 xe_guc_ads_populate_post_load(&guc->ads); 426 guc->submission_state.enabled = true; 427 428 return 0; 429 } 430 431 int xe_guc_reset(struct xe_guc *guc) 432 { 433 struct xe_gt *gt = guc_to_gt(guc); 434 struct xe_mmio *mmio = >->mmio; 435 u32 guc_status, gdrst; 436 int ret; 437 438 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 439 440 if (IS_SRIOV_VF(gt_to_xe(gt))) 441 return xe_gt_sriov_vf_bootstrap(gt); 442 443 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 444 445 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 446 if (ret) { 447 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 448 goto err_out; 449 } 450 451 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 452 if (!(guc_status & GS_MIA_IN_RESET)) { 453 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 454 guc_status); 455 ret = -EIO; 456 goto err_out; 457 } 458 459 return 0; 460 461 err_out: 462 463 return ret; 464 } 465 466 static void guc_prepare_xfer(struct xe_guc *guc) 467 { 468 struct xe_gt *gt = guc_to_gt(guc); 469 struct xe_mmio *mmio = >->mmio; 470 struct xe_device *xe = guc_to_xe(guc); 471 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 472 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 473 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 474 GUC_ENABLE_MIA_CLOCK_GATING; 475 476 if (GRAPHICS_VERx100(xe) < 1250) 477 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 478 GUC_ENABLE_MIA_CACHING; 479 480 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 481 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 482 483 /* Must program this register before loading the ucode with DMA */ 484 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 485 486 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 487 488 /* Make sure GuC receives ARAT interrupts */ 489 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 490 } 491 492 /* 493 * Supporting MMIO & in memory RSA 494 */ 495 static int guc_xfer_rsa(struct xe_guc *guc) 496 { 497 struct xe_gt *gt = guc_to_gt(guc); 498 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 499 size_t copied; 500 int i; 501 502 if (guc->fw.rsa_size > 256) { 503 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 504 xe_uc_fw_rsa_offset(&guc->fw); 505 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 506 return 0; 507 } 508 509 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 510 if (copied < sizeof(rsa)) 511 return -ENOMEM; 512 513 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 514 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 515 516 return 0; 517 } 518 519 /* 520 * Check a previously read GuC status register (GUC_STATUS) looking for 521 * known terminal states (either completion or failure) of either the 522 * microkernel status field or the boot ROM status field. Returns +1 for 523 * successful completion, -1 for failure and 0 for any intermediate state. 524 */ 525 static int guc_load_done(u32 status) 526 { 527 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); 528 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); 529 530 switch (uk_val) { 531 case XE_GUC_LOAD_STATUS_READY: 532 return 1; 533 534 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 535 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 536 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 537 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 538 case XE_GUC_LOAD_STATUS_DPC_ERROR: 539 case XE_GUC_LOAD_STATUS_EXCEPTION: 540 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 541 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 542 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 543 return -1; 544 } 545 546 switch (br_val) { 547 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 548 case XE_BOOTROM_STATUS_RSA_FAILED: 549 case XE_BOOTROM_STATUS_PAVPC_FAILED: 550 case XE_BOOTROM_STATUS_WOPCM_FAILED: 551 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 552 case XE_BOOTROM_STATUS_JUMP_FAILED: 553 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 554 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 555 case XE_BOOTROM_STATUS_EXCEPTION: 556 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 557 return -1; 558 } 559 560 return 0; 561 } 562 563 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) 564 { 565 u32 freq; 566 int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq); 567 568 return ret ? ret : freq; 569 } 570 571 /* 572 * Wait for the GuC to start up. 573 * 574 * Measurements indicate this should take no more than 20ms (assuming the GT 575 * clock is at maximum frequency). However, thermal throttling and other issues 576 * can prevent the clock hitting max and thus making the load take significantly 577 * longer. Allow up to 200ms as a safety margin for real world worst case situations. 578 * 579 * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can 580 * lead to even longer times. E.g. if the GT is clamped to minimum frequency then 581 * the load times can be in the seconds range. So the timeout is increased for debug 582 * builds to ensure that problems can be correctly analysed. For release builds, the 583 * timeout is kept short so that users don't wait forever to find out that there is a 584 * problem. In either case, if the load took longer than is reasonable even with some 585 * 'sensible' throttling, then flag a warning because something is not right. 586 * 587 * Note that there is a limit on how long an individual usleep_range() can wait for, 588 * hence longer waits require wrapping a shorter wait in a loop. 589 * 590 * Note that the only reason an end user should hit the shorter timeout is in case of 591 * extreme thermal throttling. And a system that is that hot during boot is probably 592 * dead anyway! 593 */ 594 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 595 #define GUC_LOAD_RETRY_LIMIT 20 596 #else 597 #define GUC_LOAD_RETRY_LIMIT 3 598 #endif 599 #define GUC_LOAD_TIME_WARN_MS 200 600 601 static void guc_wait_ucode(struct xe_guc *guc) 602 { 603 struct xe_gt *gt = guc_to_gt(guc); 604 struct xe_mmio *mmio = >->mmio; 605 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 606 ktime_t before, after, delta; 607 int load_done; 608 u32 status = 0; 609 int count = 0; 610 u64 delta_ms; 611 u32 before_freq; 612 613 before_freq = xe_guc_pc_get_act_freq(guc_pc); 614 before = ktime_get(); 615 /* 616 * Note, can't use any kind of timing information from the call to xe_mmio_wait. 617 * It could return a thousand intermediate stages at random times. Instead, must 618 * manually track the total time taken and locally implement the timeout. 619 */ 620 do { 621 u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK); 622 int ret; 623 624 /* 625 * Wait for any change (intermediate or terminal) in the status register. 626 * Note, the return value is a don't care. The only failure code is timeout 627 * but the timeouts need to be accumulated over all the intermediate partial 628 * timeouts rather than allowing a huge timeout each time. So basically, need 629 * to treat a timeout no different to a value change. 630 */ 631 ret = xe_mmio_wait32_not(mmio, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK, 632 last_status, 1000 * 1000, &status, false); 633 if (ret < 0) 634 count++; 635 after = ktime_get(); 636 delta = ktime_sub(after, before); 637 delta_ms = ktime_to_ms(delta); 638 639 load_done = guc_load_done(status); 640 if (load_done != 0) 641 break; 642 643 if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000)) 644 break; 645 646 xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 647 count, xe_guc_pc_get_act_freq(guc_pc), 648 guc_pc_get_cur_freq(guc_pc), status, 649 REG_FIELD_GET(GS_BOOTROM_MASK, status), 650 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 651 } while (1); 652 653 if (load_done != 1) { 654 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 655 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 656 657 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n", 658 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 659 guc_pc_get_cur_freq(guc_pc), load_done); 660 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 661 REG_FIELD_GET(GS_MIA_IN_RESET, status), 662 bootrom, ukernel, 663 REG_FIELD_GET(GS_MIA_MASK, status), 664 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 665 666 switch (bootrom) { 667 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 668 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 669 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 670 break; 671 672 case XE_BOOTROM_STATUS_RSA_FAILED: 673 xe_gt_err(gt, "firmware signature verification failed\n"); 674 break; 675 676 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 677 xe_gt_err(gt, "firmware production part check failure\n"); 678 break; 679 } 680 681 switch (ukernel) { 682 case XE_GUC_LOAD_STATUS_EXCEPTION: 683 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 684 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 685 break; 686 687 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 688 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 689 break; 690 691 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 692 xe_gt_err(gt, "still extracting hwconfig table.\n"); 693 break; 694 } 695 696 xe_device_declare_wedged(gt_to_xe(gt)); 697 } else if (delta_ms > GUC_LOAD_TIME_WARN_MS) { 698 xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n", 699 delta_ms, status, count); 700 xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 701 xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 702 before_freq, xe_gt_throttle_get_limit_reasons(gt)); 703 } else { 704 xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n", 705 delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 706 before_freq, status, count); 707 } 708 } 709 710 static int __xe_guc_upload(struct xe_guc *guc) 711 { 712 int ret; 713 714 /* Raise GT freq to speed up HuC/GuC load */ 715 xe_guc_pc_raise_unslice(&guc->pc); 716 717 guc_write_params(guc); 718 guc_prepare_xfer(guc); 719 720 /* 721 * Note that GuC needs the CSS header plus uKernel code to be copied 722 * by the DMA engine in one operation, whereas the RSA signature is 723 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 724 * register (if key size <= 256) or through a ggtt-pinned vma (if key 725 * size > 256). The RSA size and therefore the way we provide it to the 726 * HW is fixed for each platform and hard-coded in the bootrom. 727 */ 728 ret = guc_xfer_rsa(guc); 729 if (ret) 730 goto out; 731 /* 732 * Current uCode expects the code to be loaded at 8k; locations below 733 * this are used for the stack. 734 */ 735 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 736 if (ret) 737 goto out; 738 739 /* Wait for authentication */ 740 guc_wait_ucode(guc); 741 742 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 743 return 0; 744 745 out: 746 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 747 return 0 /* FIXME: ret, don't want to stop load currently */; 748 } 749 750 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 751 { 752 struct xe_gt *gt = guc_to_gt(guc); 753 int ret; 754 755 ret = xe_gt_sriov_vf_bootstrap(gt); 756 if (ret) 757 return ret; 758 759 ret = xe_gt_sriov_vf_query_config(gt); 760 if (ret) 761 return ret; 762 763 ret = xe_guc_hwconfig_init(guc); 764 if (ret) 765 return ret; 766 767 ret = xe_guc_enable_communication(guc); 768 if (ret) 769 return ret; 770 771 ret = xe_gt_sriov_vf_connect(gt); 772 if (ret) 773 return ret; 774 775 ret = xe_gt_sriov_vf_query_runtime(gt); 776 if (ret) 777 return ret; 778 779 return 0; 780 } 781 782 /** 783 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 784 * @guc: The GuC object 785 * 786 * This function uploads a minimal GuC that does not support submissions but 787 * in a state where the hwconfig table can be read. Next, it reads and parses 788 * the hwconfig table so it can be used for subsequent steps in the driver load. 789 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 790 * 791 * Return: 0 on success, negative error code on error. 792 */ 793 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 794 { 795 int ret; 796 797 if (IS_SRIOV_VF(guc_to_xe(guc))) 798 return vf_guc_min_load_for_hwconfig(guc); 799 800 xe_guc_ads_populate_minimal(&guc->ads); 801 802 xe_guc_pc_init_early(&guc->pc); 803 804 ret = __xe_guc_upload(guc); 805 if (ret) 806 return ret; 807 808 ret = xe_guc_hwconfig_init(guc); 809 if (ret) 810 return ret; 811 812 ret = xe_guc_enable_communication(guc); 813 if (ret) 814 return ret; 815 816 return 0; 817 } 818 819 int xe_guc_upload(struct xe_guc *guc) 820 { 821 xe_guc_ads_populate(&guc->ads); 822 823 return __xe_guc_upload(guc); 824 } 825 826 static void guc_handle_mmio_msg(struct xe_guc *guc) 827 { 828 struct xe_gt *gt = guc_to_gt(guc); 829 u32 msg; 830 831 if (IS_SRIOV_VF(guc_to_xe(guc))) 832 return; 833 834 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 835 836 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 837 msg &= XE_GUC_RECV_MSG_EXCEPTION | 838 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 839 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 840 841 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 842 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 843 844 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 845 xe_gt_err(gt, "Received early GuC exception notification!\n"); 846 } 847 848 static void guc_enable_irq(struct xe_guc *guc) 849 { 850 struct xe_gt *gt = guc_to_gt(guc); 851 u32 events = xe_gt_is_media_type(gt) ? 852 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 853 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 854 855 /* Primary GuC and media GuC share a single enable bit */ 856 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 857 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 858 859 /* 860 * There are separate mask bits for primary and media GuCs, so use 861 * a RMW operation to avoid clobbering the other GuC's setting. 862 */ 863 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 864 } 865 866 int xe_guc_enable_communication(struct xe_guc *guc) 867 { 868 struct xe_device *xe = guc_to_xe(guc); 869 int err; 870 871 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 872 struct xe_gt *gt = guc_to_gt(guc); 873 struct xe_tile *tile = gt_to_tile(gt); 874 875 err = xe_memirq_init_guc(&tile->memirq, guc); 876 if (err) 877 return err; 878 } else { 879 guc_enable_irq(guc); 880 } 881 882 err = xe_guc_ct_enable(&guc->ct); 883 if (err) 884 return err; 885 886 guc_handle_mmio_msg(guc); 887 888 return 0; 889 } 890 891 int xe_guc_suspend(struct xe_guc *guc) 892 { 893 struct xe_gt *gt = guc_to_gt(guc); 894 u32 action[] = { 895 XE_GUC_ACTION_CLIENT_SOFT_RESET, 896 }; 897 int ret; 898 899 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 900 if (ret) { 901 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 902 return ret; 903 } 904 905 xe_guc_sanitize(guc); 906 return 0; 907 } 908 909 void xe_guc_notify(struct xe_guc *guc) 910 { 911 struct xe_gt *gt = guc_to_gt(guc); 912 const u32 default_notify_data = 0; 913 914 /* 915 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 916 * additional payload data to the GuC but this capability is not 917 * used by the firmware yet. Use default value in the meantime. 918 */ 919 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 920 } 921 922 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 923 { 924 u32 action[] = { 925 XE_GUC_ACTION_AUTHENTICATE_HUC, 926 rsa_addr 927 }; 928 929 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 930 } 931 932 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 933 u32 len, u32 *response_buf) 934 { 935 struct xe_device *xe = guc_to_xe(guc); 936 struct xe_gt *gt = guc_to_gt(guc); 937 struct xe_mmio *mmio = >->mmio; 938 u32 header, reply; 939 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 940 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 941 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 942 int ret; 943 int i; 944 945 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 946 947 xe_assert(xe, !xe_guc_ct_enabled(&guc->ct)); 948 xe_assert(xe, len); 949 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 950 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 951 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 952 GUC_HXG_ORIGIN_HOST); 953 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 954 GUC_HXG_TYPE_REQUEST); 955 956 retry: 957 /* Not in critical data-path, just do if else for GT type */ 958 if (xe_gt_is_media_type(gt)) { 959 for (i = 0; i < len; ++i) 960 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 961 request[i]); 962 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 963 } else { 964 for (i = 0; i < len; ++i) 965 xe_mmio_write32(mmio, VF_SW_FLAG(i), 966 request[i]); 967 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 968 } 969 970 xe_guc_notify(guc); 971 972 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 973 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 974 50000, &reply, false); 975 if (ret) { 976 timeout: 977 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 978 request[0], reply); 979 return ret; 980 } 981 982 header = xe_mmio_read32(mmio, reply_reg); 983 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 984 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 985 /* 986 * Once we got a BUSY reply we must wait again for the final 987 * response but this time we can't use ORIGIN mask anymore. 988 * To spot a right change in the reply, we take advantage that 989 * response SUCCESS and FAILURE differ only by the single bit 990 * and all other bits are set and can be used as a new mask. 991 */ 992 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 993 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 994 995 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 996 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 997 998 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 999 1000000, &header, false); 1000 1001 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1002 GUC_HXG_ORIGIN_GUC)) 1003 goto proto; 1004 if (unlikely(ret)) { 1005 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1006 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1007 goto proto; 1008 goto timeout; 1009 } 1010 } 1011 1012 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1013 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1014 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1015 1016 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1017 request[0], reason); 1018 goto retry; 1019 } 1020 1021 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1022 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1023 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1024 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1025 1026 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1027 request[0], error, hint); 1028 return -ENXIO; 1029 } 1030 1031 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1032 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1033 proto: 1034 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1035 request[0], header); 1036 return -EPROTO; 1037 } 1038 1039 /* Just copy entire possible message response */ 1040 if (response_buf) { 1041 response_buf[0] = header; 1042 1043 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1044 reply_reg.addr += sizeof(u32); 1045 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1046 } 1047 } 1048 1049 /* Use data from the GuC response as our return value */ 1050 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1051 } 1052 1053 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1054 { 1055 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1056 } 1057 1058 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1059 { 1060 struct xe_device *xe = guc_to_xe(guc); 1061 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1062 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1063 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1064 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1065 GUC_ACTION_HOST2GUC_SELF_CFG), 1066 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1067 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1068 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1069 lower_32_bits(val)), 1070 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1071 upper_32_bits(val)), 1072 }; 1073 int ret; 1074 1075 xe_assert(xe, len <= 2); 1076 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1077 1078 /* Self config must go over MMIO */ 1079 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1080 1081 if (unlikely(ret < 0)) 1082 return ret; 1083 if (unlikely(ret > 1)) 1084 return -EPROTO; 1085 if (unlikely(!ret)) 1086 return -ENOKEY; 1087 1088 return 0; 1089 } 1090 1091 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1092 { 1093 return guc_self_cfg(guc, key, 1, val); 1094 } 1095 1096 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1097 { 1098 return guc_self_cfg(guc, key, 2, val); 1099 } 1100 1101 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1102 { 1103 if (iir & GUC_INTR_GUC2HOST) 1104 xe_guc_ct_irq_handler(&guc->ct); 1105 } 1106 1107 void xe_guc_sanitize(struct xe_guc *guc) 1108 { 1109 xe_uc_fw_sanitize(&guc->fw); 1110 xe_guc_ct_disable(&guc->ct); 1111 guc->submission_state.enabled = false; 1112 } 1113 1114 int xe_guc_reset_prepare(struct xe_guc *guc) 1115 { 1116 return xe_guc_submit_reset_prepare(guc); 1117 } 1118 1119 void xe_guc_reset_wait(struct xe_guc *guc) 1120 { 1121 xe_guc_submit_reset_wait(guc); 1122 } 1123 1124 void xe_guc_stop_prepare(struct xe_guc *guc) 1125 { 1126 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1127 int err; 1128 1129 err = xe_guc_pc_stop(&guc->pc); 1130 xe_gt_WARN(guc_to_gt(guc), err, "Failed to stop GuC PC: %pe\n", 1131 ERR_PTR(err)); 1132 } 1133 } 1134 1135 void xe_guc_stop(struct xe_guc *guc) 1136 { 1137 xe_guc_ct_stop(&guc->ct); 1138 1139 xe_guc_submit_stop(guc); 1140 } 1141 1142 int xe_guc_start(struct xe_guc *guc) 1143 { 1144 if (!IS_SRIOV_VF(guc_to_xe(guc))) { 1145 int err; 1146 1147 err = xe_guc_pc_start(&guc->pc); 1148 xe_gt_WARN(guc_to_gt(guc), err, "Failed to start GuC PC: %pe\n", 1149 ERR_PTR(err)); 1150 } 1151 1152 return xe_guc_submit_start(guc); 1153 } 1154 1155 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1156 { 1157 struct xe_gt *gt = guc_to_gt(guc); 1158 u32 status; 1159 int err; 1160 int i; 1161 1162 xe_uc_fw_print(&guc->fw, p); 1163 1164 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1165 if (err) 1166 return; 1167 1168 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1169 1170 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1171 drm_printf(p, "\tBootrom status = 0x%x\n", 1172 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1173 drm_printf(p, "\tuKernel status = 0x%x\n", 1174 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1175 drm_printf(p, "\tMIA Core status = 0x%x\n", 1176 REG_FIELD_GET(GS_MIA_MASK, status)); 1177 drm_printf(p, "\tLog level = %d\n", 1178 xe_guc_log_get_level(&guc->log)); 1179 1180 drm_puts(p, "\nScratch registers:\n"); 1181 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1182 drm_printf(p, "\t%2d: \t0x%x\n", 1183 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1184 } 1185 1186 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 1187 1188 xe_guc_ct_print(&guc->ct, p); 1189 xe_guc_submit_print(guc, p); 1190 } 1191 1192 /** 1193 * xe_guc_declare_wedged() - Declare GuC wedged 1194 * @guc: the GuC object 1195 * 1196 * Wedge the GuC which stops all submission, saves desired debug state, and 1197 * cleans up anything which could timeout. 1198 */ 1199 void xe_guc_declare_wedged(struct xe_guc *guc) 1200 { 1201 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1202 1203 xe_guc_reset_prepare(guc); 1204 xe_guc_ct_stop(&guc->ct); 1205 xe_guc_submit_wedge(guc); 1206 } 1207