1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <linux/iopoll.h> 9 #include <drm/drm_managed.h> 10 11 #include <generated/xe_wa_oob.h> 12 13 #include "abi/guc_actions_abi.h" 14 #include "abi/guc_errors_abi.h" 15 #include "abi/guc_klvs_abi.h" 16 #include "regs/xe_gt_regs.h" 17 #include "regs/xe_gtt_defs.h" 18 #include "regs/xe_guc_regs.h" 19 #include "regs/xe_irq_regs.h" 20 #include "xe_bo.h" 21 #include "xe_configfs.h" 22 #include "xe_device.h" 23 #include "xe_force_wake.h" 24 #include "xe_gt.h" 25 #include "xe_gt_printk.h" 26 #include "xe_gt_sriov_vf.h" 27 #include "xe_gt_throttle.h" 28 #include "xe_gt_sriov_pf_migration.h" 29 #include "xe_guc_ads.h" 30 #include "xe_guc_buf.h" 31 #include "xe_guc_capture.h" 32 #include "xe_guc_ct.h" 33 #include "xe_guc_db_mgr.h" 34 #include "xe_guc_engine_activity.h" 35 #include "xe_guc_hwconfig.h" 36 #include "xe_guc_klv_helpers.h" 37 #include "xe_guc_log.h" 38 #include "xe_guc_pc.h" 39 #include "xe_guc_rc.h" 40 #include "xe_guc_relay.h" 41 #include "xe_guc_submit.h" 42 #include "xe_memirq.h" 43 #include "xe_mmio.h" 44 #include "xe_platform_types.h" 45 #include "xe_sleep.h" 46 #include "xe_sriov.h" 47 #include "xe_sriov_pf_migration.h" 48 #include "xe_uc.h" 49 #include "xe_uc_fw.h" 50 #include "xe_wa.h" 51 #include "xe_wopcm.h" 52 53 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 54 struct xe_bo *bo) 55 { 56 struct xe_device *xe = guc_to_xe(guc); 57 u32 addr; 58 59 /* 60 * For most BOs, the address on the allocating tile is fine. However for 61 * some, e.g. G2G CTB, the address on a specific tile is required as it 62 * might be different for each tile. So, just always ask for the address 63 * on the target GuC. 64 */ 65 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 66 67 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 68 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 69 xe_assert(xe, addr < GUC_GGTT_TOP); 70 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); 71 72 return addr; 73 } 74 75 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 76 { 77 u32 level = xe_guc_log_get_level(&guc->log); 78 u32 flags = 0; 79 80 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 81 flags |= GUC_LOG_DISABLED; 82 else 83 flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level)); 84 85 return flags; 86 } 87 88 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 89 { 90 struct xe_device *xe = guc_to_xe(guc); 91 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 92 93 if (!xe->info.skip_guc_pc) 94 flags |= GUC_CTL_ENABLE_SLPC; 95 96 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) 97 flags |= GUC_CTL_ENABLE_PSMI_LOGGING; 98 99 if (xe_guc_using_main_gamctrl_queues(guc)) 100 flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES; 101 102 if (xe_device_is_l2_flush_optimized(xe) && xe_gt_is_media_type(guc_to_gt(guc))) 103 flags |= GUC_CTL_ENABLE_L2FLUSH_OPT; 104 105 /* 106 * On GuC firmware 70.66 and above, the GUC_FEATURE_KLV_DISABLE_MULTI_QUEUE 107 * Feature KLV is used instead. 108 */ 109 if (!xe_configfs_get_enable_multi_queue(to_pci_dev(xe->drm.dev)) && 110 !GUC_FIRMWARE_VER_AT_LEAST(guc, 70, 66)) 111 flags |= GUC_CTL_DISABLE_MULTI_QUEUE; 112 113 return flags; 114 } 115 116 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 117 { 118 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 119 u32 flags; 120 121 #if (((XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE) % SZ_1M) == 0) 122 #define LOG_UNIT SZ_1M 123 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 124 #else 125 #define LOG_UNIT SZ_4K 126 #define LOG_FLAG 0 127 #endif 128 129 #if (((XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 130 #define CAPTURE_UNIT SZ_1M 131 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 132 #else 133 #define CAPTURE_UNIT SZ_4K 134 #define CAPTURE_FLAG 0 135 #endif 136 137 BUILD_BUG_ON(!XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE); 138 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE, LOG_UNIT)); 139 BUILD_BUG_ON(!XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE); 140 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE, LOG_UNIT)); 141 BUILD_BUG_ON(!XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE); 142 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 143 144 flags = GUC_LOG_VALID | 145 GUC_LOG_NOTIFY_ON_HALF_FULL | 146 CAPTURE_FLAG | 147 LOG_FLAG | 148 FIELD_PREP(GUC_LOG_CRASH_DUMP, XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE / LOG_UNIT - 1) | 149 FIELD_PREP(GUC_LOG_EVENT_DATA, XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE / LOG_UNIT - 1) | 150 FIELD_PREP(GUC_LOG_STATE_CAPTURE, XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE / 151 CAPTURE_UNIT - 1) | 152 FIELD_PREP(GUC_LOG_BUF_ADDR, offset); 153 154 #undef LOG_UNIT 155 #undef LOG_FLAG 156 #undef CAPTURE_UNIT 157 #undef CAPTURE_FLAG 158 159 return flags; 160 } 161 162 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 163 { 164 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 165 u32 flags = FIELD_PREP(GUC_ADS_ADDR, ads); 166 167 return flags; 168 } 169 170 static bool needs_wa_dual_queue(struct xe_gt *gt) 171 { 172 /* 173 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 174 * on RCS and CCSes with different address spaces, which on DG2 is 175 * required as a WA for an HW bug. 176 */ 177 if (XE_GT_WA(gt, 22011391025)) 178 return true; 179 180 /* 181 * On newer platforms, the HW has been updated to not allow parallel 182 * execution of different address spaces, so the RCS/CCS will stall the 183 * context switch if one of the other RCS/CCSes is busy with a different 184 * address space. While functionally correct, having a submission 185 * stalled on the HW limits the GuC ability to shuffle things around and 186 * can cause complications if the non-stalled submission runs for a long 187 * time, because the GuC doesn't know that the stalled submission isn't 188 * actually running and might declare it as hung. Therefore, we enable 189 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 190 * to move management back to the GuC. 191 */ 192 if (CCS_INSTANCES(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 193 return true; 194 195 return false; 196 } 197 198 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 199 { 200 struct xe_device *xe = guc_to_xe(guc); 201 struct xe_gt *gt = guc_to_gt(guc); 202 u32 flags = 0; 203 204 if (XE_GT_WA(gt, 22012773006)) 205 flags |= GUC_WA_POLLCS; 206 207 if (XE_GT_WA(gt, 14014475959)) 208 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 209 210 if (needs_wa_dual_queue(gt)) 211 flags |= GUC_WA_DUAL_QUEUE; 212 213 /* 214 * Wa_22011802037: FIXME - there's more to be done than simply setting 215 * this flag: make sure each CS is stopped when preparing for GT reset 216 * and wait for pending MI_FW. 217 */ 218 if (GRAPHICS_VERx100(xe) < 1270) 219 flags |= GUC_WA_PRE_PARSER; 220 221 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) 222 flags |= GUC_WA_CONTEXT_ISOLATION; 223 224 if (XE_GT_WA(gt, 18020744125) && 225 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 226 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 227 228 if (XE_GT_WA(gt, 14018913170)) 229 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 230 231 if (XE_GT_WA(gt, 16023683509)) 232 flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6; 233 234 return flags; 235 } 236 237 static u32 guc_ctl_devid(struct xe_guc *guc) 238 { 239 struct xe_device *xe = guc_to_xe(guc); 240 241 return (((u32)xe->info.devid) << 16) | xe->info.revid; 242 } 243 244 static void guc_print_params(struct xe_guc *guc) 245 { 246 struct xe_gt *gt = guc_to_gt(guc); 247 u32 *params = guc->params; 248 int i; 249 250 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 251 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 252 253 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 254 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 255 } 256 257 static void guc_init_params(struct xe_guc *guc) 258 { 259 u32 *params = guc->params; 260 261 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 262 params[GUC_CTL_FEATURE] = 0; 263 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 264 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 265 params[GUC_CTL_WA] = 0; 266 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 267 268 guc_print_params(guc); 269 } 270 271 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 272 { 273 u32 *params = guc->params; 274 275 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 276 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 277 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 278 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 279 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 280 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 281 282 guc_print_params(guc); 283 } 284 285 /* 286 * Initialize the GuC parameter block before starting the firmware 287 * transfer. These parameters are read by the firmware on startup 288 * and cannot be changed thereafter. 289 */ 290 static void guc_write_params(struct xe_guc *guc) 291 { 292 struct xe_gt *gt = guc_to_gt(guc); 293 int i; 294 295 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 296 297 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 298 299 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 300 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 301 } 302 303 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 304 u32 desc_addr, u32 buff_addr, u32 size) 305 { 306 struct xe_gt *gt = guc_to_gt(guc); 307 struct xe_device *xe = gt_to_xe(gt); 308 u32 action[] = { 309 XE_GUC_ACTION_REGISTER_G2G, 310 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 311 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 312 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 313 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 314 desc_addr, 315 buff_addr, 316 }; 317 318 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 319 xe_assert(xe, !(size % SZ_4K)); 320 321 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 322 } 323 324 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 325 { 326 struct xe_gt *gt = guc_to_gt(guc); 327 struct xe_device *xe = gt_to_xe(gt); 328 u32 action[] = { 329 XE_GUC_ACTION_DEREGISTER_G2G, 330 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 331 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 332 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 333 }; 334 335 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 336 337 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 338 } 339 340 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 341 342 #define G2G_BUFFER_SIZE (SZ_4K) 343 #define G2G_DESC_SIZE (64) 344 #define G2G_DESC_AREA_SIZE (SZ_4K) 345 346 /* 347 * Generate a unique id for each bi-directional CTB for each pair of 348 * near and far tiles/devices. The id can then be used as an index into 349 * a single allocation that is sub-divided into multiple CTBs. 350 * 351 * For example, with two devices per tile and two tiles, the table should 352 * look like: 353 * Far <tile>.<dev> 354 * 0.0 0.1 1.0 1.1 355 * N 0.0 --/-- 00/01 02/03 04/05 356 * e 0.1 01/00 --/-- 06/07 08/09 357 * a 1.0 03/02 07/06 --/-- 10/11 358 * r 1.1 05/04 09/08 11/10 --/-- 359 * 360 * Where each entry is Rx/Tx channel id. 361 * 362 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 363 * be reading from channel #11 and writing to channel #10. Whereas, 364 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 365 */ 366 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 367 u32 type, u32 max_inst, bool have_dev) 368 { 369 u32 near = near_tile, far = far_tile; 370 u32 idx = 0, x, y, direction; 371 int i; 372 373 if (have_dev) { 374 near = (near << 1) | near_dev; 375 far = (far << 1) | far_dev; 376 } 377 378 /* No need to send to one's self */ 379 if (far == near) 380 return -1; 381 382 if (far > near) { 383 /* Top right table half */ 384 x = far; 385 y = near; 386 387 /* T/R is 'forwards' direction */ 388 direction = type; 389 } else { 390 /* Bottom left table half */ 391 x = near; 392 y = far; 393 394 /* B/L is 'backwards' direction */ 395 direction = (1 - type); 396 } 397 398 /* Count the rows prior to the target */ 399 for (i = y; i > 0; i--) 400 idx += max_inst - i; 401 402 /* Count this row up to the target */ 403 idx += (x - 1 - y); 404 405 /* Slots are in Rx/Tx pairs */ 406 idx *= 2; 407 408 /* Pick Rx/Tx direction */ 409 idx += direction; 410 411 return idx; 412 } 413 414 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 415 { 416 struct xe_gt *near_gt = guc_to_gt(near_guc); 417 struct xe_device *xe = gt_to_xe(near_gt); 418 struct xe_bo *g2g_bo; 419 u32 near_tile = gt_to_tile(near_gt)->id; 420 u32 near_dev = G2G_DEV(near_gt); 421 u32 far_tile = gt_to_tile(far_gt)->id; 422 u32 far_dev = G2G_DEV(far_gt); 423 u32 max = xe->info.gt_count; 424 u32 base, desc, buf; 425 int slot; 426 427 /* G2G is not allowed between different cards */ 428 xe_assert(xe, xe == gt_to_xe(far_gt)); 429 430 g2g_bo = near_guc->g2g.bo; 431 xe_assert(xe, g2g_bo); 432 433 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 434 xe_assert(xe, slot >= 0); 435 436 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 437 desc = base + slot * G2G_DESC_SIZE; 438 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 439 440 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 441 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(g2g_bo)); 442 443 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 444 desc, buf, G2G_BUFFER_SIZE); 445 } 446 447 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 448 { 449 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 450 } 451 452 static u32 guc_g2g_size(struct xe_guc *guc) 453 { 454 struct xe_gt *gt = guc_to_gt(guc); 455 struct xe_device *xe = gt_to_xe(gt); 456 unsigned int count = xe->info.gt_count; 457 u32 num_channels = (count * (count - 1)) / 2; 458 459 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 460 461 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 462 } 463 464 static bool xe_guc_g2g_wanted(struct xe_device *xe) 465 { 466 /* Can't do GuC to GuC communication if there is only one GuC */ 467 if (xe->info.gt_count <= 1) 468 return false; 469 470 /* No current user */ 471 return false; 472 } 473 474 static int guc_g2g_alloc(struct xe_guc *guc) 475 { 476 struct xe_gt *gt = guc_to_gt(guc); 477 struct xe_device *xe = gt_to_xe(gt); 478 struct xe_tile *tile = gt_to_tile(gt); 479 struct xe_bo *bo; 480 u32 g2g_size; 481 482 if (guc->g2g.bo) 483 return 0; 484 485 if (gt->info.id != 0) { 486 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 487 struct xe_guc *root_guc = &root_gt->uc.guc; 488 struct xe_bo *bo; 489 490 bo = xe_bo_get(root_guc->g2g.bo); 491 if (!bo) 492 return -ENODEV; 493 494 guc->g2g.bo = bo; 495 guc->g2g.owned = false; 496 return 0; 497 } 498 499 g2g_size = guc_g2g_size(guc); 500 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 501 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 502 XE_BO_FLAG_GGTT | 503 XE_BO_FLAG_GGTT_ALL | 504 XE_BO_FLAG_GGTT_INVALIDATE | 505 XE_BO_FLAG_PINNED_NORESTORE); 506 if (IS_ERR(bo)) 507 return PTR_ERR(bo); 508 509 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 510 guc->g2g.bo = bo; 511 guc->g2g.owned = true; 512 513 return 0; 514 } 515 516 static void guc_g2g_fini(struct xe_guc *guc) 517 { 518 if (!guc->g2g.bo) 519 return; 520 521 /* Unpinning the owned object is handled by generic shutdown */ 522 if (!guc->g2g.owned) 523 xe_bo_put(guc->g2g.bo); 524 525 guc->g2g.bo = NULL; 526 } 527 528 static int guc_g2g_start(struct xe_guc *guc) 529 { 530 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 531 struct xe_device *xe = gt_to_xe(gt); 532 unsigned int i, j; 533 int t, err; 534 bool have_dev; 535 536 if (!guc->g2g.bo) { 537 int ret; 538 539 ret = guc_g2g_alloc(guc); 540 if (ret) 541 return ret; 542 } 543 544 /* GuC interface will need extending if more GT device types are ever created. */ 545 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 546 547 /* Channel numbering depends on whether there are multiple GTs per tile */ 548 have_dev = xe->info.gt_count > xe->info.tile_count; 549 550 for_each_gt(far_gt, xe, i) { 551 u32 far_tile, far_dev; 552 553 if (far_gt->info.id == gt->info.id) 554 continue; 555 556 far_tile = gt_to_tile(far_gt)->id; 557 far_dev = G2G_DEV(far_gt); 558 559 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 560 err = guc_g2g_register(guc, far_gt, t, have_dev); 561 if (err) { 562 while (--t >= 0) 563 guc_g2g_deregister(guc, far_tile, far_dev, t); 564 goto err_deregister; 565 } 566 } 567 } 568 569 return 0; 570 571 err_deregister: 572 for_each_gt(far_gt, xe, j) { 573 u32 tile, dev; 574 575 if (far_gt->info.id == gt->info.id) 576 continue; 577 578 if (j >= i) 579 break; 580 581 tile = gt_to_tile(far_gt)->id; 582 dev = G2G_DEV(far_gt); 583 584 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 585 guc_g2g_deregister(guc, tile, dev, t); 586 } 587 588 return err; 589 } 590 591 static int __guc_opt_in_features_enable(struct xe_guc *guc, u64 addr, u32 num_dwords) 592 { 593 u32 action[] = { 594 XE_GUC_ACTION_OPT_IN_FEATURE_KLV, 595 lower_32_bits(addr), 596 upper_32_bits(addr), 597 num_dwords 598 }; 599 600 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 601 } 602 603 static bool supports_dynamic_ics(struct xe_guc *guc) 604 { 605 struct xe_device *xe = guc_to_xe(guc); 606 struct xe_gt *gt = guc_to_gt(guc); 607 608 /* Dynamic ICS is available for PVC and Xe2 and newer platforms. */ 609 if (xe->info.platform != XE_PVC && GRAPHICS_VER(xe) < 20) 610 return false; 611 612 /* 613 * The feature is currently not compatible with multi-lrc, so the GuC 614 * does not support it at all on the media engines (which are the main 615 * users of mlrc). On the primary GT side, to avoid it being used in 616 * conjunction with mlrc, we only enable it if we are in single CCS 617 * mode. 618 */ 619 if (xe_gt_is_media_type(gt) || gt->ccs_mode > 1) 620 return false; 621 622 /* 623 * Dynamic ICS requires GuC v70.40.1, which maps to compatibility 624 * version v1.18.4. 625 */ 626 return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 4); 627 } 628 629 #define OPT_IN_MAX_DWORDS 16 630 int xe_guc_opt_in_features_enable(struct xe_guc *guc) 631 { 632 struct xe_device *xe = guc_to_xe(guc); 633 CLASS(xe_guc_buf, buf)(&guc->buf, OPT_IN_MAX_DWORDS); 634 u32 count = 0; 635 u32 *klvs; 636 int ret; 637 638 if (!xe_guc_buf_is_valid(buf)) 639 return -ENOBUFS; 640 641 klvs = xe_guc_buf_cpu_ptr(buf); 642 643 /* 644 * The extra CAT error type opt-in was added in GuC v70.17.0, which maps 645 * to compatibility version v1.7.0. 646 * Note that the GuC allows enabling this KLV even on platforms that do 647 * not support the extra type; in such case the returned type variable 648 * will be set to a known invalid value which we can check against. 649 */ 650 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 7, 0)) 651 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_EXT_CAT_ERR_TYPE); 652 653 /* 654 * The uncorrectable local error notification opt-in was added in 655 * GuC v70.38.0, which maps to compatibility version v1.18.0. 656 */ 657 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 0) && 658 guc_to_gt(guc)->info.has_uncorrectable_error_reporting) 659 klvs[count++] = 660 PREP_GUC_KLV_TAG(OPT_IN_FEATURE_UNCORRECTABLE_LOCAL_ERROR_NOTIFICATION); 661 662 if (supports_dynamic_ics(guc)) 663 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH); 664 665 if (count) { 666 xe_assert(xe, count <= OPT_IN_MAX_DWORDS); 667 668 ret = __guc_opt_in_features_enable(guc, xe_guc_buf_flush(buf), count); 669 if (ret < 0) { 670 xe_gt_err(guc_to_gt(guc), 671 "failed to enable GuC opt-in features: %pe\n", 672 ERR_PTR(ret)); 673 return ret; 674 } 675 } 676 677 return 0; 678 } 679 680 static void guc_fini_hw(void *arg) 681 { 682 struct xe_guc *guc = arg; 683 struct xe_gt *gt = guc_to_gt(guc); 684 685 xe_with_force_wake(fw_ref, gt_to_fw(gt), XE_FORCEWAKE_ALL) 686 xe_uc_sanitize_reset(&guc_to_gt(guc)->uc); 687 688 guc_g2g_fini(guc); 689 } 690 691 static void vf_guc_fini_hw(void *arg) 692 { 693 struct xe_guc *guc = arg; 694 695 xe_gt_sriov_vf_reset(guc_to_gt(guc)); 696 } 697 698 /** 699 * xe_guc_comm_init_early - early initialization of GuC communication 700 * @guc: the &xe_guc to initialize 701 * 702 * Must be called prior to first MMIO communication with GuC firmware. 703 */ 704 void xe_guc_comm_init_early(struct xe_guc *guc) 705 { 706 struct xe_gt *gt = guc_to_gt(guc); 707 708 if (xe_gt_is_media_type(gt)) 709 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 710 else 711 guc->notify_reg = GUC_HOST_INTERRUPT; 712 } 713 714 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 715 { 716 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 717 struct xe_device *xe = guc_to_xe(guc); 718 int ret; 719 720 if (!IS_DGFX(guc_to_xe(guc))) 721 return 0; 722 723 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 724 if (ret) 725 return ret; 726 727 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 728 if (ret) 729 return ret; 730 731 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 732 if (ret) 733 return ret; 734 735 return 0; 736 } 737 738 static int vf_guc_init_noalloc(struct xe_guc *guc) 739 { 740 struct xe_gt *gt = guc_to_gt(guc); 741 int err; 742 743 err = xe_gt_sriov_vf_bootstrap(gt); 744 if (err) 745 return err; 746 747 err = xe_gt_sriov_vf_query_config(gt); 748 if (err) 749 return err; 750 751 return 0; 752 } 753 754 int xe_guc_init_noalloc(struct xe_guc *guc) 755 { 756 struct xe_device *xe = guc_to_xe(guc); 757 struct xe_gt *gt = guc_to_gt(guc); 758 int ret; 759 760 xe_guc_comm_init_early(guc); 761 762 ret = xe_guc_ct_init_noalloc(&guc->ct); 763 if (ret) 764 goto out; 765 766 ret = xe_guc_relay_init(&guc->relay); 767 if (ret) 768 goto out; 769 770 if (IS_SRIOV_VF(xe)) { 771 ret = vf_guc_init_noalloc(guc); 772 if (ret) 773 goto out; 774 } 775 776 return 0; 777 778 out: 779 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 780 return ret; 781 } 782 783 int xe_guc_init(struct xe_guc *guc) 784 { 785 struct xe_device *xe = guc_to_xe(guc); 786 struct xe_gt *gt = guc_to_gt(guc); 787 int ret; 788 789 guc->fw.type = XE_UC_FW_TYPE_GUC; 790 ret = xe_uc_fw_init(&guc->fw); 791 if (ret) 792 return ret; 793 794 if (!xe_uc_fw_is_enabled(&guc->fw)) 795 return 0; 796 797 /* Disable page reclaim if GuC FW does not support */ 798 if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 14, 0)) 799 xe->info.has_page_reclaim_hw_assist = false; 800 801 /* Disable indirect_ring_state if missing GuC 70.53+ WA 14025515070. */ 802 if (gt->info.has_indirect_ring_state && 803 XE_GT_WA(gt, 14025515070) && 804 GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 26, 0)) { 805 gt->info.has_indirect_ring_state = 0; 806 xe_gt_notice(gt, "indirect ring state requires WA in GuC submit ver 1.26+\n"); 807 } 808 809 if (IS_SRIOV_VF(xe)) { 810 ret = devm_add_action_or_reset(xe->drm.dev, vf_guc_fini_hw, guc); 811 if (ret) 812 goto out; 813 814 ret = xe_guc_ct_init(&guc->ct); 815 if (ret) 816 goto out; 817 return 0; 818 } 819 820 ret = xe_guc_log_init(&guc->log); 821 if (ret) 822 goto out; 823 824 ret = xe_guc_capture_init(guc); 825 if (ret) 826 goto out; 827 828 ret = xe_guc_ads_init(&guc->ads); 829 if (ret) 830 goto out; 831 832 ret = xe_guc_ct_init(&guc->ct); 833 if (ret) 834 goto out; 835 836 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 837 838 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 839 if (ret) 840 goto out; 841 842 guc_init_params(guc); 843 844 return 0; 845 846 out: 847 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 848 return ret; 849 } 850 851 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 852 { 853 int err; 854 855 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 856 if (err) 857 return err; 858 859 err = xe_guc_buf_cache_init(&guc->buf); 860 if (err) 861 return err; 862 863 /* XXX xe_guc_db_mgr_init not needed for now */ 864 865 return 0; 866 } 867 868 static u32 guc_additional_cache_size(struct xe_device *xe) 869 { 870 if (IS_SRIOV_PF(xe) && xe_sriov_pf_migration_supported(xe)) 871 return XE_GT_SRIOV_PF_MIGRATION_GUC_DATA_MAX_SIZE; 872 else 873 return 0; /* Fallback to default size */ 874 } 875 876 /** 877 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 878 * @guc: The GuC object 879 * 880 * Return: 0 on success, negative error code on error. 881 */ 882 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 883 { 884 int ret; 885 886 if (IS_SRIOV_VF(guc_to_xe(guc))) 887 return vf_guc_init_post_hwconfig(guc); 888 889 ret = xe_guc_realloc_post_hwconfig(guc); 890 if (ret) 891 return ret; 892 893 ret = xe_guc_ct_init_post_hwconfig(&guc->ct); 894 if (ret) 895 return ret; 896 897 guc_init_params_post_hwconfig(guc); 898 899 ret = xe_guc_submit_init(guc, ~0); 900 if (ret) 901 return ret; 902 903 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 904 if (ret) 905 return ret; 906 907 ret = xe_guc_pc_init(&guc->pc); 908 if (ret) 909 return ret; 910 911 ret = xe_guc_rc_init(guc); 912 if (ret) 913 return ret; 914 915 ret = xe_guc_engine_activity_init(guc); 916 if (ret) 917 return ret; 918 919 ret = xe_guc_buf_cache_init_with_size(&guc->buf, 920 guc_additional_cache_size(guc_to_xe(guc))); 921 if (ret) 922 return ret; 923 924 return xe_guc_ads_init_post_hwconfig(&guc->ads); 925 } 926 927 int xe_guc_post_load_init(struct xe_guc *guc) 928 { 929 int ret; 930 931 xe_guc_ads_populate_post_load(&guc->ads); 932 933 ret = xe_guc_opt_in_features_enable(guc); 934 if (ret) 935 return ret; 936 937 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 938 ret = guc_g2g_start(guc); 939 if (ret) 940 return ret; 941 } 942 943 return xe_guc_submit_enable(guc); 944 } 945 946 /* 947 * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only reset by ensuring 948 * SRAM save/restore operations are complete before reset. 949 */ 950 static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc) 951 { 952 struct xe_gt *gt = guc_to_gt(guc); 953 u32 boot_hash_chk, guc_status, sram_status; 954 int ret; 955 956 guc_status = xe_mmio_read32(>->mmio, GUC_STATUS); 957 if (guc_status & GS_MIA_IN_RESET) 958 return; 959 960 boot_hash_chk = xe_mmio_read32(>->mmio, BOOT_HASH_CHK); 961 if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID)) 962 return; 963 964 /* Disable idle flow during reset (GuC reset re-enables it automatically) */ 965 xe_mmio_rmw32(>->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE); 966 967 ret = xe_mmio_wait32(>->mmio, GUC_STATUS, GS_UKERNEL_MASK, 968 FIELD_PREP(GS_UKERNEL_MASK, XE_GUC_LOAD_STATUS_READY), 969 100000, &guc_status, false); 970 if (ret) 971 xe_gt_warn(gt, "GuC not ready after disabling idle flow (GUC_STATUS: 0x%x)\n", 972 guc_status); 973 974 ret = xe_mmio_wait32(>->mmio, GUC_SRAM_STATUS, GUC_SRAM_HANDLING_MASK, 975 0, 5000, &sram_status, false); 976 if (ret) 977 xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 0x%x)\n", 978 sram_status); 979 } 980 981 int xe_guc_reset(struct xe_guc *guc) 982 { 983 struct xe_gt *gt = guc_to_gt(guc); 984 struct xe_mmio *mmio = >->mmio; 985 u32 guc_status, gdrst; 986 int ret; 987 988 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 989 990 if (IS_SRIOV_VF(gt_to_xe(gt))) 991 return xe_gt_sriov_vf_bootstrap(gt); 992 993 if (XE_GT_WA(gt, 14025883347)) 994 guc_prevent_fw_dma_failure_on_reset(guc); 995 996 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 997 998 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 999 if (ret) { 1000 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 1001 goto err_out; 1002 } 1003 1004 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 1005 if (!(guc_status & GS_MIA_IN_RESET)) { 1006 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 1007 guc_status); 1008 ret = -EIO; 1009 goto err_out; 1010 } 1011 1012 return 0; 1013 1014 err_out: 1015 1016 return ret; 1017 } 1018 1019 static void guc_prepare_xfer(struct xe_guc *guc) 1020 { 1021 struct xe_gt *gt = guc_to_gt(guc); 1022 struct xe_mmio *mmio = >->mmio; 1023 struct xe_device *xe = guc_to_xe(guc); 1024 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 1025 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 1026 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 1027 GUC_ENABLE_MIA_CLOCK_GATING; 1028 1029 if (GRAPHICS_VERx100(xe) < 1250) 1030 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 1031 GUC_ENABLE_MIA_CACHING; 1032 1033 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 1034 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 1035 1036 /* Must program this register before loading the ucode with DMA */ 1037 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 1038 1039 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 1040 1041 /* Make sure GuC receives ARAT interrupts */ 1042 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 1043 } 1044 1045 /* 1046 * Supporting MMIO & in memory RSA 1047 */ 1048 static int guc_xfer_rsa(struct xe_guc *guc) 1049 { 1050 struct xe_gt *gt = guc_to_gt(guc); 1051 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 1052 size_t copied; 1053 int i; 1054 1055 if (guc->fw.rsa_size > 256) { 1056 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 1057 xe_uc_fw_rsa_offset(&guc->fw); 1058 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 1059 return 0; 1060 } 1061 1062 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 1063 if (copied < sizeof(rsa)) 1064 return -ENOMEM; 1065 1066 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 1067 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 1068 1069 return 0; 1070 } 1071 1072 /* 1073 * Wait for the GuC to start up. 1074 * 1075 * Measurements indicate this should take no more than 20ms (assuming the GT 1076 * clock is at maximum frequency). However, thermal throttling and other issues 1077 * can prevent the clock hitting max and thus making the load take significantly 1078 * longer. Allow up to 3s as a safety margin in normal builds. For 1079 * CONFIG_DRM_XE_DEBUG allow up to 10s to account for slower execution, issues 1080 * in PCODE, driver, fan, etc. 1081 * 1082 * Keep checking the GUC_STATUS every 10ms with a debug message every 100 1083 * attempts as a "I'm slow, but alive" message. Regardless, if it takes more 1084 * than 200ms, emit a warning. 1085 */ 1086 1087 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 1088 #define GUC_LOAD_TIMEOUT_SEC 20 1089 #else 1090 #define GUC_LOAD_TIMEOUT_SEC 3 1091 #endif 1092 #define GUC_LOAD_TIME_WARN_MSEC 200 1093 1094 static void print_load_status_err(struct xe_gt *gt, u32 status) 1095 { 1096 struct xe_mmio *mmio = >->mmio; 1097 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1098 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1099 1100 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1101 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1102 bootrom, ukernel, 1103 REG_FIELD_GET(GS_MIA_MASK, status), 1104 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1105 1106 switch (bootrom) { 1107 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1108 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1109 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1110 break; 1111 case XE_BOOTROM_STATUS_RSA_FAILED: 1112 xe_gt_err(gt, "firmware signature verification failed\n"); 1113 break; 1114 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1115 xe_gt_err(gt, "firmware production part check failure\n"); 1116 break; 1117 } 1118 1119 switch (ukernel) { 1120 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1121 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1122 break; 1123 case XE_GUC_LOAD_STATUS_EXCEPTION: 1124 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1125 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1126 break; 1127 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1128 xe_gt_err(gt, "illegal init/ADS data\n"); 1129 break; 1130 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1131 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1132 break; 1133 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1134 xe_gt_err(gt, "illegal workaround KLV data\n"); 1135 break; 1136 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1137 xe_gt_err(gt, "illegal feature flag specified\n"); 1138 break; 1139 } 1140 } 1141 1142 /* 1143 * Check GUC_STATUS looking for known terminal states (either completion or 1144 * failure) of either the microkernel status field or the boot ROM status field. 1145 * 1146 * Returns 1 for successful completion, -1 for failure and 0 for any 1147 * intermediate state. 1148 */ 1149 static int guc_load_done(struct xe_gt *gt, u32 *status, u32 *tries) 1150 { 1151 u32 ukernel, bootrom; 1152 1153 *status = xe_mmio_read32(>->mmio, GUC_STATUS); 1154 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status); 1155 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status); 1156 1157 switch (ukernel) { 1158 case XE_GUC_LOAD_STATUS_READY: 1159 return 1; 1160 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 1161 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 1162 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 1163 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 1164 case XE_GUC_LOAD_STATUS_BOOTROM_VERSION_MISMATCH: 1165 case XE_GUC_LOAD_STATUS_DPC_ERROR: 1166 case XE_GUC_LOAD_STATUS_EXCEPTION: 1167 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1168 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 1169 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1170 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1171 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1172 return -1; 1173 } 1174 1175 switch (bootrom) { 1176 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1177 case XE_BOOTROM_STATUS_RSA_FAILED: 1178 case XE_BOOTROM_STATUS_PAVPC_FAILED: 1179 case XE_BOOTROM_STATUS_WOPCM_FAILED: 1180 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 1181 case XE_BOOTROM_STATUS_JUMP_FAILED: 1182 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 1183 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 1184 case XE_BOOTROM_STATUS_EXCEPTION: 1185 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1186 return -1; 1187 } 1188 1189 if (++*tries >= 100) { 1190 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1191 1192 *tries = 0; 1193 xe_gt_dbg(gt, "GuC load still in progress, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 1194 xe_guc_pc_get_act_freq(guc_pc), 1195 xe_guc_pc_get_cur_freq_fw(guc_pc), 1196 *status, ukernel, bootrom); 1197 } 1198 1199 return 0; 1200 } 1201 1202 static int guc_wait_ucode(struct xe_guc *guc) 1203 { 1204 struct xe_gt *gt = guc_to_gt(guc); 1205 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1206 u32 before_freq, act_freq, cur_freq; 1207 u32 status = 0, tries = 0; 1208 int load_result, ret; 1209 ktime_t before; 1210 u64 delta_ms; 1211 1212 before_freq = xe_guc_pc_get_act_freq(guc_pc); 1213 before = ktime_get(); 1214 1215 ret = poll_timeout_us(load_result = guc_load_done(gt, &status, &tries), load_result, 1216 10 * USEC_PER_MSEC, 1217 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false); 1218 1219 delta_ms = ktime_to_ms(ktime_sub(ktime_get(), before)); 1220 act_freq = xe_guc_pc_get_act_freq(guc_pc); 1221 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc); 1222 1223 if (ret || load_result <= 0) { 1224 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n", 1225 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1226 xe_guc_pc_get_cur_freq_fw(guc_pc)); 1227 print_load_status_err(gt, status); 1228 1229 return -EPROTO; 1230 } 1231 1232 if (delta_ms > GUC_LOAD_TIME_WARN_MSEC) { 1233 xe_gt_warn(gt, "GuC load: excessive init time: %lldms! [status = 0x%08X]\n", 1234 delta_ms, status); 1235 xe_gt_warn(gt, "GuC load: excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1236 act_freq, cur_freq, before_freq, 1237 xe_gt_throttle_get_limit_reasons(gt)); 1238 } else { 1239 xe_gt_dbg(gt, "GuC load: init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X\n", 1240 delta_ms, act_freq, cur_freq, before_freq, status); 1241 } 1242 1243 return 0; 1244 } 1245 ALLOW_ERROR_INJECTION(guc_wait_ucode, ERRNO); 1246 1247 static int __xe_guc_upload(struct xe_guc *guc) 1248 { 1249 int ret; 1250 1251 /* Raise GT freq to speed up HuC/GuC load */ 1252 xe_guc_pc_raise_unslice(&guc->pc); 1253 1254 guc_write_params(guc); 1255 guc_prepare_xfer(guc); 1256 1257 /* 1258 * Note that GuC needs the CSS header plus uKernel code to be copied 1259 * by the DMA engine in one operation, whereas the RSA signature is 1260 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1261 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1262 * size > 256). The RSA size and therefore the way we provide it to the 1263 * HW is fixed for each platform and hard-coded in the bootrom. 1264 */ 1265 ret = guc_xfer_rsa(guc); 1266 if (ret) 1267 goto out; 1268 /* 1269 * Current uCode expects the code to be loaded at 8k; locations below 1270 * this are used for the stack. 1271 */ 1272 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1273 if (ret) 1274 goto out; 1275 1276 /* Wait for authentication */ 1277 ret = guc_wait_ucode(guc); 1278 if (ret) 1279 goto out; 1280 1281 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1282 return 0; 1283 1284 out: 1285 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1286 return ret; 1287 } 1288 1289 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1290 { 1291 struct xe_gt *gt = guc_to_gt(guc); 1292 int ret; 1293 1294 ret = xe_guc_hwconfig_init(guc); 1295 if (ret) 1296 return ret; 1297 1298 ret = xe_guc_enable_communication(guc); 1299 if (ret) 1300 return ret; 1301 1302 ret = xe_gt_sriov_vf_connect(gt); 1303 if (ret) 1304 goto err_out; 1305 1306 ret = xe_gt_sriov_vf_query_runtime(gt); 1307 if (ret) 1308 goto err_out; 1309 1310 return 0; 1311 1312 err_out: 1313 xe_guc_sanitize(guc); 1314 return ret; 1315 } 1316 1317 /** 1318 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1319 * @guc: The GuC object 1320 * 1321 * This function uploads a minimal GuC that does not support submissions but 1322 * in a state where the hwconfig table can be read. Next, it reads and parses 1323 * the hwconfig table so it can be used for subsequent steps in the driver load. 1324 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1325 * 1326 * Return: 0 on success, negative error code on error. 1327 */ 1328 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1329 { 1330 int ret; 1331 1332 if (IS_SRIOV_VF(guc_to_xe(guc))) 1333 return vf_guc_min_load_for_hwconfig(guc); 1334 1335 xe_guc_ads_populate_minimal(&guc->ads); 1336 1337 xe_guc_pc_init_early(&guc->pc); 1338 1339 ret = __xe_guc_upload(guc); 1340 if (ret) 1341 return ret; 1342 1343 ret = xe_guc_hwconfig_init(guc); 1344 if (ret) 1345 return ret; 1346 1347 ret = xe_guc_enable_communication(guc); 1348 if (ret) 1349 return ret; 1350 1351 return 0; 1352 } 1353 1354 int xe_guc_upload(struct xe_guc *guc) 1355 { 1356 struct xe_gt *gt = guc_to_gt(guc); 1357 1358 xe_guc_ads_populate(&guc->ads); 1359 1360 if (xe_guc_using_main_gamctrl_queues(guc)) 1361 xe_mmio_write32(>->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT); 1362 1363 return __xe_guc_upload(guc); 1364 } 1365 1366 static void guc_handle_mmio_msg(struct xe_guc *guc) 1367 { 1368 struct xe_gt *gt = guc_to_gt(guc); 1369 u32 msg; 1370 1371 if (IS_SRIOV_VF(guc_to_xe(guc))) 1372 return; 1373 1374 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1375 1376 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1377 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1378 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1379 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1380 1381 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1382 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1383 1384 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1385 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1386 } 1387 1388 static void guc_enable_irq(struct xe_guc *guc) 1389 { 1390 struct xe_gt *gt = guc_to_gt(guc); 1391 u32 events = xe_gt_is_media_type(gt) ? 1392 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1393 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1394 1395 /* Primary GuC and media GuC share a single enable bit */ 1396 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1397 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1398 1399 /* 1400 * There are separate mask bits for primary and media GuCs, so use 1401 * a RMW operation to avoid clobbering the other GuC's setting. 1402 */ 1403 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1404 } 1405 1406 int xe_guc_enable_communication(struct xe_guc *guc) 1407 { 1408 struct xe_device *xe = guc_to_xe(guc); 1409 int err; 1410 1411 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1412 struct xe_gt *gt = guc_to_gt(guc); 1413 struct xe_tile *tile = gt_to_tile(gt); 1414 1415 err = xe_memirq_init_guc(&tile->memirq, guc); 1416 if (err) 1417 return err; 1418 } else { 1419 guc_enable_irq(guc); 1420 } 1421 1422 err = xe_guc_ct_enable(&guc->ct); 1423 if (err) 1424 return err; 1425 1426 guc_handle_mmio_msg(guc); 1427 1428 return 0; 1429 } 1430 1431 /** 1432 * xe_guc_softreset() - Soft reset GuC 1433 * @guc: The GuC object 1434 * 1435 * Send soft reset command to GuC through mmio send. 1436 * 1437 * Return: 0 if success, otherwise error code 1438 */ 1439 int xe_guc_softreset(struct xe_guc *guc) 1440 { 1441 u32 action[] = { 1442 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1443 }; 1444 int ret; 1445 1446 if (!xe_uc_fw_is_running(&guc->fw)) 1447 return 0; 1448 1449 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1450 if (ret) 1451 return ret; 1452 1453 return 0; 1454 } 1455 1456 int xe_guc_suspend(struct xe_guc *guc) 1457 { 1458 struct xe_gt *gt = guc_to_gt(guc); 1459 int ret; 1460 1461 ret = xe_guc_softreset(guc); 1462 if (ret) { 1463 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1464 return ret; 1465 } 1466 1467 xe_guc_sanitize(guc); 1468 return 0; 1469 } 1470 1471 void xe_guc_notify(struct xe_guc *guc) 1472 { 1473 struct xe_gt *gt = guc_to_gt(guc); 1474 const u32 default_notify_data = 0; 1475 1476 /* 1477 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1478 * additional payload data to the GuC but this capability is not 1479 * used by the firmware yet. Use default value in the meantime. 1480 */ 1481 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1482 } 1483 1484 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1485 { 1486 u32 action[] = { 1487 XE_GUC_ACTION_AUTHENTICATE_HUC, 1488 rsa_addr 1489 }; 1490 1491 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1492 } 1493 1494 #define MAX_RETRIES_ON_FLR 2 1495 #define MIN_SLEEP_MS_ON_FLR 256 1496 1497 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1498 u32 len, u32 *response_buf) 1499 { 1500 struct xe_device *xe = guc_to_xe(guc); 1501 struct xe_gt *gt = guc_to_gt(guc); 1502 struct xe_mmio *mmio = >->mmio; 1503 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1504 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1505 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1506 unsigned int sleep_period_ms = 1; 1507 unsigned int lost = 0; 1508 u32 header; 1509 int ret; 1510 int i; 1511 1512 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1513 1514 xe_assert(xe, len); 1515 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1516 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1517 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1518 GUC_HXG_ORIGIN_HOST); 1519 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1520 GUC_HXG_TYPE_REQUEST); 1521 1522 retry: 1523 /* Not in critical data-path, just do if else for GT type */ 1524 if (xe_gt_is_media_type(gt)) { 1525 for (i = 0; i < len; ++i) 1526 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1527 request[i]); 1528 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1529 } else { 1530 for (i = 0; i < len; ++i) 1531 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1532 request[i]); 1533 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1534 } 1535 1536 xe_guc_notify(guc); 1537 1538 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1539 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1540 50000, &header, false); 1541 if (ret) { 1542 /* scratch registers might be cleared during FLR, try once more */ 1543 if (!header) { 1544 if (++lost > MAX_RETRIES_ON_FLR) { 1545 xe_gt_err(gt, "GuC mmio request %#x: lost, too many retries %u\n", 1546 request[0], lost); 1547 return -ENOLINK; 1548 } 1549 xe_gt_dbg(gt, "GuC mmio request %#x: lost, trying again\n", request[0]); 1550 xe_sleep_relaxed_ms(MIN_SLEEP_MS_ON_FLR); 1551 goto retry; 1552 } 1553 timeout: 1554 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1555 request[0], header); 1556 return ret; 1557 } 1558 1559 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1560 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1561 /* 1562 * Once we got a BUSY reply we must wait again for the final 1563 * response but this time we can't use ORIGIN mask anymore. 1564 * To spot a right change in the reply, we take advantage that 1565 * response SUCCESS and FAILURE differ only by the single bit 1566 * and all other bits are set and can be used as a new mask. 1567 */ 1568 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1569 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1570 1571 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1572 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1573 1574 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1575 2000000, &header, false); 1576 1577 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1578 GUC_HXG_ORIGIN_GUC)) 1579 goto proto; 1580 if (unlikely(ret)) { 1581 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1582 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1583 goto proto; 1584 goto timeout; 1585 } 1586 } 1587 1588 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1589 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1590 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1591 1592 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1593 request[0], reason); 1594 1595 xe_sleep_exponential_ms(&sleep_period_ms, 256); 1596 goto retry; 1597 } 1598 1599 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1600 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1601 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1602 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1603 1604 if (unlikely(error == XE_GUC_RESPONSE_VF_MIGRATED)) { 1605 xe_gt_dbg(gt, "GuC mmio request %#x rejected due to MIGRATION (hint %#x)\n", 1606 request[0], hint); 1607 return -EREMCHG; 1608 } 1609 1610 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1611 request[0], error, hint); 1612 return -ENXIO; 1613 } 1614 1615 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1616 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1617 proto: 1618 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1619 request[0], header); 1620 return -EPROTO; 1621 } 1622 1623 /* Just copy entire possible message response */ 1624 if (response_buf) { 1625 response_buf[0] = header; 1626 1627 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1628 reply_reg.addr += sizeof(u32); 1629 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1630 } 1631 } 1632 1633 /* Use data from the GuC response as our return value */ 1634 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1635 } 1636 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1637 1638 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1639 { 1640 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1641 } 1642 1643 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1644 { 1645 struct xe_device *xe = guc_to_xe(guc); 1646 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1647 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1648 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1649 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1650 GUC_ACTION_HOST2GUC_SELF_CFG), 1651 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1652 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1653 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1654 lower_32_bits(val)), 1655 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1656 upper_32_bits(val)), 1657 }; 1658 int ret; 1659 1660 xe_assert(xe, len <= 2); 1661 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1662 1663 /* Self config must go over MMIO */ 1664 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1665 1666 if (unlikely(ret < 0)) 1667 return ret; 1668 if (unlikely(ret > 1)) 1669 return -EPROTO; 1670 if (unlikely(!ret)) 1671 return -ENOKEY; 1672 1673 return 0; 1674 } 1675 1676 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1677 { 1678 return guc_self_cfg(guc, key, 1, val); 1679 } 1680 1681 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1682 { 1683 return guc_self_cfg(guc, key, 2, val); 1684 } 1685 1686 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1687 { 1688 struct xe_gt *gt = guc_to_gt(guc); 1689 1690 if (IS_SRIOV_VF(gt_to_xe(gt))) 1691 xe_gt_sriov_vf_migrated_event_handler(gt); 1692 } 1693 1694 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1695 { 1696 if (iir & GUC_INTR_GUC2HOST) 1697 xe_guc_ct_irq_handler(&guc->ct); 1698 1699 if (iir & GUC_INTR_SW_INT_0) 1700 xe_guc_sw_0_irq_handler(guc); 1701 } 1702 1703 void xe_guc_sanitize(struct xe_guc *guc) 1704 { 1705 xe_uc_fw_sanitize(&guc->fw); 1706 xe_guc_ct_disable(&guc->ct); 1707 xe_guc_submit_disable(guc); 1708 } 1709 1710 int xe_guc_reset_prepare(struct xe_guc *guc) 1711 { 1712 return xe_guc_submit_reset_prepare(guc); 1713 } 1714 1715 void xe_guc_reset_wait(struct xe_guc *guc) 1716 { 1717 xe_guc_submit_reset_wait(guc); 1718 } 1719 1720 void xe_guc_stop_prepare(struct xe_guc *guc) 1721 { 1722 if (!IS_SRIOV_VF(guc_to_xe(guc))) 1723 xe_guc_pc_stop(&guc->pc); 1724 } 1725 1726 void xe_guc_stop(struct xe_guc *guc) 1727 { 1728 xe_guc_ct_stop(&guc->ct); 1729 1730 xe_guc_submit_stop(guc); 1731 } 1732 1733 int xe_guc_start(struct xe_guc *guc) 1734 { 1735 return xe_guc_submit_start(guc); 1736 } 1737 1738 /** 1739 * xe_guc_runtime_suspend() - GuC runtime suspend 1740 * @guc: The GuC object 1741 * 1742 * Stop further runs of submission tasks on given GuC and runtime suspend 1743 * GuC CT. 1744 */ 1745 void xe_guc_runtime_suspend(struct xe_guc *guc) 1746 { 1747 xe_guc_submit_pause(guc); 1748 xe_guc_submit_disable(guc); 1749 xe_guc_ct_runtime_suspend(&guc->ct); 1750 } 1751 1752 /** 1753 * xe_guc_runtime_resume() - GuC runtime resume 1754 * @guc: The GuC object 1755 * 1756 * Runtime resume GuC CT and allow further runs of submission tasks on 1757 * given GuC. 1758 */ 1759 void xe_guc_runtime_resume(struct xe_guc *guc) 1760 { 1761 /* 1762 * Runtime PM flows are not applicable for VFs, so it's safe to 1763 * directly enable IRQ. 1764 */ 1765 guc_enable_irq(guc); 1766 1767 xe_guc_ct_runtime_resume(&guc->ct); 1768 xe_guc_submit_enable(guc); 1769 xe_guc_submit_unpause(guc); 1770 } 1771 1772 int xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1773 { 1774 struct xe_gt *gt = guc_to_gt(guc); 1775 u32 status; 1776 int i; 1777 1778 xe_uc_fw_print(&guc->fw, p); 1779 1780 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1781 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 1782 if (!fw_ref.domains) 1783 return -EIO; 1784 1785 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1786 1787 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1788 drm_printf(p, "\tBootrom status = 0x%x\n", 1789 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1790 drm_printf(p, "\tuKernel status = 0x%x\n", 1791 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1792 drm_printf(p, "\tMIA Core status = 0x%x\n", 1793 REG_FIELD_GET(GS_MIA_MASK, status)); 1794 drm_printf(p, "\tLog level = %d\n", 1795 xe_guc_log_get_level(&guc->log)); 1796 1797 drm_puts(p, "\nScratch registers:\n"); 1798 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1799 drm_printf(p, "\t%2d: \t0x%x\n", 1800 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1801 } 1802 } 1803 1804 drm_puts(p, "\n"); 1805 xe_guc_ct_print(&guc->ct, p, false); 1806 1807 drm_puts(p, "\n"); 1808 xe_guc_submit_print(guc, p); 1809 1810 return 0; 1811 } 1812 1813 /** 1814 * xe_guc_declare_wedged() - Declare GuC wedged 1815 * @guc: the GuC object 1816 * 1817 * Wedge the GuC which stops all submission, saves desired debug state, and 1818 * cleans up anything which could timeout. 1819 */ 1820 void xe_guc_declare_wedged(struct xe_guc *guc) 1821 { 1822 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1823 1824 xe_guc_reset_prepare(guc); 1825 xe_guc_ct_stop(&guc->ct); 1826 xe_guc_submit_wedge(guc); 1827 } 1828 1829 /** 1830 * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use. 1831 * @guc: The GuC object 1832 * 1833 * For Xe3p and beyond, we want to program the hardware to use the 1834 * "Main GAMCTRL queue" rather than the legacy queue before we upload 1835 * the GuC firmware. This will allow the GuC to use a new set of 1836 * registers for pagefault handling and avoid some unnecessary 1837 * complications with MCR register range handling. 1838 * 1839 * Return: true if can use new main gamctrl queues. 1840 */ 1841 bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc) 1842 { 1843 struct xe_gt *gt = guc_to_gt(guc); 1844 1845 /* 1846 * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3 1847 * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID 1848 * inform the IP version of the subunits. 1849 */ 1850 if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) { 1851 u32 val = xe_mmio_read32(>->mmio, GMD_ID); 1852 u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val); 1853 1854 if (!subip) 1855 return true; 1856 1857 xe_gt_WARN(gt, subip != 1, 1858 "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n", 1859 subip); 1860 1861 return false; 1862 } 1863 1864 return GT_VER(gt) >= 35; 1865 } 1866 1867 bool xe_guc_has_paging_engine(struct xe_guc *guc) 1868 { 1869 struct xe_gt *gt = guc_to_gt(guc); 1870 struct xe_device *xe = gt_to_xe(gt); 1871 1872 /* 1873 * On newer platforms the GuC now has a dedicated engine class for the 1874 * special PAGING engine, which is the driver reserved BCS engine used 1875 * for KMD paging/binding operations. GuC requires KMD to refer to this 1876 * using the special PAGING engine class. Note that there is no new hw 1877 * engine here, this is purely a sw view in the GuC itself, which we 1878 * need to respect. 1879 */ 1880 1881 if (IS_SRIOV_VF(xe)) 1882 return xe_gt_sriov_vf_paging_engines(gt); 1883 1884 return xe->info.platform >= XE_NOVALAKE_S && 1885 GUC_FIRMWARE_VER_AT_LEAST(guc, 70, 69, 0); 1886 } 1887 1888 /** 1889 * xe_hwe_guc_logical_instance - Get the GuC-aligned logical instance of a 1890 * hardware engine. 1891 * @hwe: Hardware engine. 1892 * 1893 * For GuC backend usage, we should no longer use the raw logical instance 1894 * directly. This helper must be used to retrieve the logical instance of the 1895 * hardware engine, taking care of any necessary adjustments (such as the GuC 1896 * PAGING engine mapping). This is assumed to be used in conjunction with the 1897 * GuC engine class. 1898 * 1899 * Return: Logical instance, taking into account for stuff like GuC PAGING 1900 * engine mapping. 1901 */ 1902 u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe) 1903 { 1904 struct xe_gt *gt = hwe->gt; 1905 1906 if (xe_guc_has_paging_engine(&hwe->gt->uc.guc) && 1907 xe_gt_is_usm_hwe(gt, hwe)) { 1908 int shift = gt->usm.paging_hwe0->logical_instance; 1909 1910 xe_gt_assert(gt, shift <= hwe->logical_instance); 1911 1912 /* GUC_PAGING_CLASS:guc_logical_instance */ 1913 return hwe->logical_instance - shift; 1914 } 1915 1916 return hwe->logical_instance; 1917 } 1918 1919 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1920 #include "tests/xe_guc_g2g_test.c" 1921 #endif 1922