1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <drm/drm_managed.h> 9 10 #include <generated/xe_wa_oob.h> 11 12 #include "abi/guc_actions_abi.h" 13 #include "abi/guc_errors_abi.h" 14 #include "regs/xe_gt_regs.h" 15 #include "regs/xe_gtt_defs.h" 16 #include "regs/xe_guc_regs.h" 17 #include "xe_bo.h" 18 #include "xe_device.h" 19 #include "xe_force_wake.h" 20 #include "xe_gt.h" 21 #include "xe_gt_printk.h" 22 #include "xe_gt_sriov_vf.h" 23 #include "xe_gt_throttle.h" 24 #include "xe_guc_ads.h" 25 #include "xe_guc_ct.h" 26 #include "xe_guc_db_mgr.h" 27 #include "xe_guc_hwconfig.h" 28 #include "xe_guc_log.h" 29 #include "xe_guc_pc.h" 30 #include "xe_guc_relay.h" 31 #include "xe_guc_submit.h" 32 #include "xe_memirq.h" 33 #include "xe_mmio.h" 34 #include "xe_platform_types.h" 35 #include "xe_sriov.h" 36 #include "xe_uc.h" 37 #include "xe_uc_fw.h" 38 #include "xe_wa.h" 39 #include "xe_wopcm.h" 40 41 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 42 struct xe_bo *bo) 43 { 44 struct xe_device *xe = guc_to_xe(guc); 45 u32 addr = xe_bo_ggtt_addr(bo); 46 47 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 48 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 49 xe_assert(xe, addr < GUC_GGTT_TOP); 50 xe_assert(xe, bo->size <= GUC_GGTT_TOP - addr); 51 52 return addr; 53 } 54 55 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 56 { 57 u32 level = xe_guc_log_get_level(&guc->log); 58 u32 flags = 0; 59 60 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 61 flags |= GUC_LOG_DISABLED; 62 else 63 flags |= GUC_LOG_LEVEL_TO_VERBOSITY(level) << 64 GUC_LOG_VERBOSITY_SHIFT; 65 66 return flags; 67 } 68 69 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 70 { 71 u32 flags = 0; 72 73 if (!guc_to_xe(guc)->info.skip_guc_pc) 74 flags |= GUC_CTL_ENABLE_SLPC; 75 76 return flags; 77 } 78 79 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 80 { 81 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 82 u32 flags; 83 84 #if (((CRASH_BUFFER_SIZE) % SZ_1M) == 0) 85 #define LOG_UNIT SZ_1M 86 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 87 #else 88 #define LOG_UNIT SZ_4K 89 #define LOG_FLAG 0 90 #endif 91 92 #if (((CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 93 #define CAPTURE_UNIT SZ_1M 94 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 95 #else 96 #define CAPTURE_UNIT SZ_4K 97 #define CAPTURE_FLAG 0 98 #endif 99 100 BUILD_BUG_ON(!CRASH_BUFFER_SIZE); 101 BUILD_BUG_ON(!IS_ALIGNED(CRASH_BUFFER_SIZE, LOG_UNIT)); 102 BUILD_BUG_ON(!DEBUG_BUFFER_SIZE); 103 BUILD_BUG_ON(!IS_ALIGNED(DEBUG_BUFFER_SIZE, LOG_UNIT)); 104 BUILD_BUG_ON(!CAPTURE_BUFFER_SIZE); 105 BUILD_BUG_ON(!IS_ALIGNED(CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 106 107 BUILD_BUG_ON((CRASH_BUFFER_SIZE / LOG_UNIT - 1) > 108 (GUC_LOG_CRASH_MASK >> GUC_LOG_CRASH_SHIFT)); 109 BUILD_BUG_ON((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) > 110 (GUC_LOG_DEBUG_MASK >> GUC_LOG_DEBUG_SHIFT)); 111 BUILD_BUG_ON((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) > 112 (GUC_LOG_CAPTURE_MASK >> GUC_LOG_CAPTURE_SHIFT)); 113 114 flags = GUC_LOG_VALID | 115 GUC_LOG_NOTIFY_ON_HALF_FULL | 116 CAPTURE_FLAG | 117 LOG_FLAG | 118 ((CRASH_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_CRASH_SHIFT) | 119 ((DEBUG_BUFFER_SIZE / LOG_UNIT - 1) << GUC_LOG_DEBUG_SHIFT) | 120 ((CAPTURE_BUFFER_SIZE / CAPTURE_UNIT - 1) << 121 GUC_LOG_CAPTURE_SHIFT) | 122 (offset << GUC_LOG_BUF_ADDR_SHIFT); 123 124 #undef LOG_UNIT 125 #undef LOG_FLAG 126 #undef CAPTURE_UNIT 127 #undef CAPTURE_FLAG 128 129 return flags; 130 } 131 132 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 133 { 134 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 135 u32 flags = ads << GUC_ADS_ADDR_SHIFT; 136 137 return flags; 138 } 139 140 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 141 { 142 struct xe_device *xe = guc_to_xe(guc); 143 struct xe_gt *gt = guc_to_gt(guc); 144 u32 flags = 0; 145 146 if (XE_WA(gt, 22012773006)) 147 flags |= GUC_WA_POLLCS; 148 149 if (XE_WA(gt, 14014475959)) 150 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 151 152 if (XE_WA(gt, 22011391025)) 153 flags |= GUC_WA_DUAL_QUEUE; 154 155 /* 156 * Wa_22011802037: FIXME - there's more to be done than simply setting 157 * this flag: make sure each CS is stopped when preparing for GT reset 158 * and wait for pending MI_FW. 159 */ 160 if (GRAPHICS_VERx100(xe) < 1270) 161 flags |= GUC_WA_PRE_PARSER; 162 163 if (XE_WA(gt, 22012727170) || XE_WA(gt, 22012727685)) 164 flags |= GUC_WA_CONTEXT_ISOLATION; 165 166 if (XE_WA(gt, 18020744125) && 167 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 168 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 169 170 if (XE_WA(gt, 1509372804)) 171 flags |= GUC_WA_RENDER_RST_RC6_EXIT; 172 173 if (XE_WA(gt, 14018913170)) 174 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 175 176 return flags; 177 } 178 179 static u32 guc_ctl_devid(struct xe_guc *guc) 180 { 181 struct xe_device *xe = guc_to_xe(guc); 182 183 return (((u32)xe->info.devid) << 16) | xe->info.revid; 184 } 185 186 static void guc_print_params(struct xe_guc *guc) 187 { 188 struct xe_gt *gt = guc_to_gt(guc); 189 u32 *params = guc->params; 190 int i; 191 192 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 193 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 194 195 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 196 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 197 } 198 199 static void guc_init_params(struct xe_guc *guc) 200 { 201 u32 *params = guc->params; 202 203 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 204 params[GUC_CTL_FEATURE] = 0; 205 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 206 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 207 params[GUC_CTL_WA] = 0; 208 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 209 210 guc_print_params(guc); 211 } 212 213 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 214 { 215 u32 *params = guc->params; 216 217 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 218 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 219 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 220 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 221 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 222 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 223 224 guc_print_params(guc); 225 } 226 227 /* 228 * Initialize the GuC parameter block before starting the firmware 229 * transfer. These parameters are read by the firmware on startup 230 * and cannot be changed thereafter. 231 */ 232 static void guc_write_params(struct xe_guc *guc) 233 { 234 struct xe_gt *gt = guc_to_gt(guc); 235 int i; 236 237 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 238 239 xe_mmio_write32(gt, SOFT_SCRATCH(0), 0); 240 241 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 242 xe_mmio_write32(gt, SOFT_SCRATCH(1 + i), guc->params[i]); 243 } 244 245 static void guc_fini_hw(void *arg) 246 { 247 struct xe_guc *guc = arg; 248 struct xe_gt *gt = guc_to_gt(guc); 249 250 xe_gt_WARN_ON(gt, xe_force_wake_get(gt_to_fw(gt), XE_FORCEWAKE_ALL)); 251 xe_uc_fini_hw(&guc_to_gt(guc)->uc); 252 xe_force_wake_put(gt_to_fw(gt), XE_FORCEWAKE_ALL); 253 } 254 255 /** 256 * xe_guc_comm_init_early - early initialization of GuC communication 257 * @guc: the &xe_guc to initialize 258 * 259 * Must be called prior to first MMIO communication with GuC firmware. 260 */ 261 void xe_guc_comm_init_early(struct xe_guc *guc) 262 { 263 struct xe_gt *gt = guc_to_gt(guc); 264 265 if (xe_gt_is_media_type(gt)) 266 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 267 else 268 guc->notify_reg = GUC_HOST_INTERRUPT; 269 } 270 271 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 272 { 273 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 274 struct xe_device *xe = guc_to_xe(guc); 275 int ret; 276 277 if (!IS_DGFX(guc_to_xe(guc))) 278 return 0; 279 280 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 281 if (ret) 282 return ret; 283 284 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 285 if (ret) 286 return ret; 287 288 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 289 if (ret) 290 return ret; 291 292 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ct.bo); 293 if (ret) 294 return ret; 295 296 return 0; 297 } 298 299 static int vf_guc_init(struct xe_guc *guc) 300 { 301 int err; 302 303 xe_guc_comm_init_early(guc); 304 305 err = xe_guc_ct_init(&guc->ct); 306 if (err) 307 return err; 308 309 err = xe_guc_relay_init(&guc->relay); 310 if (err) 311 return err; 312 313 return 0; 314 } 315 316 int xe_guc_init(struct xe_guc *guc) 317 { 318 struct xe_device *xe = guc_to_xe(guc); 319 struct xe_gt *gt = guc_to_gt(guc); 320 int ret; 321 322 guc->fw.type = XE_UC_FW_TYPE_GUC; 323 ret = xe_uc_fw_init(&guc->fw); 324 if (ret) 325 goto out; 326 327 if (!xe_uc_fw_is_enabled(&guc->fw)) 328 return 0; 329 330 if (IS_SRIOV_VF(xe)) { 331 ret = vf_guc_init(guc); 332 if (ret) 333 goto out; 334 return 0; 335 } 336 337 ret = xe_guc_log_init(&guc->log); 338 if (ret) 339 goto out; 340 341 ret = xe_guc_ads_init(&guc->ads); 342 if (ret) 343 goto out; 344 345 ret = xe_guc_ct_init(&guc->ct); 346 if (ret) 347 goto out; 348 349 ret = xe_guc_relay_init(&guc->relay); 350 if (ret) 351 goto out; 352 353 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 354 if (ret) 355 goto out; 356 357 guc_init_params(guc); 358 359 xe_guc_comm_init_early(guc); 360 361 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 362 363 return 0; 364 365 out: 366 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 367 return ret; 368 } 369 370 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 371 { 372 int err; 373 374 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 375 if (err) 376 return err; 377 378 /* XXX xe_guc_db_mgr_init not needed for now */ 379 380 return 0; 381 } 382 383 /** 384 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 385 * @guc: The GuC object 386 * 387 * Return: 0 on success, negative error code on error. 388 */ 389 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 390 { 391 int ret; 392 393 if (IS_SRIOV_VF(guc_to_xe(guc))) 394 return vf_guc_init_post_hwconfig(guc); 395 396 ret = xe_guc_realloc_post_hwconfig(guc); 397 if (ret) 398 return ret; 399 400 guc_init_params_post_hwconfig(guc); 401 402 ret = xe_guc_submit_init(guc, ~0); 403 if (ret) 404 return ret; 405 406 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 407 if (ret) 408 return ret; 409 410 ret = xe_guc_pc_init(&guc->pc); 411 if (ret) 412 return ret; 413 414 return xe_guc_ads_init_post_hwconfig(&guc->ads); 415 } 416 417 int xe_guc_post_load_init(struct xe_guc *guc) 418 { 419 xe_guc_ads_populate_post_load(&guc->ads); 420 guc->submission_state.enabled = true; 421 422 return 0; 423 } 424 425 int xe_guc_reset(struct xe_guc *guc) 426 { 427 struct xe_gt *gt = guc_to_gt(guc); 428 u32 guc_status, gdrst; 429 int ret; 430 431 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 432 433 if (IS_SRIOV_VF(gt_to_xe(gt))) 434 return xe_gt_sriov_vf_bootstrap(gt); 435 436 xe_mmio_write32(gt, GDRST, GRDOM_GUC); 437 438 ret = xe_mmio_wait32(gt, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 439 if (ret) { 440 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 441 goto err_out; 442 } 443 444 guc_status = xe_mmio_read32(gt, GUC_STATUS); 445 if (!(guc_status & GS_MIA_IN_RESET)) { 446 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 447 guc_status); 448 ret = -EIO; 449 goto err_out; 450 } 451 452 return 0; 453 454 err_out: 455 456 return ret; 457 } 458 459 static void guc_prepare_xfer(struct xe_guc *guc) 460 { 461 struct xe_gt *gt = guc_to_gt(guc); 462 struct xe_device *xe = guc_to_xe(guc); 463 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 464 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 465 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 466 GUC_ENABLE_MIA_CLOCK_GATING; 467 468 if (GRAPHICS_VERx100(xe) < 1250) 469 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 470 GUC_ENABLE_MIA_CACHING; 471 472 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 473 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 474 475 /* Must program this register before loading the ucode with DMA */ 476 xe_mmio_write32(gt, GUC_SHIM_CONTROL, shim_flags); 477 478 xe_mmio_write32(gt, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 479 } 480 481 /* 482 * Supporting MMIO & in memory RSA 483 */ 484 static int guc_xfer_rsa(struct xe_guc *guc) 485 { 486 struct xe_gt *gt = guc_to_gt(guc); 487 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 488 size_t copied; 489 int i; 490 491 if (guc->fw.rsa_size > 256) { 492 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 493 xe_uc_fw_rsa_offset(&guc->fw); 494 xe_mmio_write32(gt, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 495 return 0; 496 } 497 498 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 499 if (copied < sizeof(rsa)) 500 return -ENOMEM; 501 502 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 503 xe_mmio_write32(gt, UOS_RSA_SCRATCH(i), rsa[i]); 504 505 return 0; 506 } 507 508 /* 509 * Check a previously read GuC status register (GUC_STATUS) looking for 510 * known terminal states (either completion or failure) of either the 511 * microkernel status field or the boot ROM status field. Returns +1 for 512 * successful completion, -1 for failure and 0 for any intermediate state. 513 */ 514 static int guc_load_done(u32 status) 515 { 516 u32 uk_val = REG_FIELD_GET(GS_UKERNEL_MASK, status); 517 u32 br_val = REG_FIELD_GET(GS_BOOTROM_MASK, status); 518 519 switch (uk_val) { 520 case XE_GUC_LOAD_STATUS_READY: 521 return 1; 522 523 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 524 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 525 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 526 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 527 case XE_GUC_LOAD_STATUS_DPC_ERROR: 528 case XE_GUC_LOAD_STATUS_EXCEPTION: 529 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 530 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 531 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 532 return -1; 533 } 534 535 switch (br_val) { 536 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 537 case XE_BOOTROM_STATUS_RSA_FAILED: 538 case XE_BOOTROM_STATUS_PAVPC_FAILED: 539 case XE_BOOTROM_STATUS_WOPCM_FAILED: 540 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 541 case XE_BOOTROM_STATUS_JUMP_FAILED: 542 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 543 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 544 case XE_BOOTROM_STATUS_EXCEPTION: 545 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 546 return -1; 547 } 548 549 return 0; 550 } 551 552 static s32 guc_pc_get_cur_freq(struct xe_guc_pc *guc_pc) 553 { 554 u32 freq; 555 int ret = xe_guc_pc_get_cur_freq(guc_pc, &freq); 556 557 return ret ? ret : freq; 558 } 559 560 /* 561 * Wait for the GuC to start up. 562 * 563 * Measurements indicate this should take no more than 20ms (assuming the GT 564 * clock is at maximum frequency). However, thermal throttling and other issues 565 * can prevent the clock hitting max and thus making the load take significantly 566 * longer. Allow up to 200ms as a safety margin for real world worst case situations. 567 * 568 * However, bugs anywhere from KMD to GuC to PCODE to fan failure in a CI farm can 569 * lead to even longer times. E.g. if the GT is clamped to minimum frequency then 570 * the load times can be in the seconds range. So the timeout is increased for debug 571 * builds to ensure that problems can be correctly analysed. For release builds, the 572 * timeout is kept short so that users don't wait forever to find out that there is a 573 * problem. In either case, if the load took longer than is reasonable even with some 574 * 'sensible' throttling, then flag a warning because something is not right. 575 * 576 * Note that there is a limit on how long an individual usleep_range() can wait for, 577 * hence longer waits require wrapping a shorter wait in a loop. 578 * 579 * Note that the only reason an end user should hit the shorter timeout is in case of 580 * extreme thermal throttling. And a system that is that hot during boot is probably 581 * dead anyway! 582 */ 583 #if defined(CONFIG_DRM_XE_DEBUG) 584 #define GUC_LOAD_RETRY_LIMIT 20 585 #else 586 #define GUC_LOAD_RETRY_LIMIT 3 587 #endif 588 #define GUC_LOAD_TIME_WARN_MS 200 589 590 static void guc_wait_ucode(struct xe_guc *guc) 591 { 592 struct xe_gt *gt = guc_to_gt(guc); 593 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 594 ktime_t before, after, delta; 595 int load_done; 596 u32 status = 0; 597 int count = 0; 598 u64 delta_ms; 599 u32 before_freq; 600 601 before_freq = xe_guc_pc_get_act_freq(guc_pc); 602 before = ktime_get(); 603 /* 604 * Note, can't use any kind of timing information from the call to xe_mmio_wait. 605 * It could return a thousand intermediate stages at random times. Instead, must 606 * manually track the total time taken and locally implement the timeout. 607 */ 608 do { 609 u32 last_status = status & (GS_UKERNEL_MASK | GS_BOOTROM_MASK); 610 int ret; 611 612 /* 613 * Wait for any change (intermediate or terminal) in the status register. 614 * Note, the return value is a don't care. The only failure code is timeout 615 * but the timeouts need to be accumulated over all the intermediate partial 616 * timeouts rather than allowing a huge timeout each time. So basically, need 617 * to treat a timeout no different to a value change. 618 */ 619 ret = xe_mmio_wait32_not(gt, GUC_STATUS, GS_UKERNEL_MASK | GS_BOOTROM_MASK, 620 last_status, 1000 * 1000, &status, false); 621 if (ret < 0) 622 count++; 623 after = ktime_get(); 624 delta = ktime_sub(after, before); 625 delta_ms = ktime_to_ms(delta); 626 627 load_done = guc_load_done(status); 628 if (load_done != 0) 629 break; 630 631 if (delta_ms >= (GUC_LOAD_RETRY_LIMIT * 1000)) 632 break; 633 634 xe_gt_dbg(gt, "load still in progress, timeouts = %d, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 635 count, xe_guc_pc_get_act_freq(guc_pc), 636 guc_pc_get_cur_freq(guc_pc), status, 637 REG_FIELD_GET(GS_BOOTROM_MASK, status), 638 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 639 } while (1); 640 641 if (load_done != 1) { 642 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 643 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 644 645 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz), done = %d\n", 646 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 647 guc_pc_get_cur_freq(guc_pc), load_done); 648 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 649 REG_FIELD_GET(GS_MIA_IN_RESET, status), 650 bootrom, ukernel, 651 REG_FIELD_GET(GS_MIA_MASK, status), 652 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 653 654 switch (bootrom) { 655 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 656 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 657 xe_mmio_read32(gt, GUC_HEADER_INFO)); 658 break; 659 660 case XE_BOOTROM_STATUS_RSA_FAILED: 661 xe_gt_err(gt, "firmware signature verification failed\n"); 662 break; 663 664 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 665 xe_gt_err(gt, "firmware production part check failure\n"); 666 break; 667 } 668 669 switch (ukernel) { 670 case XE_GUC_LOAD_STATUS_EXCEPTION: 671 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 672 xe_mmio_read32(gt, SOFT_SCRATCH(13))); 673 break; 674 675 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 676 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 677 break; 678 679 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 680 xe_gt_err(gt, "still extracting hwconfig table.\n"); 681 break; 682 } 683 684 xe_device_declare_wedged(gt_to_xe(gt)); 685 } else if (delta_ms > GUC_LOAD_TIME_WARN_MS) { 686 xe_gt_warn(gt, "excessive init time: %lldms! [status = 0x%08X, timeouts = %d]\n", 687 delta_ms, status, count); 688 xe_gt_warn(gt, "excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 689 xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 690 before_freq, xe_gt_throttle_get_limit_reasons(gt)); 691 } else { 692 xe_gt_dbg(gt, "init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X, timeouts = %d\n", 693 delta_ms, xe_guc_pc_get_act_freq(guc_pc), guc_pc_get_cur_freq(guc_pc), 694 before_freq, status, count); 695 } 696 } 697 698 static int __xe_guc_upload(struct xe_guc *guc) 699 { 700 int ret; 701 702 guc_write_params(guc); 703 guc_prepare_xfer(guc); 704 705 /* 706 * Note that GuC needs the CSS header plus uKernel code to be copied 707 * by the DMA engine in one operation, whereas the RSA signature is 708 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 709 * register (if key size <= 256) or through a ggtt-pinned vma (if key 710 * size > 256). The RSA size and therefore the way we provide it to the 711 * HW is fixed for each platform and hard-coded in the bootrom. 712 */ 713 ret = guc_xfer_rsa(guc); 714 if (ret) 715 goto out; 716 /* 717 * Current uCode expects the code to be loaded at 8k; locations below 718 * this are used for the stack. 719 */ 720 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 721 if (ret) 722 goto out; 723 724 /* Wait for authentication */ 725 guc_wait_ucode(guc); 726 727 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 728 return 0; 729 730 out: 731 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 732 return 0 /* FIXME: ret, don't want to stop load currently */; 733 } 734 735 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 736 { 737 struct xe_gt *gt = guc_to_gt(guc); 738 int ret; 739 740 ret = xe_gt_sriov_vf_bootstrap(gt); 741 if (ret) 742 return ret; 743 744 ret = xe_gt_sriov_vf_query_config(gt); 745 if (ret) 746 return ret; 747 748 ret = xe_guc_hwconfig_init(guc); 749 if (ret) 750 return ret; 751 752 ret = xe_guc_enable_communication(guc); 753 if (ret) 754 return ret; 755 756 ret = xe_gt_sriov_vf_connect(gt); 757 if (ret) 758 return ret; 759 760 ret = xe_gt_sriov_vf_query_runtime(gt); 761 if (ret) 762 return ret; 763 764 return 0; 765 } 766 767 /** 768 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 769 * @guc: The GuC object 770 * 771 * This function uploads a minimal GuC that does not support submissions but 772 * in a state where the hwconfig table can be read. Next, it reads and parses 773 * the hwconfig table so it can be used for subsequent steps in the driver load. 774 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 775 * 776 * Return: 0 on success, negative error code on error. 777 */ 778 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 779 { 780 int ret; 781 782 if (IS_SRIOV_VF(guc_to_xe(guc))) 783 return vf_guc_min_load_for_hwconfig(guc); 784 785 xe_guc_ads_populate_minimal(&guc->ads); 786 787 /* Raise GT freq to speed up HuC/GuC load */ 788 xe_guc_pc_init_early(&guc->pc); 789 790 ret = __xe_guc_upload(guc); 791 if (ret) 792 return ret; 793 794 ret = xe_guc_hwconfig_init(guc); 795 if (ret) 796 return ret; 797 798 ret = xe_guc_enable_communication(guc); 799 if (ret) 800 return ret; 801 802 return 0; 803 } 804 805 int xe_guc_upload(struct xe_guc *guc) 806 { 807 xe_guc_ads_populate(&guc->ads); 808 809 return __xe_guc_upload(guc); 810 } 811 812 static void guc_handle_mmio_msg(struct xe_guc *guc) 813 { 814 struct xe_gt *gt = guc_to_gt(guc); 815 u32 msg; 816 817 if (IS_SRIOV_VF(guc_to_xe(guc))) 818 return; 819 820 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 821 822 msg = xe_mmio_read32(gt, SOFT_SCRATCH(15)); 823 msg &= XE_GUC_RECV_MSG_EXCEPTION | 824 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 825 xe_mmio_write32(gt, SOFT_SCRATCH(15), 0); 826 827 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 828 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 829 830 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 831 xe_gt_err(gt, "Received early GuC exception notification!\n"); 832 } 833 834 static void guc_enable_irq(struct xe_guc *guc) 835 { 836 struct xe_gt *gt = guc_to_gt(guc); 837 u32 events = xe_gt_is_media_type(gt) ? 838 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 839 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 840 841 /* Primary GuC and media GuC share a single enable bit */ 842 xe_mmio_write32(gt, GUC_SG_INTR_ENABLE, 843 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 844 845 /* 846 * There are separate mask bits for primary and media GuCs, so use 847 * a RMW operation to avoid clobbering the other GuC's setting. 848 */ 849 xe_mmio_rmw32(gt, GUC_SG_INTR_MASK, events, 0); 850 } 851 852 int xe_guc_enable_communication(struct xe_guc *guc) 853 { 854 struct xe_device *xe = guc_to_xe(guc); 855 int err; 856 857 guc_enable_irq(guc); 858 859 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 860 struct xe_gt *gt = guc_to_gt(guc); 861 struct xe_tile *tile = gt_to_tile(gt); 862 863 err = xe_memirq_init_guc(&tile->sriov.vf.memirq, guc); 864 if (err) 865 return err; 866 } 867 868 xe_mmio_rmw32(guc_to_gt(guc), PMINTRMSK, 869 ARAT_EXPIRED_INTRMSK, 0); 870 871 err = xe_guc_ct_enable(&guc->ct); 872 if (err) 873 return err; 874 875 guc_handle_mmio_msg(guc); 876 877 return 0; 878 } 879 880 int xe_guc_suspend(struct xe_guc *guc) 881 { 882 struct xe_gt *gt = guc_to_gt(guc); 883 u32 action[] = { 884 XE_GUC_ACTION_CLIENT_SOFT_RESET, 885 }; 886 int ret; 887 888 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 889 if (ret) { 890 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 891 return ret; 892 } 893 894 xe_guc_sanitize(guc); 895 return 0; 896 } 897 898 void xe_guc_notify(struct xe_guc *guc) 899 { 900 struct xe_gt *gt = guc_to_gt(guc); 901 const u32 default_notify_data = 0; 902 903 /* 904 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 905 * additional payload data to the GuC but this capability is not 906 * used by the firmware yet. Use default value in the meantime. 907 */ 908 xe_mmio_write32(gt, guc->notify_reg, default_notify_data); 909 } 910 911 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 912 { 913 u32 action[] = { 914 XE_GUC_ACTION_AUTHENTICATE_HUC, 915 rsa_addr 916 }; 917 918 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 919 } 920 921 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 922 u32 len, u32 *response_buf) 923 { 924 struct xe_device *xe = guc_to_xe(guc); 925 struct xe_gt *gt = guc_to_gt(guc); 926 u32 header, reply; 927 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 928 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 929 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 930 int ret; 931 int i; 932 933 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 934 935 xe_assert(xe, !xe_guc_ct_enabled(&guc->ct)); 936 xe_assert(xe, len); 937 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 938 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 939 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 940 GUC_HXG_ORIGIN_HOST); 941 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 942 GUC_HXG_TYPE_REQUEST); 943 944 retry: 945 /* Not in critical data-path, just do if else for GT type */ 946 if (xe_gt_is_media_type(gt)) { 947 for (i = 0; i < len; ++i) 948 xe_mmio_write32(gt, MED_VF_SW_FLAG(i), 949 request[i]); 950 xe_mmio_read32(gt, MED_VF_SW_FLAG(LAST_INDEX)); 951 } else { 952 for (i = 0; i < len; ++i) 953 xe_mmio_write32(gt, VF_SW_FLAG(i), 954 request[i]); 955 xe_mmio_read32(gt, VF_SW_FLAG(LAST_INDEX)); 956 } 957 958 xe_guc_notify(guc); 959 960 ret = xe_mmio_wait32(gt, reply_reg, GUC_HXG_MSG_0_ORIGIN, 961 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 962 50000, &reply, false); 963 if (ret) { 964 timeout: 965 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 966 request[0], reply); 967 return ret; 968 } 969 970 header = xe_mmio_read32(gt, reply_reg); 971 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 972 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 973 /* 974 * Once we got a BUSY reply we must wait again for the final 975 * response but this time we can't use ORIGIN mask anymore. 976 * To spot a right change in the reply, we take advantage that 977 * response SUCCESS and FAILURE differ only by the single bit 978 * and all other bits are set and can be used as a new mask. 979 */ 980 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 981 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 982 983 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 984 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 985 986 ret = xe_mmio_wait32(gt, reply_reg, resp_mask, resp_mask, 987 1000000, &header, false); 988 989 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 990 GUC_HXG_ORIGIN_GUC)) 991 goto proto; 992 if (unlikely(ret)) { 993 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 994 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 995 goto proto; 996 goto timeout; 997 } 998 } 999 1000 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1001 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1002 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1003 1004 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1005 request[0], reason); 1006 goto retry; 1007 } 1008 1009 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1010 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1011 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1012 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1013 1014 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1015 request[0], error, hint); 1016 return -ENXIO; 1017 } 1018 1019 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1020 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1021 proto: 1022 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1023 request[0], header); 1024 return -EPROTO; 1025 } 1026 1027 /* Just copy entire possible message response */ 1028 if (response_buf) { 1029 response_buf[0] = header; 1030 1031 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1032 reply_reg.addr += sizeof(u32); 1033 response_buf[i] = xe_mmio_read32(gt, reply_reg); 1034 } 1035 } 1036 1037 /* Use data from the GuC response as our return value */ 1038 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1039 } 1040 1041 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1042 { 1043 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1044 } 1045 1046 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1047 { 1048 struct xe_device *xe = guc_to_xe(guc); 1049 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1050 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1051 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1052 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1053 GUC_ACTION_HOST2GUC_SELF_CFG), 1054 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1055 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1056 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1057 lower_32_bits(val)), 1058 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1059 upper_32_bits(val)), 1060 }; 1061 int ret; 1062 1063 xe_assert(xe, len <= 2); 1064 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1065 1066 /* Self config must go over MMIO */ 1067 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1068 1069 if (unlikely(ret < 0)) 1070 return ret; 1071 if (unlikely(ret > 1)) 1072 return -EPROTO; 1073 if (unlikely(!ret)) 1074 return -ENOKEY; 1075 1076 return 0; 1077 } 1078 1079 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1080 { 1081 return guc_self_cfg(guc, key, 1, val); 1082 } 1083 1084 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1085 { 1086 return guc_self_cfg(guc, key, 2, val); 1087 } 1088 1089 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1090 { 1091 if (iir & GUC_INTR_GUC2HOST) 1092 xe_guc_ct_irq_handler(&guc->ct); 1093 } 1094 1095 void xe_guc_sanitize(struct xe_guc *guc) 1096 { 1097 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 1098 xe_guc_ct_disable(&guc->ct); 1099 guc->submission_state.enabled = false; 1100 } 1101 1102 int xe_guc_reset_prepare(struct xe_guc *guc) 1103 { 1104 return xe_guc_submit_reset_prepare(guc); 1105 } 1106 1107 void xe_guc_reset_wait(struct xe_guc *guc) 1108 { 1109 xe_guc_submit_reset_wait(guc); 1110 } 1111 1112 void xe_guc_stop_prepare(struct xe_guc *guc) 1113 { 1114 XE_WARN_ON(xe_guc_pc_stop(&guc->pc)); 1115 } 1116 1117 void xe_guc_stop(struct xe_guc *guc) 1118 { 1119 xe_guc_ct_stop(&guc->ct); 1120 1121 xe_guc_submit_stop(guc); 1122 } 1123 1124 int xe_guc_start(struct xe_guc *guc) 1125 { 1126 int ret; 1127 1128 ret = xe_guc_pc_start(&guc->pc); 1129 XE_WARN_ON(ret); 1130 1131 return xe_guc_submit_start(guc); 1132 } 1133 1134 void xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1135 { 1136 struct xe_gt *gt = guc_to_gt(guc); 1137 u32 status; 1138 int err; 1139 int i; 1140 1141 xe_uc_fw_print(&guc->fw, p); 1142 1143 err = xe_force_wake_get(gt_to_fw(gt), XE_FW_GT); 1144 if (err) 1145 return; 1146 1147 status = xe_mmio_read32(gt, GUC_STATUS); 1148 1149 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1150 drm_printf(p, "\tBootrom status = 0x%x\n", 1151 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1152 drm_printf(p, "\tuKernel status = 0x%x\n", 1153 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1154 drm_printf(p, "\tMIA Core status = 0x%x\n", 1155 REG_FIELD_GET(GS_MIA_MASK, status)); 1156 drm_printf(p, "\tLog level = %d\n", 1157 xe_guc_log_get_level(&guc->log)); 1158 1159 drm_puts(p, "\nScratch registers:\n"); 1160 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1161 drm_printf(p, "\t%2d: \t0x%x\n", 1162 i, xe_mmio_read32(gt, SOFT_SCRATCH(i))); 1163 } 1164 1165 xe_force_wake_put(gt_to_fw(gt), XE_FW_GT); 1166 1167 xe_guc_ct_print(&guc->ct, p, false); 1168 xe_guc_submit_print(guc, p); 1169 } 1170