1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_guc.h" 7 8 #include <linux/error-injection.h> 9 #include <linux/iopoll.h> 10 #include <drm/drm_managed.h> 11 12 #include <generated/xe_wa_oob.h> 13 14 #include "abi/guc_actions_abi.h" 15 #include "abi/guc_errors_abi.h" 16 #include "abi/guc_klvs_abi.h" 17 #include "regs/xe_gt_regs.h" 18 #include "regs/xe_gtt_defs.h" 19 #include "regs/xe_guc_regs.h" 20 #include "regs/xe_irq_regs.h" 21 #include "xe_bo.h" 22 #include "xe_configfs.h" 23 #include "xe_device.h" 24 #include "xe_force_wake.h" 25 #include "xe_gt.h" 26 #include "xe_gt_printk.h" 27 #include "xe_gt_sriov_vf.h" 28 #include "xe_gt_throttle.h" 29 #include "xe_gt_sriov_pf_migration.h" 30 #include "xe_guc_ads.h" 31 #include "xe_guc_buf.h" 32 #include "xe_guc_capture.h" 33 #include "xe_guc_ct.h" 34 #include "xe_guc_db_mgr.h" 35 #include "xe_guc_engine_activity.h" 36 #include "xe_guc_hwconfig.h" 37 #include "xe_guc_klv_helpers.h" 38 #include "xe_guc_log.h" 39 #include "xe_guc_pc.h" 40 #include "xe_guc_rc.h" 41 #include "xe_guc_relay.h" 42 #include "xe_guc_submit.h" 43 #include "xe_memirq.h" 44 #include "xe_mmio.h" 45 #include "xe_platform_types.h" 46 #include "xe_sleep.h" 47 #include "xe_sriov.h" 48 #include "xe_sriov_pf_migration.h" 49 #include "xe_uc.h" 50 #include "xe_uc_fw.h" 51 #include "xe_wa.h" 52 #include "xe_wopcm.h" 53 54 static u32 guc_bo_ggtt_addr(struct xe_guc *guc, 55 struct xe_bo *bo) 56 { 57 struct xe_device *xe = guc_to_xe(guc); 58 u32 addr; 59 60 /* 61 * For most BOs, the address on the allocating tile is fine. However for 62 * some, e.g. G2G CTB, the address on a specific tile is required as it 63 * might be different for each tile. So, just always ask for the address 64 * on the target GuC. 65 */ 66 addr = __xe_bo_ggtt_addr(bo, gt_to_tile(guc_to_gt(guc))->id); 67 68 /* GuC addresses above GUC_GGTT_TOP don't map through the GTT */ 69 xe_assert(xe, addr >= xe_wopcm_size(guc_to_xe(guc))); 70 xe_assert(xe, addr < GUC_GGTT_TOP); 71 xe_assert(xe, xe_bo_size(bo) <= GUC_GGTT_TOP - addr); 72 73 return addr; 74 } 75 76 static u32 guc_ctl_debug_flags(struct xe_guc *guc) 77 { 78 u32 level = xe_guc_log_get_level(&guc->log); 79 u32 flags = 0; 80 81 if (!GUC_LOG_LEVEL_IS_VERBOSE(level)) 82 flags |= GUC_LOG_DISABLED; 83 else 84 flags |= FIELD_PREP(GUC_LOG_VERBOSITY, GUC_LOG_LEVEL_TO_VERBOSITY(level)); 85 86 return flags; 87 } 88 89 static u32 guc_ctl_feature_flags(struct xe_guc *guc) 90 { 91 struct xe_device *xe = guc_to_xe(guc); 92 u32 flags = GUC_CTL_ENABLE_LITE_RESTORE; 93 94 if (!xe->info.skip_guc_pc) 95 flags |= GUC_CTL_ENABLE_SLPC; 96 97 if (xe_configfs_get_psmi_enabled(to_pci_dev(xe->drm.dev))) 98 flags |= GUC_CTL_ENABLE_PSMI_LOGGING; 99 100 if (xe_guc_using_main_gamctrl_queues(guc)) 101 flags |= GUC_CTL_MAIN_GAMCTRL_QUEUES; 102 103 if (xe_device_is_l2_flush_optimized(xe) && xe_gt_is_media_type(guc_to_gt(guc))) 104 flags |= GUC_CTL_ENABLE_L2FLUSH_OPT; 105 106 /* 107 * On GuC firmware 70.66 and above, the GUC_FEATURE_KLV_DISABLE_MULTI_QUEUE 108 * Feature KLV is used instead. 109 */ 110 if (!xe_configfs_get_enable_multi_queue(to_pci_dev(xe->drm.dev)) && 111 !GUC_FIRMWARE_VER_AT_LEAST(guc, 70, 66)) 112 flags |= GUC_CTL_DISABLE_MULTI_QUEUE; 113 114 return flags; 115 } 116 117 static u32 guc_ctl_log_params_flags(struct xe_guc *guc) 118 { 119 u32 offset = guc_bo_ggtt_addr(guc, guc->log.bo) >> PAGE_SHIFT; 120 u32 flags; 121 122 #if (((XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE) % SZ_1M) == 0) 123 #define LOG_UNIT SZ_1M 124 #define LOG_FLAG GUC_LOG_LOG_ALLOC_UNITS 125 #else 126 #define LOG_UNIT SZ_4K 127 #define LOG_FLAG 0 128 #endif 129 130 #if (((XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE) % SZ_1M) == 0) 131 #define CAPTURE_UNIT SZ_1M 132 #define CAPTURE_FLAG GUC_LOG_CAPTURE_ALLOC_UNITS 133 #else 134 #define CAPTURE_UNIT SZ_4K 135 #define CAPTURE_FLAG 0 136 #endif 137 138 BUILD_BUG_ON(!XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE); 139 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE, LOG_UNIT)); 140 BUILD_BUG_ON(!XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE); 141 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE, LOG_UNIT)); 142 BUILD_BUG_ON(!XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE); 143 BUILD_BUG_ON(!IS_ALIGNED(XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE, CAPTURE_UNIT)); 144 145 flags = GUC_LOG_VALID | 146 GUC_LOG_NOTIFY_ON_HALF_FULL | 147 CAPTURE_FLAG | 148 LOG_FLAG | 149 FIELD_PREP(GUC_LOG_CRASH_DUMP, XE_GUC_LOG_CRASH_DUMP_BUFFER_SIZE / LOG_UNIT - 1) | 150 FIELD_PREP(GUC_LOG_EVENT_DATA, XE_GUC_LOG_EVENT_DATA_BUFFER_SIZE / LOG_UNIT - 1) | 151 FIELD_PREP(GUC_LOG_STATE_CAPTURE, XE_GUC_LOG_STATE_CAPTURE_BUFFER_SIZE / 152 CAPTURE_UNIT - 1) | 153 FIELD_PREP(GUC_LOG_BUF_ADDR, offset); 154 155 #undef LOG_UNIT 156 #undef LOG_FLAG 157 #undef CAPTURE_UNIT 158 #undef CAPTURE_FLAG 159 160 return flags; 161 } 162 163 static u32 guc_ctl_ads_flags(struct xe_guc *guc) 164 { 165 u32 ads = guc_bo_ggtt_addr(guc, guc->ads.bo) >> PAGE_SHIFT; 166 u32 flags = FIELD_PREP(GUC_ADS_ADDR, ads); 167 168 return flags; 169 } 170 171 static bool needs_wa_dual_queue(struct xe_gt *gt) 172 { 173 /* 174 * The DUAL_QUEUE_WA tells the GuC to not allow concurrent submissions 175 * on RCS and CCSes with different address spaces, which on DG2 is 176 * required as a WA for an HW bug. 177 */ 178 if (XE_GT_WA(gt, 22011391025)) 179 return true; 180 181 /* 182 * On newer platforms, the HW has been updated to not allow parallel 183 * execution of different address spaces, so the RCS/CCS will stall the 184 * context switch if one of the other RCS/CCSes is busy with a different 185 * address space. While functionally correct, having a submission 186 * stalled on the HW limits the GuC ability to shuffle things around and 187 * can cause complications if the non-stalled submission runs for a long 188 * time, because the GuC doesn't know that the stalled submission isn't 189 * actually running and might declare it as hung. Therefore, we enable 190 * the DUAL_QUEUE_WA on all newer platforms on GTs that have CCS engines 191 * to move management back to the GuC. 192 */ 193 if (CCS_INSTANCES(gt) && GRAPHICS_VERx100(gt_to_xe(gt)) >= 1270) 194 return true; 195 196 return false; 197 } 198 199 static u32 guc_ctl_wa_flags(struct xe_guc *guc) 200 { 201 struct xe_device *xe = guc_to_xe(guc); 202 struct xe_gt *gt = guc_to_gt(guc); 203 u32 flags = 0; 204 205 if (XE_GT_WA(gt, 22012773006)) 206 flags |= GUC_WA_POLLCS; 207 208 if (XE_GT_WA(gt, 14014475959)) 209 flags |= GUC_WA_HOLD_CCS_SWITCHOUT; 210 211 if (needs_wa_dual_queue(gt)) 212 flags |= GUC_WA_DUAL_QUEUE; 213 214 /* 215 * Wa_22011802037: FIXME - there's more to be done than simply setting 216 * this flag: make sure each CS is stopped when preparing for GT reset 217 * and wait for pending MI_FW. 218 */ 219 if (GRAPHICS_VERx100(xe) < 1270) 220 flags |= GUC_WA_PRE_PARSER; 221 222 if (XE_GT_WA(gt, 22012727170) || XE_GT_WA(gt, 22012727685)) 223 flags |= GUC_WA_CONTEXT_ISOLATION; 224 225 if (XE_GT_WA(gt, 18020744125) && 226 !xe_hw_engine_mask_per_class(gt, XE_ENGINE_CLASS_RENDER)) 227 flags |= GUC_WA_RCS_REGS_IN_CCS_REGS_LIST; 228 229 if (XE_GT_WA(gt, 14018913170)) 230 flags |= GUC_WA_ENABLE_TSC_CHECK_ON_RC6; 231 232 if (XE_GT_WA(gt, 16023683509)) 233 flags |= GUC_WA_SAVE_RESTORE_MCFG_REG_AT_MC6; 234 235 return flags; 236 } 237 238 static u32 guc_ctl_devid(struct xe_guc *guc) 239 { 240 struct xe_device *xe = guc_to_xe(guc); 241 242 return (((u32)xe->info.devid) << 16) | xe->info.revid; 243 } 244 245 static void guc_print_params(struct xe_guc *guc) 246 { 247 struct xe_gt *gt = guc_to_gt(guc); 248 u32 *params = guc->params; 249 int i; 250 251 BUILD_BUG_ON(sizeof(guc->params) != GUC_CTL_MAX_DWORDS * sizeof(u32)); 252 BUILD_BUG_ON(GUC_CTL_MAX_DWORDS + 2 != SOFT_SCRATCH_COUNT); 253 254 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 255 xe_gt_dbg(gt, "GuC param[%2d] = 0x%08x\n", i, params[i]); 256 } 257 258 static void guc_init_params(struct xe_guc *guc) 259 { 260 u32 *params = guc->params; 261 262 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 263 params[GUC_CTL_FEATURE] = 0; 264 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 265 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 266 params[GUC_CTL_WA] = 0; 267 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 268 269 guc_print_params(guc); 270 } 271 272 static void guc_init_params_post_hwconfig(struct xe_guc *guc) 273 { 274 u32 *params = guc->params; 275 276 params[GUC_CTL_LOG_PARAMS] = guc_ctl_log_params_flags(guc); 277 params[GUC_CTL_FEATURE] = guc_ctl_feature_flags(guc); 278 params[GUC_CTL_DEBUG] = guc_ctl_debug_flags(guc); 279 params[GUC_CTL_ADS] = guc_ctl_ads_flags(guc); 280 params[GUC_CTL_WA] = guc_ctl_wa_flags(guc); 281 params[GUC_CTL_DEVID] = guc_ctl_devid(guc); 282 283 guc_print_params(guc); 284 } 285 286 /* 287 * Initialize the GuC parameter block before starting the firmware 288 * transfer. These parameters are read by the firmware on startup 289 * and cannot be changed thereafter. 290 */ 291 static void guc_write_params(struct xe_guc *guc) 292 { 293 struct xe_gt *gt = guc_to_gt(guc); 294 int i; 295 296 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 297 298 xe_mmio_write32(>->mmio, SOFT_SCRATCH(0), 0); 299 300 for (i = 0; i < GUC_CTL_MAX_DWORDS; i++) 301 xe_mmio_write32(>->mmio, SOFT_SCRATCH(1 + i), guc->params[i]); 302 } 303 304 static int guc_action_register_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev, 305 u32 desc_addr, u32 buff_addr, u32 size) 306 { 307 struct xe_gt *gt = guc_to_gt(guc); 308 struct xe_device *xe = gt_to_xe(gt); 309 u32 action[] = { 310 XE_GUC_ACTION_REGISTER_G2G, 311 FIELD_PREP(XE_G2G_REGISTER_SIZE, size / SZ_4K - 1) | 312 FIELD_PREP(XE_G2G_REGISTER_TYPE, type) | 313 FIELD_PREP(XE_G2G_REGISTER_TILE, dst_tile) | 314 FIELD_PREP(XE_G2G_REGISTER_DEVICE, dst_dev), 315 desc_addr, 316 buff_addr, 317 }; 318 319 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 320 xe_assert(xe, !(size % SZ_4K)); 321 322 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 323 } 324 325 static int guc_action_deregister_g2g_buffer(struct xe_guc *guc, u32 type, u32 dst_tile, u32 dst_dev) 326 { 327 struct xe_gt *gt = guc_to_gt(guc); 328 struct xe_device *xe = gt_to_xe(gt); 329 u32 action[] = { 330 XE_GUC_ACTION_DEREGISTER_G2G, 331 FIELD_PREP(XE_G2G_DEREGISTER_TYPE, type) | 332 FIELD_PREP(XE_G2G_DEREGISTER_TILE, dst_tile) | 333 FIELD_PREP(XE_G2G_DEREGISTER_DEVICE, dst_dev), 334 }; 335 336 xe_assert(xe, (type == XE_G2G_TYPE_IN) || (type == XE_G2G_TYPE_OUT)); 337 338 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 339 } 340 341 #define G2G_DEV(gt) (((gt)->info.type == XE_GT_TYPE_MAIN) ? 0 : 1) 342 343 #define G2G_BUFFER_SIZE (SZ_4K) 344 #define G2G_DESC_SIZE (64) 345 #define G2G_DESC_AREA_SIZE (SZ_4K) 346 347 /* 348 * Generate a unique id for each bi-directional CTB for each pair of 349 * near and far tiles/devices. The id can then be used as an index into 350 * a single allocation that is sub-divided into multiple CTBs. 351 * 352 * For example, with two devices per tile and two tiles, the table should 353 * look like: 354 * Far <tile>.<dev> 355 * 0.0 0.1 1.0 1.1 356 * N 0.0 --/-- 00/01 02/03 04/05 357 * e 0.1 01/00 --/-- 06/07 08/09 358 * a 1.0 03/02 07/06 --/-- 10/11 359 * r 1.1 05/04 09/08 11/10 --/-- 360 * 361 * Where each entry is Rx/Tx channel id. 362 * 363 * So GuC #3 (tile 1, dev 1) talking to GuC #2 (tile 1, dev 0) would 364 * be reading from channel #11 and writing to channel #10. Whereas, 365 * GuC #2 talking to GuC #3 would be read on #10 and write to #11. 366 */ 367 static unsigned int g2g_slot(u32 near_tile, u32 near_dev, u32 far_tile, u32 far_dev, 368 u32 type, u32 max_inst, bool have_dev) 369 { 370 u32 near = near_tile, far = far_tile; 371 u32 idx = 0, x, y, direction; 372 int i; 373 374 if (have_dev) { 375 near = (near << 1) | near_dev; 376 far = (far << 1) | far_dev; 377 } 378 379 /* No need to send to one's self */ 380 if (far == near) 381 return -1; 382 383 if (far > near) { 384 /* Top right table half */ 385 x = far; 386 y = near; 387 388 /* T/R is 'forwards' direction */ 389 direction = type; 390 } else { 391 /* Bottom left table half */ 392 x = near; 393 y = far; 394 395 /* B/L is 'backwards' direction */ 396 direction = (1 - type); 397 } 398 399 /* Count the rows prior to the target */ 400 for (i = y; i > 0; i--) 401 idx += max_inst - i; 402 403 /* Count this row up to the target */ 404 idx += (x - 1 - y); 405 406 /* Slots are in Rx/Tx pairs */ 407 idx *= 2; 408 409 /* Pick Rx/Tx direction */ 410 idx += direction; 411 412 return idx; 413 } 414 415 static int guc_g2g_register(struct xe_guc *near_guc, struct xe_gt *far_gt, u32 type, bool have_dev) 416 { 417 struct xe_gt *near_gt = guc_to_gt(near_guc); 418 struct xe_device *xe = gt_to_xe(near_gt); 419 struct xe_bo *g2g_bo; 420 u32 near_tile = gt_to_tile(near_gt)->id; 421 u32 near_dev = G2G_DEV(near_gt); 422 u32 far_tile = gt_to_tile(far_gt)->id; 423 u32 far_dev = G2G_DEV(far_gt); 424 u32 max = xe->info.gt_count; 425 u32 base, desc, buf; 426 int slot; 427 428 /* G2G is not allowed between different cards */ 429 xe_assert(xe, xe == gt_to_xe(far_gt)); 430 431 g2g_bo = near_guc->g2g.bo; 432 xe_assert(xe, g2g_bo); 433 434 slot = g2g_slot(near_tile, near_dev, far_tile, far_dev, type, max, have_dev); 435 xe_assert(xe, slot >= 0); 436 437 base = guc_bo_ggtt_addr(near_guc, g2g_bo); 438 desc = base + slot * G2G_DESC_SIZE; 439 buf = base + G2G_DESC_AREA_SIZE + slot * G2G_BUFFER_SIZE; 440 441 xe_assert(xe, (desc - base + G2G_DESC_SIZE) <= G2G_DESC_AREA_SIZE); 442 xe_assert(xe, (buf - base + G2G_BUFFER_SIZE) <= xe_bo_size(g2g_bo)); 443 444 return guc_action_register_g2g_buffer(near_guc, type, far_tile, far_dev, 445 desc, buf, G2G_BUFFER_SIZE); 446 } 447 448 static void guc_g2g_deregister(struct xe_guc *guc, u32 far_tile, u32 far_dev, u32 type) 449 { 450 guc_action_deregister_g2g_buffer(guc, type, far_tile, far_dev); 451 } 452 453 static u32 guc_g2g_size(struct xe_guc *guc) 454 { 455 struct xe_gt *gt = guc_to_gt(guc); 456 struct xe_device *xe = gt_to_xe(gt); 457 unsigned int count = xe->info.gt_count; 458 u32 num_channels = (count * (count - 1)) / 2; 459 460 xe_assert(xe, num_channels * XE_G2G_TYPE_LIMIT * G2G_DESC_SIZE <= G2G_DESC_AREA_SIZE); 461 462 return num_channels * XE_G2G_TYPE_LIMIT * G2G_BUFFER_SIZE + G2G_DESC_AREA_SIZE; 463 } 464 465 static bool xe_guc_g2g_wanted(struct xe_device *xe) 466 { 467 /* Can't do GuC to GuC communication if there is only one GuC */ 468 if (xe->info.gt_count <= 1) 469 return false; 470 471 /* No current user */ 472 return false; 473 } 474 475 static int guc_g2g_alloc(struct xe_guc *guc) 476 { 477 struct xe_gt *gt = guc_to_gt(guc); 478 struct xe_device *xe = gt_to_xe(gt); 479 struct xe_tile *tile = gt_to_tile(gt); 480 struct xe_bo *bo; 481 u32 g2g_size; 482 483 if (guc->g2g.bo) 484 return 0; 485 486 if (gt->info.id != 0) { 487 struct xe_gt *root_gt = xe_device_get_gt(xe, 0); 488 struct xe_guc *root_guc = &root_gt->uc.guc; 489 struct xe_bo *bo; 490 491 bo = xe_bo_get(root_guc->g2g.bo); 492 if (!bo) 493 return -ENODEV; 494 495 guc->g2g.bo = bo; 496 guc->g2g.owned = false; 497 return 0; 498 } 499 500 g2g_size = guc_g2g_size(guc); 501 bo = xe_managed_bo_create_pin_map(xe, tile, g2g_size, 502 XE_BO_FLAG_VRAM_IF_DGFX(tile) | 503 XE_BO_FLAG_GGTT | 504 XE_BO_FLAG_GGTT_ALL | 505 XE_BO_FLAG_GGTT_INVALIDATE | 506 XE_BO_FLAG_PINNED_NORESTORE); 507 if (IS_ERR(bo)) 508 return PTR_ERR(bo); 509 510 xe_map_memset(xe, &bo->vmap, 0, 0, g2g_size); 511 guc->g2g.bo = bo; 512 guc->g2g.owned = true; 513 514 return 0; 515 } 516 517 static void guc_g2g_fini(struct xe_guc *guc) 518 { 519 if (!guc->g2g.bo) 520 return; 521 522 /* Unpinning the owned object is handled by generic shutdown */ 523 if (!guc->g2g.owned) 524 xe_bo_put(guc->g2g.bo); 525 526 guc->g2g.bo = NULL; 527 } 528 529 static int guc_g2g_start(struct xe_guc *guc) 530 { 531 struct xe_gt *far_gt, *gt = guc_to_gt(guc); 532 struct xe_device *xe = gt_to_xe(gt); 533 unsigned int i, j; 534 int t, err; 535 bool have_dev; 536 537 if (!guc->g2g.bo) { 538 int ret; 539 540 ret = guc_g2g_alloc(guc); 541 if (ret) 542 return ret; 543 } 544 545 /* GuC interface will need extending if more GT device types are ever created. */ 546 xe_gt_assert(gt, (gt->info.type == XE_GT_TYPE_MAIN) || (gt->info.type == XE_GT_TYPE_MEDIA)); 547 548 /* Channel numbering depends on whether there are multiple GTs per tile */ 549 have_dev = xe->info.gt_count > xe->info.tile_count; 550 551 for_each_gt(far_gt, xe, i) { 552 u32 far_tile, far_dev; 553 554 if (far_gt->info.id == gt->info.id) 555 continue; 556 557 far_tile = gt_to_tile(far_gt)->id; 558 far_dev = G2G_DEV(far_gt); 559 560 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) { 561 err = guc_g2g_register(guc, far_gt, t, have_dev); 562 if (err) { 563 while (--t >= 0) 564 guc_g2g_deregister(guc, far_tile, far_dev, t); 565 goto err_deregister; 566 } 567 } 568 } 569 570 return 0; 571 572 err_deregister: 573 for_each_gt(far_gt, xe, j) { 574 u32 tile, dev; 575 576 if (far_gt->info.id == gt->info.id) 577 continue; 578 579 if (j >= i) 580 break; 581 582 tile = gt_to_tile(far_gt)->id; 583 dev = G2G_DEV(far_gt); 584 585 for (t = 0; t < XE_G2G_TYPE_LIMIT; t++) 586 guc_g2g_deregister(guc, tile, dev, t); 587 } 588 589 return err; 590 } 591 592 static int __guc_opt_in_features_enable(struct xe_guc *guc, u64 addr, u32 num_dwords) 593 { 594 u32 action[] = { 595 XE_GUC_ACTION_OPT_IN_FEATURE_KLV, 596 lower_32_bits(addr), 597 upper_32_bits(addr), 598 num_dwords 599 }; 600 601 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 602 } 603 604 static bool supports_dynamic_ics(struct xe_guc *guc) 605 { 606 struct xe_device *xe = guc_to_xe(guc); 607 struct xe_gt *gt = guc_to_gt(guc); 608 609 /* Dynamic ICS is available for PVC and Xe2 and newer platforms. */ 610 if (xe->info.platform != XE_PVC && GRAPHICS_VER(xe) < 20) 611 return false; 612 613 /* 614 * The feature is currently not compatible with multi-lrc, so the GuC 615 * does not support it at all on the media engines (which are the main 616 * users of mlrc). On the primary GT side, to avoid it being used in 617 * conjunction with mlrc, we only enable it if we are in single CCS 618 * mode. 619 */ 620 if (xe_gt_is_media_type(gt) || gt->ccs_mode > 1) 621 return false; 622 623 /* 624 * Dynamic ICS requires GuC v70.40.1, which maps to compatibility 625 * version v1.18.4. 626 */ 627 return GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 4); 628 } 629 630 #define OPT_IN_MAX_DWORDS 16 631 int xe_guc_opt_in_features_enable(struct xe_guc *guc) 632 { 633 struct xe_device *xe = guc_to_xe(guc); 634 CLASS(xe_guc_buf, buf)(&guc->buf, OPT_IN_MAX_DWORDS); 635 u32 count = 0; 636 u32 *klvs; 637 int ret; 638 639 if (!xe_guc_buf_is_valid(buf)) 640 return -ENOBUFS; 641 642 klvs = xe_guc_buf_cpu_ptr(buf); 643 644 /* 645 * The extra CAT error type opt-in was added in GuC v70.17.0, which maps 646 * to compatibility version v1.7.0. 647 * Note that the GuC allows enabling this KLV even on platforms that do 648 * not support the extra type; in such case the returned type variable 649 * will be set to a known invalid value which we can check against. 650 */ 651 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 7, 0)) 652 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_EXT_CAT_ERR_TYPE); 653 654 /* 655 * The uncorrectable local error notification opt-in was added in 656 * GuC v70.38.0, which maps to compatibility version v1.18.0. 657 */ 658 if (GUC_SUBMIT_VER(guc) >= MAKE_GUC_VER(1, 18, 0) && 659 guc_to_gt(guc)->info.has_uncorrectable_error_reporting) 660 klvs[count++] = 661 PREP_GUC_KLV_TAG(OPT_IN_FEATURE_UNCORRECTABLE_LOCAL_ERROR_NOTIFICATION); 662 663 if (supports_dynamic_ics(guc)) 664 klvs[count++] = PREP_GUC_KLV_TAG(OPT_IN_FEATURE_DYNAMIC_INHIBIT_CONTEXT_SWITCH); 665 666 if (count) { 667 xe_assert(xe, count <= OPT_IN_MAX_DWORDS); 668 669 ret = __guc_opt_in_features_enable(guc, xe_guc_buf_flush(buf), count); 670 if (ret < 0) { 671 xe_gt_err(guc_to_gt(guc), 672 "failed to enable GuC opt-in features: %pe\n", 673 ERR_PTR(ret)); 674 return ret; 675 } 676 } 677 678 return 0; 679 } 680 681 static void guc_fini_hw(void *arg) 682 { 683 struct xe_guc *guc = arg; 684 struct xe_gt *gt = guc_to_gt(guc); 685 686 xe_with_force_wake(fw_ref, gt_to_fw(gt), XE_FORCEWAKE_ALL) 687 xe_uc_sanitize_reset(&guc_to_gt(guc)->uc); 688 689 guc_g2g_fini(guc); 690 } 691 692 static void vf_guc_fini_hw(void *arg) 693 { 694 struct xe_guc *guc = arg; 695 696 xe_gt_sriov_vf_reset(guc_to_gt(guc)); 697 } 698 699 /** 700 * xe_guc_comm_init_early - early initialization of GuC communication 701 * @guc: the &xe_guc to initialize 702 * 703 * Must be called prior to first MMIO communication with GuC firmware. 704 */ 705 void xe_guc_comm_init_early(struct xe_guc *guc) 706 { 707 struct xe_gt *gt = guc_to_gt(guc); 708 709 if (xe_gt_is_media_type(gt)) 710 guc->notify_reg = MED_GUC_HOST_INTERRUPT; 711 else 712 guc->notify_reg = GUC_HOST_INTERRUPT; 713 } 714 715 static int xe_guc_realloc_post_hwconfig(struct xe_guc *guc) 716 { 717 struct xe_tile *tile = gt_to_tile(guc_to_gt(guc)); 718 struct xe_device *xe = guc_to_xe(guc); 719 int ret; 720 721 if (!IS_DGFX(guc_to_xe(guc))) 722 return 0; 723 724 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->fw.bo); 725 if (ret) 726 return ret; 727 728 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->log.bo); 729 if (ret) 730 return ret; 731 732 ret = xe_managed_bo_reinit_in_vram(xe, tile, &guc->ads.bo); 733 if (ret) 734 return ret; 735 736 return 0; 737 } 738 739 static int vf_guc_init_noalloc(struct xe_guc *guc) 740 { 741 struct xe_gt *gt = guc_to_gt(guc); 742 int err; 743 744 err = xe_gt_sriov_vf_bootstrap(gt); 745 if (err) 746 return err; 747 748 err = xe_gt_sriov_vf_query_config(gt); 749 if (err) 750 return err; 751 752 return 0; 753 } 754 755 int xe_guc_init_noalloc(struct xe_guc *guc) 756 { 757 struct xe_device *xe = guc_to_xe(guc); 758 struct xe_gt *gt = guc_to_gt(guc); 759 int ret; 760 761 xe_guc_comm_init_early(guc); 762 763 ret = xe_guc_ct_init_noalloc(&guc->ct); 764 if (ret) 765 goto out; 766 767 ret = xe_guc_relay_init(&guc->relay); 768 if (ret) 769 goto out; 770 771 if (IS_SRIOV_VF(xe)) { 772 ret = vf_guc_init_noalloc(guc); 773 if (ret) 774 goto out; 775 } 776 777 return 0; 778 779 out: 780 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 781 return ret; 782 } 783 784 int xe_guc_init(struct xe_guc *guc) 785 { 786 struct xe_device *xe = guc_to_xe(guc); 787 struct xe_gt *gt = guc_to_gt(guc); 788 int ret; 789 790 guc->fw.type = XE_UC_FW_TYPE_GUC; 791 ret = xe_uc_fw_init(&guc->fw); 792 if (ret) 793 return ret; 794 795 if (!xe_uc_fw_is_enabled(&guc->fw)) 796 return 0; 797 798 /* Disable page reclaim if GuC FW does not support */ 799 if (GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 14, 0)) 800 xe->info.has_page_reclaim_hw_assist = false; 801 802 /* Disable indirect_ring_state if missing GuC 70.53+ WA 14025515070. */ 803 if (gt->info.has_indirect_ring_state && 804 XE_GT_WA(gt, 14025515070) && 805 GUC_SUBMIT_VER(guc) < MAKE_GUC_VER(1, 26, 0)) { 806 gt->info.has_indirect_ring_state = 0; 807 xe_gt_notice(gt, "indirect ring state requires WA in GuC submit ver 1.26+\n"); 808 } 809 810 if (IS_SRIOV_VF(xe)) { 811 ret = devm_add_action_or_reset(xe->drm.dev, vf_guc_fini_hw, guc); 812 if (ret) 813 goto out; 814 815 ret = xe_guc_ct_init(&guc->ct); 816 if (ret) 817 goto out; 818 return 0; 819 } 820 821 ret = xe_guc_log_init(&guc->log); 822 if (ret) 823 goto out; 824 825 ret = xe_guc_capture_init(guc); 826 if (ret) 827 goto out; 828 829 ret = xe_guc_ads_init(&guc->ads); 830 if (ret) 831 goto out; 832 833 ret = xe_guc_ct_init(&guc->ct); 834 if (ret) 835 goto out; 836 837 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOADABLE); 838 839 ret = devm_add_action_or_reset(xe->drm.dev, guc_fini_hw, guc); 840 if (ret) 841 goto out; 842 843 guc_init_params(guc); 844 845 return 0; 846 847 out: 848 xe_gt_err(gt, "GuC init failed with %pe\n", ERR_PTR(ret)); 849 return ret; 850 } 851 852 static int vf_guc_init_post_hwconfig(struct xe_guc *guc) 853 { 854 int err; 855 856 err = xe_guc_submit_init(guc, xe_gt_sriov_vf_guc_ids(guc_to_gt(guc))); 857 if (err) 858 return err; 859 860 err = xe_guc_buf_cache_init(&guc->buf); 861 if (err) 862 return err; 863 864 /* XXX xe_guc_db_mgr_init not needed for now */ 865 866 return 0; 867 } 868 869 static u32 guc_additional_cache_size(struct xe_device *xe) 870 { 871 if (IS_SRIOV_PF(xe) && xe_sriov_pf_migration_supported(xe)) 872 return XE_GT_SRIOV_PF_MIGRATION_GUC_DATA_MAX_SIZE; 873 else 874 return 0; /* Fallback to default size */ 875 } 876 877 /** 878 * xe_guc_init_post_hwconfig - initialize GuC post hwconfig load 879 * @guc: The GuC object 880 * 881 * Return: 0 on success, negative error code on error. 882 */ 883 int xe_guc_init_post_hwconfig(struct xe_guc *guc) 884 { 885 int ret; 886 887 if (IS_SRIOV_VF(guc_to_xe(guc))) 888 return vf_guc_init_post_hwconfig(guc); 889 890 ret = xe_guc_realloc_post_hwconfig(guc); 891 if (ret) 892 return ret; 893 894 ret = xe_guc_ct_init_post_hwconfig(&guc->ct); 895 if (ret) 896 return ret; 897 898 guc_init_params_post_hwconfig(guc); 899 900 ret = xe_guc_submit_init(guc, ~0); 901 if (ret) 902 return ret; 903 904 ret = xe_guc_db_mgr_init(&guc->dbm, ~0); 905 if (ret) 906 return ret; 907 908 ret = xe_guc_pc_init(&guc->pc); 909 if (ret) 910 return ret; 911 912 ret = xe_guc_rc_init(guc); 913 if (ret) 914 return ret; 915 916 ret = xe_guc_engine_activity_init(guc); 917 if (ret) 918 return ret; 919 920 ret = xe_guc_buf_cache_init_with_size(&guc->buf, 921 guc_additional_cache_size(guc_to_xe(guc))); 922 if (ret) 923 return ret; 924 925 return xe_guc_ads_init_post_hwconfig(&guc->ads); 926 } 927 928 int xe_guc_post_load_init(struct xe_guc *guc) 929 { 930 int ret; 931 932 xe_guc_ads_populate_post_load(&guc->ads); 933 934 ret = xe_guc_opt_in_features_enable(guc); 935 if (ret) 936 return ret; 937 938 if (xe_guc_g2g_wanted(guc_to_xe(guc))) { 939 ret = guc_g2g_start(guc); 940 if (ret) 941 return ret; 942 } 943 944 return xe_guc_submit_enable(guc); 945 } 946 947 /* 948 * Wa_14025883347: Prevent GuC firmware DMA failures during GuC-only reset by ensuring 949 * SRAM save/restore operations are complete before reset. 950 */ 951 static void guc_prevent_fw_dma_failure_on_reset(struct xe_guc *guc) 952 { 953 struct xe_gt *gt = guc_to_gt(guc); 954 u32 boot_hash_chk, guc_status, sram_status; 955 int ret; 956 957 guc_status = xe_mmio_read32(>->mmio, GUC_STATUS); 958 if (guc_status & GS_MIA_IN_RESET) 959 return; 960 961 boot_hash_chk = xe_mmio_read32(>->mmio, BOOT_HASH_CHK); 962 if (!(boot_hash_chk & GUC_BOOT_UKERNEL_VALID)) 963 return; 964 965 /* Disable idle flow during reset (GuC reset re-enables it automatically) */ 966 xe_mmio_rmw32(>->mmio, GUC_MAX_IDLE_COUNT, 0, GUC_IDLE_FLOW_DISABLE); 967 968 ret = xe_mmio_wait32(>->mmio, GUC_STATUS, GS_UKERNEL_MASK, 969 FIELD_PREP(GS_UKERNEL_MASK, XE_GUC_LOAD_STATUS_READY), 970 100000, &guc_status, false); 971 if (ret) 972 xe_gt_warn(gt, "GuC not ready after disabling idle flow (GUC_STATUS: 0x%x)\n", 973 guc_status); 974 975 ret = xe_mmio_wait32(>->mmio, GUC_SRAM_STATUS, GUC_SRAM_HANDLING_MASK, 976 0, 5000, &sram_status, false); 977 if (ret) 978 xe_gt_warn(gt, "SRAM handling not complete (GUC_SRAM_STATUS: 0x%x)\n", 979 sram_status); 980 } 981 982 int xe_guc_reset(struct xe_guc *guc) 983 { 984 struct xe_gt *gt = guc_to_gt(guc); 985 struct xe_mmio *mmio = >->mmio; 986 u32 guc_status, gdrst; 987 int ret; 988 989 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 990 991 if (IS_SRIOV_VF(gt_to_xe(gt))) 992 return xe_gt_sriov_vf_bootstrap(gt); 993 994 if (XE_GT_WA(gt, 14025883347)) 995 guc_prevent_fw_dma_failure_on_reset(guc); 996 997 xe_mmio_write32(mmio, GDRST, GRDOM_GUC); 998 999 ret = xe_mmio_wait32(mmio, GDRST, GRDOM_GUC, 0, 5000, &gdrst, false); 1000 if (ret) { 1001 xe_gt_err(gt, "GuC reset timed out, GDRST=%#x\n", gdrst); 1002 goto err_out; 1003 } 1004 1005 guc_status = xe_mmio_read32(mmio, GUC_STATUS); 1006 if (!(guc_status & GS_MIA_IN_RESET)) { 1007 xe_gt_err(gt, "GuC status: %#x, MIA core expected to be in reset\n", 1008 guc_status); 1009 ret = -EIO; 1010 goto err_out; 1011 } 1012 1013 return 0; 1014 1015 err_out: 1016 1017 return ret; 1018 } 1019 1020 static void guc_prepare_xfer(struct xe_guc *guc) 1021 { 1022 struct xe_gt *gt = guc_to_gt(guc); 1023 struct xe_mmio *mmio = >->mmio; 1024 struct xe_device *xe = guc_to_xe(guc); 1025 u32 shim_flags = GUC_ENABLE_READ_CACHE_LOGIC | 1026 GUC_ENABLE_READ_CACHE_FOR_SRAM_DATA | 1027 GUC_ENABLE_READ_CACHE_FOR_WOPCM_DATA | 1028 GUC_ENABLE_MIA_CLOCK_GATING; 1029 1030 if (GRAPHICS_VERx100(xe) < 1250) 1031 shim_flags |= GUC_DISABLE_SRAM_INIT_TO_ZEROES | 1032 GUC_ENABLE_MIA_CACHING; 1033 1034 if (GRAPHICS_VER(xe) >= 20 || xe->info.platform == XE_PVC) 1035 shim_flags |= REG_FIELD_PREP(GUC_MOCS_INDEX_MASK, gt->mocs.uc_index); 1036 1037 /* Must program this register before loading the ucode with DMA */ 1038 xe_mmio_write32(mmio, GUC_SHIM_CONTROL, shim_flags); 1039 1040 xe_mmio_write32(mmio, GT_PM_CONFIG, GT_DOORBELL_ENABLE); 1041 1042 /* Make sure GuC receives ARAT interrupts */ 1043 xe_mmio_rmw32(mmio, PMINTRMSK, ARAT_EXPIRED_INTRMSK, 0); 1044 } 1045 1046 /* 1047 * Supporting MMIO & in memory RSA 1048 */ 1049 static int guc_xfer_rsa(struct xe_guc *guc) 1050 { 1051 struct xe_gt *gt = guc_to_gt(guc); 1052 u32 rsa[UOS_RSA_SCRATCH_COUNT]; 1053 size_t copied; 1054 int i; 1055 1056 if (guc->fw.rsa_size > 256) { 1057 u32 rsa_ggtt_addr = xe_bo_ggtt_addr(guc->fw.bo) + 1058 xe_uc_fw_rsa_offset(&guc->fw); 1059 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(0), rsa_ggtt_addr); 1060 return 0; 1061 } 1062 1063 copied = xe_uc_fw_copy_rsa(&guc->fw, rsa, sizeof(rsa)); 1064 if (copied < sizeof(rsa)) 1065 return -ENOMEM; 1066 1067 for (i = 0; i < UOS_RSA_SCRATCH_COUNT; i++) 1068 xe_mmio_write32(>->mmio, UOS_RSA_SCRATCH(i), rsa[i]); 1069 1070 return 0; 1071 } 1072 1073 /* 1074 * Wait for the GuC to start up. 1075 * 1076 * Measurements indicate this should take no more than 20ms (assuming the GT 1077 * clock is at maximum frequency). However, thermal throttling and other issues 1078 * can prevent the clock hitting max and thus making the load take significantly 1079 * longer. Allow up to 3s as a safety margin in normal builds. For 1080 * CONFIG_DRM_XE_DEBUG allow up to 10s to account for slower execution, issues 1081 * in PCODE, driver, fan, etc. 1082 * 1083 * Keep checking the GUC_STATUS every 10ms with a debug message every 100 1084 * attempts as a "I'm slow, but alive" message. Regardless, if it takes more 1085 * than 200ms, emit a warning. 1086 */ 1087 1088 #if IS_ENABLED(CONFIG_DRM_XE_DEBUG) 1089 #define GUC_LOAD_TIMEOUT_SEC 20 1090 #else 1091 #define GUC_LOAD_TIMEOUT_SEC 3 1092 #endif 1093 #define GUC_LOAD_TIME_WARN_MSEC 200 1094 1095 static void print_load_status_err(struct xe_gt *gt, u32 status) 1096 { 1097 struct xe_mmio *mmio = >->mmio; 1098 u32 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, status); 1099 u32 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, status); 1100 1101 xe_gt_err(gt, "load failed: status: Reset = %d, BootROM = 0x%02X, UKernel = 0x%02X, MIA = 0x%02X, Auth = 0x%02X\n", 1102 REG_FIELD_GET(GS_MIA_IN_RESET, status), 1103 bootrom, ukernel, 1104 REG_FIELD_GET(GS_MIA_MASK, status), 1105 REG_FIELD_GET(GS_AUTH_STATUS_MASK, status)); 1106 1107 switch (bootrom) { 1108 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1109 xe_gt_err(gt, "invalid key requested, header = 0x%08X\n", 1110 xe_mmio_read32(mmio, GUC_HEADER_INFO)); 1111 break; 1112 case XE_BOOTROM_STATUS_RSA_FAILED: 1113 xe_gt_err(gt, "firmware signature verification failed\n"); 1114 break; 1115 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1116 xe_gt_err(gt, "firmware production part check failure\n"); 1117 break; 1118 } 1119 1120 switch (ukernel) { 1121 case XE_GUC_LOAD_STATUS_HWCONFIG_START: 1122 xe_gt_err(gt, "still extracting hwconfig table.\n"); 1123 break; 1124 case XE_GUC_LOAD_STATUS_EXCEPTION: 1125 xe_gt_err(gt, "firmware exception. EIP: %#x\n", 1126 xe_mmio_read32(mmio, SOFT_SCRATCH(13))); 1127 break; 1128 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1129 xe_gt_err(gt, "illegal init/ADS data\n"); 1130 break; 1131 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1132 xe_gt_err(gt, "illegal register in save/restore workaround list\n"); 1133 break; 1134 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1135 xe_gt_err(gt, "illegal workaround KLV data\n"); 1136 break; 1137 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1138 xe_gt_err(gt, "illegal feature flag specified\n"); 1139 break; 1140 } 1141 } 1142 1143 /* 1144 * Check GUC_STATUS looking for known terminal states (either completion or 1145 * failure) of either the microkernel status field or the boot ROM status field. 1146 * 1147 * Returns 1 for successful completion, -1 for failure and 0 for any 1148 * intermediate state. 1149 */ 1150 static int guc_load_done(struct xe_gt *gt, u32 *status, u32 *tries) 1151 { 1152 u32 ukernel, bootrom; 1153 1154 *status = xe_mmio_read32(>->mmio, GUC_STATUS); 1155 ukernel = REG_FIELD_GET(GS_UKERNEL_MASK, *status); 1156 bootrom = REG_FIELD_GET(GS_BOOTROM_MASK, *status); 1157 1158 switch (ukernel) { 1159 case XE_GUC_LOAD_STATUS_READY: 1160 return 1; 1161 case XE_GUC_LOAD_STATUS_ERROR_DEVID_BUILD_MISMATCH: 1162 case XE_GUC_LOAD_STATUS_GUC_PREPROD_BUILD_MISMATCH: 1163 case XE_GUC_LOAD_STATUS_ERROR_DEVID_INVALID_GUCTYPE: 1164 case XE_GUC_LOAD_STATUS_HWCONFIG_ERROR: 1165 case XE_GUC_LOAD_STATUS_BOOTROM_VERSION_MISMATCH: 1166 case XE_GUC_LOAD_STATUS_DPC_ERROR: 1167 case XE_GUC_LOAD_STATUS_EXCEPTION: 1168 case XE_GUC_LOAD_STATUS_INIT_DATA_INVALID: 1169 case XE_GUC_LOAD_STATUS_MPU_DATA_INVALID: 1170 case XE_GUC_LOAD_STATUS_INIT_MMIO_SAVE_RESTORE_INVALID: 1171 case XE_GUC_LOAD_STATUS_KLV_WORKAROUND_INIT_ERROR: 1172 case XE_GUC_LOAD_STATUS_INVALID_FTR_FLAG: 1173 return -1; 1174 } 1175 1176 switch (bootrom) { 1177 case XE_BOOTROM_STATUS_NO_KEY_FOUND: 1178 case XE_BOOTROM_STATUS_RSA_FAILED: 1179 case XE_BOOTROM_STATUS_PAVPC_FAILED: 1180 case XE_BOOTROM_STATUS_WOPCM_FAILED: 1181 case XE_BOOTROM_STATUS_LOADLOC_FAILED: 1182 case XE_BOOTROM_STATUS_JUMP_FAILED: 1183 case XE_BOOTROM_STATUS_RC6CTXCONFIG_FAILED: 1184 case XE_BOOTROM_STATUS_MPUMAP_INCORRECT: 1185 case XE_BOOTROM_STATUS_EXCEPTION: 1186 case XE_BOOTROM_STATUS_PROD_KEY_CHECK_FAILURE: 1187 return -1; 1188 } 1189 1190 if (++*tries >= 100) { 1191 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1192 1193 *tries = 0; 1194 xe_gt_dbg(gt, "GuC load still in progress, freq = %dMHz (req %dMHz), status = 0x%08X [0x%02X/%02X]\n", 1195 xe_guc_pc_get_act_freq(guc_pc), 1196 xe_guc_pc_get_cur_freq_fw(guc_pc), 1197 *status, ukernel, bootrom); 1198 } 1199 1200 return 0; 1201 } 1202 1203 static int guc_wait_ucode(struct xe_guc *guc) 1204 { 1205 struct xe_gt *gt = guc_to_gt(guc); 1206 struct xe_guc_pc *guc_pc = >->uc.guc.pc; 1207 u32 before_freq, act_freq, cur_freq; 1208 u32 status = 0, tries = 0; 1209 int load_result, ret; 1210 ktime_t before; 1211 u64 delta_ms; 1212 1213 before_freq = xe_guc_pc_get_act_freq(guc_pc); 1214 before = ktime_get(); 1215 1216 ret = poll_timeout_us(load_result = guc_load_done(gt, &status, &tries), load_result, 1217 10 * USEC_PER_MSEC, 1218 GUC_LOAD_TIMEOUT_SEC * USEC_PER_SEC, false); 1219 1220 delta_ms = ktime_to_ms(ktime_sub(ktime_get(), before)); 1221 act_freq = xe_guc_pc_get_act_freq(guc_pc); 1222 cur_freq = xe_guc_pc_get_cur_freq_fw(guc_pc); 1223 1224 if (ret || load_result <= 0) { 1225 xe_gt_err(gt, "load failed: status = 0x%08X, time = %lldms, freq = %dMHz (req %dMHz)\n", 1226 status, delta_ms, xe_guc_pc_get_act_freq(guc_pc), 1227 xe_guc_pc_get_cur_freq_fw(guc_pc)); 1228 print_load_status_err(gt, status); 1229 1230 return -EPROTO; 1231 } 1232 1233 if (delta_ms > GUC_LOAD_TIME_WARN_MSEC) { 1234 xe_gt_warn(gt, "GuC load: excessive init time: %lldms! [status = 0x%08X]\n", 1235 delta_ms, status); 1236 xe_gt_warn(gt, "GuC load: excessive init time: [freq = %dMHz (req = %dMHz), before = %dMHz, perf_limit_reasons = 0x%08X]\n", 1237 act_freq, cur_freq, before_freq, 1238 xe_gt_throttle_get_limit_reasons(gt)); 1239 } else { 1240 xe_gt_dbg(gt, "GuC load: init took %lldms, freq = %dMHz (req = %dMHz), before = %dMHz, status = 0x%08X\n", 1241 delta_ms, act_freq, cur_freq, before_freq, status); 1242 } 1243 1244 return 0; 1245 } 1246 ALLOW_ERROR_INJECTION(guc_wait_ucode, ERRNO); 1247 1248 static int __xe_guc_upload(struct xe_guc *guc) 1249 { 1250 int ret; 1251 1252 /* Raise GT freq to speed up HuC/GuC load */ 1253 xe_guc_pc_raise_unslice(&guc->pc); 1254 1255 guc_write_params(guc); 1256 guc_prepare_xfer(guc); 1257 1258 /* 1259 * Note that GuC needs the CSS header plus uKernel code to be copied 1260 * by the DMA engine in one operation, whereas the RSA signature is 1261 * loaded separately, either by copying it to the UOS_RSA_SCRATCH 1262 * register (if key size <= 256) or through a ggtt-pinned vma (if key 1263 * size > 256). The RSA size and therefore the way we provide it to the 1264 * HW is fixed for each platform and hard-coded in the bootrom. 1265 */ 1266 ret = guc_xfer_rsa(guc); 1267 if (ret) 1268 goto out; 1269 /* 1270 * Current uCode expects the code to be loaded at 8k; locations below 1271 * this are used for the stack. 1272 */ 1273 ret = xe_uc_fw_upload(&guc->fw, 0x2000, UOS_MOVE); 1274 if (ret) 1275 goto out; 1276 1277 /* Wait for authentication */ 1278 ret = guc_wait_ucode(guc); 1279 if (ret) 1280 goto out; 1281 1282 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_RUNNING); 1283 return 0; 1284 1285 out: 1286 xe_uc_fw_change_status(&guc->fw, XE_UC_FIRMWARE_LOAD_FAIL); 1287 return ret; 1288 } 1289 1290 static int vf_guc_min_load_for_hwconfig(struct xe_guc *guc) 1291 { 1292 struct xe_gt *gt = guc_to_gt(guc); 1293 int ret; 1294 1295 ret = xe_guc_hwconfig_init(guc); 1296 if (ret) 1297 return ret; 1298 1299 ret = xe_guc_enable_communication(guc); 1300 if (ret) 1301 return ret; 1302 1303 ret = xe_gt_sriov_vf_connect(gt); 1304 if (ret) 1305 goto err_out; 1306 1307 ret = xe_gt_sriov_vf_query_runtime(gt); 1308 if (ret) 1309 goto err_out; 1310 1311 return 0; 1312 1313 err_out: 1314 xe_guc_sanitize(guc); 1315 return ret; 1316 } 1317 1318 /** 1319 * xe_guc_min_load_for_hwconfig - load minimal GuC and read hwconfig table 1320 * @guc: The GuC object 1321 * 1322 * This function uploads a minimal GuC that does not support submissions but 1323 * in a state where the hwconfig table can be read. Next, it reads and parses 1324 * the hwconfig table so it can be used for subsequent steps in the driver load. 1325 * Lastly, it enables CT communication (XXX: this is needed for PFs/VFs only). 1326 * 1327 * Return: 0 on success, negative error code on error. 1328 */ 1329 int xe_guc_min_load_for_hwconfig(struct xe_guc *guc) 1330 { 1331 int ret; 1332 1333 if (IS_SRIOV_VF(guc_to_xe(guc))) 1334 return vf_guc_min_load_for_hwconfig(guc); 1335 1336 xe_guc_ads_populate_minimal(&guc->ads); 1337 1338 xe_guc_pc_init_early(&guc->pc); 1339 1340 ret = __xe_guc_upload(guc); 1341 if (ret) 1342 return ret; 1343 1344 ret = xe_guc_hwconfig_init(guc); 1345 if (ret) 1346 return ret; 1347 1348 ret = xe_guc_enable_communication(guc); 1349 if (ret) 1350 return ret; 1351 1352 return 0; 1353 } 1354 1355 int xe_guc_upload(struct xe_guc *guc) 1356 { 1357 struct xe_gt *gt = guc_to_gt(guc); 1358 1359 xe_guc_ads_populate(&guc->ads); 1360 1361 if (xe_guc_using_main_gamctrl_queues(guc)) 1362 xe_mmio_write32(>->mmio, MAIN_GAMCTRL_MODE, MAIN_GAMCTRL_QUEUE_SELECT); 1363 1364 return __xe_guc_upload(guc); 1365 } 1366 1367 static void guc_handle_mmio_msg(struct xe_guc *guc) 1368 { 1369 struct xe_gt *gt = guc_to_gt(guc); 1370 u32 msg; 1371 1372 if (IS_SRIOV_VF(guc_to_xe(guc))) 1373 return; 1374 1375 xe_force_wake_assert_held(gt_to_fw(gt), XE_FW_GT); 1376 1377 msg = xe_mmio_read32(>->mmio, SOFT_SCRATCH(15)); 1378 msg &= XE_GUC_RECV_MSG_EXCEPTION | 1379 XE_GUC_RECV_MSG_CRASH_DUMP_POSTED; 1380 xe_mmio_write32(>->mmio, SOFT_SCRATCH(15), 0); 1381 1382 if (msg & XE_GUC_RECV_MSG_CRASH_DUMP_POSTED) 1383 xe_gt_err(gt, "Received early GuC crash dump notification!\n"); 1384 1385 if (msg & XE_GUC_RECV_MSG_EXCEPTION) 1386 xe_gt_err(gt, "Received early GuC exception notification!\n"); 1387 } 1388 1389 static void guc_enable_irq(struct xe_guc *guc) 1390 { 1391 struct xe_gt *gt = guc_to_gt(guc); 1392 u32 events = xe_gt_is_media_type(gt) ? 1393 REG_FIELD_PREP(ENGINE0_MASK, GUC_INTR_GUC2HOST) : 1394 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST); 1395 1396 /* Primary GuC and media GuC share a single enable bit */ 1397 xe_mmio_write32(>->mmio, GUC_SG_INTR_ENABLE, 1398 REG_FIELD_PREP(ENGINE1_MASK, GUC_INTR_GUC2HOST)); 1399 1400 /* 1401 * There are separate mask bits for primary and media GuCs, so use 1402 * a RMW operation to avoid clobbering the other GuC's setting. 1403 */ 1404 xe_mmio_rmw32(>->mmio, GUC_SG_INTR_MASK, events, 0); 1405 } 1406 1407 int xe_guc_enable_communication(struct xe_guc *guc) 1408 { 1409 struct xe_device *xe = guc_to_xe(guc); 1410 int err; 1411 1412 if (IS_SRIOV_VF(xe) && xe_device_has_memirq(xe)) { 1413 struct xe_gt *gt = guc_to_gt(guc); 1414 struct xe_tile *tile = gt_to_tile(gt); 1415 1416 err = xe_memirq_init_guc(&tile->memirq, guc); 1417 if (err) 1418 return err; 1419 } else { 1420 guc_enable_irq(guc); 1421 } 1422 1423 err = xe_guc_ct_enable(&guc->ct); 1424 if (err) 1425 return err; 1426 1427 guc_handle_mmio_msg(guc); 1428 1429 return 0; 1430 } 1431 1432 /** 1433 * xe_guc_softreset() - Soft reset GuC 1434 * @guc: The GuC object 1435 * 1436 * Send soft reset command to GuC through mmio send. 1437 * 1438 * Return: 0 if success, otherwise error code 1439 */ 1440 int xe_guc_softreset(struct xe_guc *guc) 1441 { 1442 u32 action[] = { 1443 XE_GUC_ACTION_CLIENT_SOFT_RESET, 1444 }; 1445 int ret; 1446 1447 if (!xe_uc_fw_is_running(&guc->fw)) 1448 return 0; 1449 1450 ret = xe_guc_mmio_send(guc, action, ARRAY_SIZE(action)); 1451 if (ret) 1452 return ret; 1453 1454 return 0; 1455 } 1456 1457 int xe_guc_suspend(struct xe_guc *guc) 1458 { 1459 struct xe_gt *gt = guc_to_gt(guc); 1460 int ret; 1461 1462 ret = xe_guc_softreset(guc); 1463 if (ret) { 1464 xe_gt_err(gt, "GuC suspend failed: %pe\n", ERR_PTR(ret)); 1465 return ret; 1466 } 1467 1468 xe_guc_sanitize(guc); 1469 return 0; 1470 } 1471 1472 void xe_guc_notify(struct xe_guc *guc) 1473 { 1474 struct xe_gt *gt = guc_to_gt(guc); 1475 const u32 default_notify_data = 0; 1476 1477 /* 1478 * Both GUC_HOST_INTERRUPT and MED_GUC_HOST_INTERRUPT can pass 1479 * additional payload data to the GuC but this capability is not 1480 * used by the firmware yet. Use default value in the meantime. 1481 */ 1482 xe_mmio_write32(>->mmio, guc->notify_reg, default_notify_data); 1483 } 1484 1485 int xe_guc_auth_huc(struct xe_guc *guc, u32 rsa_addr) 1486 { 1487 u32 action[] = { 1488 XE_GUC_ACTION_AUTHENTICATE_HUC, 1489 rsa_addr 1490 }; 1491 1492 return xe_guc_ct_send_block(&guc->ct, action, ARRAY_SIZE(action)); 1493 } 1494 1495 #define MAX_RETRIES_ON_FLR 2 1496 #define MIN_SLEEP_MS_ON_FLR 256 1497 1498 int xe_guc_mmio_send_recv(struct xe_guc *guc, const u32 *request, 1499 u32 len, u32 *response_buf) 1500 { 1501 struct xe_device *xe = guc_to_xe(guc); 1502 struct xe_gt *gt = guc_to_gt(guc); 1503 struct xe_mmio *mmio = >->mmio; 1504 struct xe_reg reply_reg = xe_gt_is_media_type(gt) ? 1505 MED_VF_SW_FLAG(0) : VF_SW_FLAG(0); 1506 const u32 LAST_INDEX = VF_SW_FLAG_COUNT - 1; 1507 unsigned int sleep_period_ms = 1; 1508 unsigned int lost = 0; 1509 u32 header; 1510 int ret; 1511 int i; 1512 1513 BUILD_BUG_ON(VF_SW_FLAG_COUNT != MED_VF_SW_FLAG_COUNT); 1514 1515 xe_assert(xe, len); 1516 xe_assert(xe, len <= VF_SW_FLAG_COUNT); 1517 xe_assert(xe, len <= MED_VF_SW_FLAG_COUNT); 1518 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_ORIGIN, request[0]) == 1519 GUC_HXG_ORIGIN_HOST); 1520 xe_assert(xe, FIELD_GET(GUC_HXG_MSG_0_TYPE, request[0]) == 1521 GUC_HXG_TYPE_REQUEST); 1522 1523 retry: 1524 /* Not in critical data-path, just do if else for GT type */ 1525 if (xe_gt_is_media_type(gt)) { 1526 for (i = 0; i < len; ++i) 1527 xe_mmio_write32(mmio, MED_VF_SW_FLAG(i), 1528 request[i]); 1529 xe_mmio_read32(mmio, MED_VF_SW_FLAG(LAST_INDEX)); 1530 } else { 1531 for (i = 0; i < len; ++i) 1532 xe_mmio_write32(mmio, VF_SW_FLAG(i), 1533 request[i]); 1534 xe_mmio_read32(mmio, VF_SW_FLAG(LAST_INDEX)); 1535 } 1536 1537 xe_guc_notify(guc); 1538 1539 ret = xe_mmio_wait32(mmio, reply_reg, GUC_HXG_MSG_0_ORIGIN, 1540 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_GUC), 1541 50000, &header, false); 1542 if (ret) { 1543 /* scratch registers might be cleared during FLR, try once more */ 1544 if (!header) { 1545 if (++lost > MAX_RETRIES_ON_FLR) { 1546 xe_gt_err(gt, "GuC mmio request %#x: lost, too many retries %u\n", 1547 request[0], lost); 1548 return -ENOLINK; 1549 } 1550 xe_gt_dbg(gt, "GuC mmio request %#x: lost, trying again\n", request[0]); 1551 xe_sleep_relaxed_ms(MIN_SLEEP_MS_ON_FLR); 1552 goto retry; 1553 } 1554 timeout: 1555 xe_gt_err(gt, "GuC mmio request %#x: no reply %#x\n", 1556 request[0], header); 1557 return ret; 1558 } 1559 1560 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1561 GUC_HXG_TYPE_NO_RESPONSE_BUSY) { 1562 /* 1563 * Once we got a BUSY reply we must wait again for the final 1564 * response but this time we can't use ORIGIN mask anymore. 1565 * To spot a right change in the reply, we take advantage that 1566 * response SUCCESS and FAILURE differ only by the single bit 1567 * and all other bits are set and can be used as a new mask. 1568 */ 1569 u32 resp_bits = GUC_HXG_TYPE_RESPONSE_SUCCESS & GUC_HXG_TYPE_RESPONSE_FAILURE; 1570 u32 resp_mask = FIELD_PREP(GUC_HXG_MSG_0_TYPE, resp_bits); 1571 1572 BUILD_BUG_ON(FIELD_MAX(GUC_HXG_MSG_0_TYPE) != GUC_HXG_TYPE_RESPONSE_SUCCESS); 1573 BUILD_BUG_ON((GUC_HXG_TYPE_RESPONSE_SUCCESS ^ GUC_HXG_TYPE_RESPONSE_FAILURE) != 1); 1574 1575 ret = xe_mmio_wait32(mmio, reply_reg, resp_mask, resp_mask, 1576 2000000, &header, false); 1577 1578 if (unlikely(FIELD_GET(GUC_HXG_MSG_0_ORIGIN, header) != 1579 GUC_HXG_ORIGIN_GUC)) 1580 goto proto; 1581 if (unlikely(ret)) { 1582 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1583 GUC_HXG_TYPE_NO_RESPONSE_BUSY) 1584 goto proto; 1585 goto timeout; 1586 } 1587 } 1588 1589 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1590 GUC_HXG_TYPE_NO_RESPONSE_RETRY) { 1591 u32 reason = FIELD_GET(GUC_HXG_RETRY_MSG_0_REASON, header); 1592 1593 xe_gt_dbg(gt, "GuC mmio request %#x: retrying, reason %#x\n", 1594 request[0], reason); 1595 1596 xe_sleep_exponential_ms(&sleep_period_ms, 256); 1597 goto retry; 1598 } 1599 1600 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) == 1601 GUC_HXG_TYPE_RESPONSE_FAILURE) { 1602 u32 hint = FIELD_GET(GUC_HXG_FAILURE_MSG_0_HINT, header); 1603 u32 error = FIELD_GET(GUC_HXG_FAILURE_MSG_0_ERROR, header); 1604 1605 if (unlikely(error == XE_GUC_RESPONSE_VF_MIGRATED)) { 1606 xe_gt_dbg(gt, "GuC mmio request %#x rejected due to MIGRATION (hint %#x)\n", 1607 request[0], hint); 1608 return -EREMCHG; 1609 } 1610 1611 xe_gt_err(gt, "GuC mmio request %#x: failure %#x hint %#x\n", 1612 request[0], error, hint); 1613 return -ENXIO; 1614 } 1615 1616 if (FIELD_GET(GUC_HXG_MSG_0_TYPE, header) != 1617 GUC_HXG_TYPE_RESPONSE_SUCCESS) { 1618 proto: 1619 xe_gt_err(gt, "GuC mmio request %#x: unexpected reply %#x\n", 1620 request[0], header); 1621 return -EPROTO; 1622 } 1623 1624 /* Just copy entire possible message response */ 1625 if (response_buf) { 1626 response_buf[0] = header; 1627 1628 for (i = 1; i < VF_SW_FLAG_COUNT; i++) { 1629 reply_reg.addr += sizeof(u32); 1630 response_buf[i] = xe_mmio_read32(mmio, reply_reg); 1631 } 1632 } 1633 1634 /* Use data from the GuC response as our return value */ 1635 return FIELD_GET(GUC_HXG_RESPONSE_MSG_0_DATA0, header); 1636 } 1637 ALLOW_ERROR_INJECTION(xe_guc_mmio_send_recv, ERRNO); 1638 1639 int xe_guc_mmio_send(struct xe_guc *guc, const u32 *request, u32 len) 1640 { 1641 return xe_guc_mmio_send_recv(guc, request, len, NULL); 1642 } 1643 1644 static int guc_self_cfg(struct xe_guc *guc, u16 key, u16 len, u64 val) 1645 { 1646 struct xe_device *xe = guc_to_xe(guc); 1647 u32 request[HOST2GUC_SELF_CFG_REQUEST_MSG_LEN] = { 1648 FIELD_PREP(GUC_HXG_MSG_0_ORIGIN, GUC_HXG_ORIGIN_HOST) | 1649 FIELD_PREP(GUC_HXG_MSG_0_TYPE, GUC_HXG_TYPE_REQUEST) | 1650 FIELD_PREP(GUC_HXG_REQUEST_MSG_0_ACTION, 1651 GUC_ACTION_HOST2GUC_SELF_CFG), 1652 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_KEY, key) | 1653 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_1_KLV_LEN, len), 1654 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_2_VALUE32, 1655 lower_32_bits(val)), 1656 FIELD_PREP(HOST2GUC_SELF_CFG_REQUEST_MSG_3_VALUE64, 1657 upper_32_bits(val)), 1658 }; 1659 int ret; 1660 1661 xe_assert(xe, len <= 2); 1662 xe_assert(xe, len != 1 || !upper_32_bits(val)); 1663 1664 /* Self config must go over MMIO */ 1665 ret = xe_guc_mmio_send(guc, request, ARRAY_SIZE(request)); 1666 1667 if (unlikely(ret < 0)) 1668 return ret; 1669 if (unlikely(ret > 1)) 1670 return -EPROTO; 1671 if (unlikely(!ret)) 1672 return -ENOKEY; 1673 1674 return 0; 1675 } 1676 1677 int xe_guc_self_cfg32(struct xe_guc *guc, u16 key, u32 val) 1678 { 1679 return guc_self_cfg(guc, key, 1, val); 1680 } 1681 1682 int xe_guc_self_cfg64(struct xe_guc *guc, u16 key, u64 val) 1683 { 1684 return guc_self_cfg(guc, key, 2, val); 1685 } 1686 1687 static void xe_guc_sw_0_irq_handler(struct xe_guc *guc) 1688 { 1689 struct xe_gt *gt = guc_to_gt(guc); 1690 1691 if (IS_SRIOV_VF(gt_to_xe(gt))) 1692 xe_gt_sriov_vf_migrated_event_handler(gt); 1693 } 1694 1695 void xe_guc_irq_handler(struct xe_guc *guc, const u16 iir) 1696 { 1697 if (iir & GUC_INTR_GUC2HOST) 1698 xe_guc_ct_irq_handler(&guc->ct); 1699 1700 if (iir & GUC_INTR_SW_INT_0) 1701 xe_guc_sw_0_irq_handler(guc); 1702 } 1703 1704 void xe_guc_sanitize(struct xe_guc *guc) 1705 { 1706 xe_uc_fw_sanitize(&guc->fw); 1707 xe_guc_ct_disable(&guc->ct); 1708 xe_guc_submit_disable(guc); 1709 } 1710 1711 int xe_guc_reset_prepare(struct xe_guc *guc) 1712 { 1713 return xe_guc_submit_reset_prepare(guc); 1714 } 1715 1716 void xe_guc_reset_wait(struct xe_guc *guc) 1717 { 1718 xe_guc_submit_reset_wait(guc); 1719 } 1720 1721 void xe_guc_stop_prepare(struct xe_guc *guc) 1722 { 1723 if (!IS_SRIOV_VF(guc_to_xe(guc))) 1724 xe_guc_pc_stop(&guc->pc); 1725 } 1726 1727 void xe_guc_stop(struct xe_guc *guc) 1728 { 1729 xe_guc_ct_stop(&guc->ct); 1730 1731 xe_guc_submit_stop(guc); 1732 } 1733 1734 int xe_guc_start(struct xe_guc *guc) 1735 { 1736 return xe_guc_submit_start(guc); 1737 } 1738 1739 /** 1740 * xe_guc_runtime_suspend() - GuC runtime suspend 1741 * @guc: The GuC object 1742 * 1743 * Stop further runs of submission tasks on given GuC and runtime suspend 1744 * GuC CT. 1745 */ 1746 void xe_guc_runtime_suspend(struct xe_guc *guc) 1747 { 1748 xe_guc_submit_pause(guc); 1749 xe_guc_submit_disable(guc); 1750 xe_guc_ct_runtime_suspend(&guc->ct); 1751 } 1752 1753 /** 1754 * xe_guc_runtime_resume() - GuC runtime resume 1755 * @guc: The GuC object 1756 * 1757 * Runtime resume GuC CT and allow further runs of submission tasks on 1758 * given GuC. 1759 */ 1760 void xe_guc_runtime_resume(struct xe_guc *guc) 1761 { 1762 /* 1763 * Runtime PM flows are not applicable for VFs, so it's safe to 1764 * directly enable IRQ. 1765 */ 1766 guc_enable_irq(guc); 1767 1768 xe_guc_ct_runtime_resume(&guc->ct); 1769 xe_guc_submit_enable(guc); 1770 xe_guc_submit_unpause(guc); 1771 } 1772 1773 int xe_guc_print_info(struct xe_guc *guc, struct drm_printer *p) 1774 { 1775 struct xe_gt *gt = guc_to_gt(guc); 1776 u32 status; 1777 int i; 1778 1779 xe_uc_fw_print(&guc->fw, p); 1780 1781 if (!IS_SRIOV_VF(gt_to_xe(gt))) { 1782 CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); 1783 if (!fw_ref.domains) 1784 return -EIO; 1785 1786 status = xe_mmio_read32(>->mmio, GUC_STATUS); 1787 1788 drm_printf(p, "\nGuC status 0x%08x:\n", status); 1789 drm_printf(p, "\tBootrom status = 0x%x\n", 1790 REG_FIELD_GET(GS_BOOTROM_MASK, status)); 1791 drm_printf(p, "\tuKernel status = 0x%x\n", 1792 REG_FIELD_GET(GS_UKERNEL_MASK, status)); 1793 drm_printf(p, "\tMIA Core status = 0x%x\n", 1794 REG_FIELD_GET(GS_MIA_MASK, status)); 1795 drm_printf(p, "\tLog level = %d\n", 1796 xe_guc_log_get_level(&guc->log)); 1797 1798 drm_puts(p, "\nScratch registers:\n"); 1799 for (i = 0; i < SOFT_SCRATCH_COUNT; i++) { 1800 drm_printf(p, "\t%2d: \t0x%x\n", 1801 i, xe_mmio_read32(>->mmio, SOFT_SCRATCH(i))); 1802 } 1803 } 1804 1805 drm_puts(p, "\n"); 1806 xe_guc_ct_print(&guc->ct, p, false); 1807 1808 drm_puts(p, "\n"); 1809 xe_guc_submit_print(guc, p); 1810 1811 return 0; 1812 } 1813 1814 /** 1815 * xe_guc_declare_wedged() - Declare GuC wedged 1816 * @guc: the GuC object 1817 * 1818 * Wedge the GuC which stops all submission, saves desired debug state, and 1819 * cleans up anything which could timeout. 1820 */ 1821 void xe_guc_declare_wedged(struct xe_guc *guc) 1822 { 1823 xe_gt_assert(guc_to_gt(guc), guc_to_xe(guc)->wedged.mode); 1824 1825 xe_guc_reset_prepare(guc); 1826 xe_guc_ct_stop(&guc->ct); 1827 xe_guc_submit_wedge(guc); 1828 } 1829 1830 /** 1831 * xe_guc_using_main_gamctrl_queues() - Detect which reporting queues to use. 1832 * @guc: The GuC object 1833 * 1834 * For Xe3p and beyond, we want to program the hardware to use the 1835 * "Main GAMCTRL queue" rather than the legacy queue before we upload 1836 * the GuC firmware. This will allow the GuC to use a new set of 1837 * registers for pagefault handling and avoid some unnecessary 1838 * complications with MCR register range handling. 1839 * 1840 * Return: true if can use new main gamctrl queues. 1841 */ 1842 bool xe_guc_using_main_gamctrl_queues(struct xe_guc *guc) 1843 { 1844 struct xe_gt *gt = guc_to_gt(guc); 1845 1846 /* 1847 * For Xe3p media gt (35), the GuC and the CS subunits may be still Xe3 1848 * that lacks the Main GAMCTRL support. Reserved bits from the GMD_ID 1849 * inform the IP version of the subunits. 1850 */ 1851 if (xe_gt_is_media_type(gt) && MEDIA_VER(gt_to_xe(gt)) == 35) { 1852 u32 val = xe_mmio_read32(>->mmio, GMD_ID); 1853 u32 subip = REG_FIELD_GET(GMD_ID_SUBIP_FLAG_MASK, val); 1854 1855 if (!subip) 1856 return true; 1857 1858 xe_gt_WARN(gt, subip != 1, 1859 "GMD_ID has unknown value in the SUBIP_FLAG field - 0x%x\n", 1860 subip); 1861 1862 return false; 1863 } 1864 1865 return GT_VER(gt) >= 35; 1866 } 1867 1868 bool xe_guc_has_paging_engine(struct xe_guc *guc) 1869 { 1870 struct xe_gt *gt = guc_to_gt(guc); 1871 struct xe_device *xe = gt_to_xe(gt); 1872 1873 /* 1874 * On newer platforms the GuC now has a dedicated engine class for the 1875 * special PAGING engine, which is the driver reserved BCS engine used 1876 * for KMD paging/binding operations. GuC requires KMD to refer to this 1877 * using the special PAGING engine class. Note that there is no new hw 1878 * engine here, this is purely a sw view in the GuC itself, which we 1879 * need to respect. 1880 */ 1881 1882 if (IS_SRIOV_VF(xe)) 1883 return xe_gt_sriov_vf_paging_engines(gt); 1884 1885 return xe->info.platform >= XE_NOVALAKE_S && 1886 GUC_FIRMWARE_VER_AT_LEAST(guc, 70, 69, 0); 1887 } 1888 1889 /** 1890 * xe_hwe_guc_logical_instance - Get the GuC-aligned logical instance of a 1891 * hardware engine. 1892 * @hwe: Hardware engine. 1893 * 1894 * For GuC backend usage, we should no longer use the raw logical instance 1895 * directly. This helper must be used to retrieve the logical instance of the 1896 * hardware engine, taking care of any necessary adjustments (such as the GuC 1897 * PAGING engine mapping). This is assumed to be used in conjunction with the 1898 * GuC engine class. 1899 * 1900 * Return: Logical instance, taking into account for stuff like GuC PAGING 1901 * engine mapping. 1902 */ 1903 u16 xe_hwe_guc_logical_instance(struct xe_hw_engine *hwe) 1904 { 1905 struct xe_gt *gt = hwe->gt; 1906 1907 if (xe_guc_has_paging_engine(&hwe->gt->uc.guc) && 1908 xe_gt_is_usm_hwe(gt, hwe)) { 1909 int shift = gt->usm.paging_hwe0->logical_instance; 1910 1911 xe_gt_assert(gt, shift <= hwe->logical_instance); 1912 1913 /* GUC_PAGING_CLASS:guc_logical_instance */ 1914 return hwe->logical_instance - shift; 1915 } 1916 1917 return hwe->logical_instance; 1918 } 1919 1920 #if IS_ENABLED(CONFIG_DRM_XE_KUNIT_TEST) 1921 #include "tests/xe_guc_g2g_test.c" 1922 #endif 1923