1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt_pagefault.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/circ_buf.h> 10 11 #include <drm/drm_exec.h> 12 #include <drm/drm_managed.h> 13 #include <drm/ttm/ttm_execbuf_util.h> 14 15 #include "abi/guc_actions_abi.h" 16 #include "xe_bo.h" 17 #include "xe_gt.h" 18 #include "xe_gt_tlb_invalidation.h" 19 #include "xe_guc.h" 20 #include "xe_guc_ct.h" 21 #include "xe_migrate.h" 22 #include "xe_trace_bo.h" 23 #include "xe_vm.h" 24 25 struct pagefault { 26 u64 page_addr; 27 u32 asid; 28 u16 pdata; 29 u8 vfid; 30 u8 access_type; 31 u8 fault_type; 32 u8 fault_level; 33 u8 engine_class; 34 u8 engine_instance; 35 u8 fault_unsuccessful; 36 bool trva_fault; 37 }; 38 39 enum access_type { 40 ACCESS_TYPE_READ = 0, 41 ACCESS_TYPE_WRITE = 1, 42 ACCESS_TYPE_ATOMIC = 2, 43 ACCESS_TYPE_RESERVED = 3, 44 }; 45 46 enum fault_type { 47 NOT_PRESENT = 0, 48 WRITE_ACCESS_VIOLATION = 1, 49 ATOMIC_ACCESS_VIOLATION = 2, 50 }; 51 52 struct acc { 53 u64 va_range_base; 54 u32 asid; 55 u32 sub_granularity; 56 u8 granularity; 57 u8 vfid; 58 u8 access_type; 59 u8 engine_class; 60 u8 engine_instance; 61 }; 62 63 static bool access_is_atomic(enum access_type access_type) 64 { 65 return access_type == ACCESS_TYPE_ATOMIC; 66 } 67 68 static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma) 69 { 70 return BIT(tile->id) & vma->tile_present && 71 !(BIT(tile->id) & vma->tile_invalidated); 72 } 73 74 static bool vma_matches(struct xe_vma *vma, u64 page_addr) 75 { 76 if (page_addr > xe_vma_end(vma) - 1 || 77 page_addr + SZ_4K - 1 < xe_vma_start(vma)) 78 return false; 79 80 return true; 81 } 82 83 static struct xe_vma *lookup_vma(struct xe_vm *vm, u64 page_addr) 84 { 85 struct xe_vma *vma = NULL; 86 87 if (vm->usm.last_fault_vma) { /* Fast lookup */ 88 if (vma_matches(vm->usm.last_fault_vma, page_addr)) 89 vma = vm->usm.last_fault_vma; 90 } 91 if (!vma) 92 vma = xe_vm_find_overlapping_vma(vm, page_addr, SZ_4K); 93 94 return vma; 95 } 96 97 static int xe_pf_begin(struct drm_exec *exec, struct xe_vma *vma, 98 bool atomic, unsigned int id) 99 { 100 struct xe_bo *bo = xe_vma_bo(vma); 101 struct xe_vm *vm = xe_vma_vm(vma); 102 int err; 103 104 err = xe_vm_lock_vma(exec, vma); 105 if (err) 106 return err; 107 108 if (atomic && IS_DGFX(vm->xe)) { 109 if (xe_vma_is_userptr(vma)) { 110 err = -EACCES; 111 return err; 112 } 113 114 /* Migrate to VRAM, move should invalidate the VMA first */ 115 err = xe_bo_migrate(bo, XE_PL_VRAM0 + id); 116 if (err) 117 return err; 118 } else if (bo) { 119 /* Create backing store if needed */ 120 err = xe_bo_validate(bo, vm, true); 121 if (err) 122 return err; 123 } 124 125 return 0; 126 } 127 128 static int handle_vma_pagefault(struct xe_tile *tile, struct pagefault *pf, 129 struct xe_vma *vma) 130 { 131 struct xe_vm *vm = xe_vma_vm(vma); 132 struct drm_exec exec; 133 struct dma_fence *fence; 134 ktime_t end = 0; 135 int err; 136 bool atomic; 137 138 trace_xe_vma_pagefault(vma); 139 atomic = access_is_atomic(pf->access_type); 140 141 /* Check if VMA is valid */ 142 if (vma_is_valid(tile, vma) && !atomic) 143 return 0; 144 145 retry_userptr: 146 if (xe_vma_is_userptr(vma) && 147 xe_vma_userptr_check_repin(to_userptr_vma(vma))) { 148 struct xe_userptr_vma *uvma = to_userptr_vma(vma); 149 150 err = xe_vma_userptr_pin_pages(uvma); 151 if (err) 152 return err; 153 } 154 155 /* Lock VM and BOs dma-resv */ 156 drm_exec_init(&exec, 0, 0); 157 drm_exec_until_all_locked(&exec) { 158 err = xe_pf_begin(&exec, vma, atomic, tile->id); 159 drm_exec_retry_on_contention(&exec); 160 if (xe_vm_validate_should_retry(&exec, err, &end)) 161 err = -EAGAIN; 162 if (err) 163 goto unlock_dma_resv; 164 165 /* Bind VMA only to the GT that has faulted */ 166 trace_xe_vma_pf_bind(vma); 167 fence = xe_vma_rebind(vm, vma, BIT(tile->id)); 168 if (IS_ERR(fence)) { 169 err = PTR_ERR(fence); 170 if (xe_vm_validate_should_retry(&exec, err, &end)) 171 err = -EAGAIN; 172 goto unlock_dma_resv; 173 } 174 } 175 176 dma_fence_wait(fence, false); 177 dma_fence_put(fence); 178 vma->tile_invalidated &= ~BIT(tile->id); 179 180 unlock_dma_resv: 181 drm_exec_fini(&exec); 182 if (err == -EAGAIN) 183 goto retry_userptr; 184 185 return err; 186 } 187 188 static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf) 189 { 190 struct xe_device *xe = gt_to_xe(gt); 191 struct xe_tile *tile = gt_to_tile(gt); 192 struct xe_vm *vm; 193 struct xe_vma *vma = NULL; 194 int err; 195 196 /* SW isn't expected to handle TRTT faults */ 197 if (pf->trva_fault) 198 return -EFAULT; 199 200 /* ASID to VM */ 201 mutex_lock(&xe->usm.lock); 202 vm = xa_load(&xe->usm.asid_to_vm, pf->asid); 203 if (vm && xe_vm_in_fault_mode(vm)) 204 xe_vm_get(vm); 205 else 206 vm = NULL; 207 mutex_unlock(&xe->usm.lock); 208 if (!vm) 209 return -EINVAL; 210 211 /* 212 * TODO: Change to read lock? Using write lock for simplicity. 213 */ 214 down_write(&vm->lock); 215 vma = lookup_vma(vm, pf->page_addr); 216 if (!vma) { 217 err = -EINVAL; 218 goto unlock_vm; 219 } 220 221 err = handle_vma_pagefault(tile, pf, vma); 222 223 unlock_vm: 224 if (!err) 225 vm->usm.last_fault_vma = vma; 226 up_write(&vm->lock); 227 xe_vm_put(vm); 228 229 return err; 230 } 231 232 static int send_pagefault_reply(struct xe_guc *guc, 233 struct xe_guc_pagefault_reply *reply) 234 { 235 u32 action[] = { 236 XE_GUC_ACTION_PAGE_FAULT_RES_DESC, 237 reply->dw0, 238 reply->dw1, 239 }; 240 241 return xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); 242 } 243 244 static void print_pagefault(struct xe_device *xe, struct pagefault *pf) 245 { 246 drm_dbg(&xe->drm, "\n\tASID: %d\n" 247 "\tVFID: %d\n" 248 "\tPDATA: 0x%04x\n" 249 "\tFaulted Address: 0x%08x%08x\n" 250 "\tFaultType: %d\n" 251 "\tAccessType: %d\n" 252 "\tFaultLevel: %d\n" 253 "\tEngineClass: %d\n" 254 "\tEngineInstance: %d\n", 255 pf->asid, pf->vfid, pf->pdata, upper_32_bits(pf->page_addr), 256 lower_32_bits(pf->page_addr), 257 pf->fault_type, pf->access_type, pf->fault_level, 258 pf->engine_class, pf->engine_instance); 259 } 260 261 #define PF_MSG_LEN_DW 4 262 263 static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf) 264 { 265 const struct xe_guc_pagefault_desc *desc; 266 bool ret = false; 267 268 spin_lock_irq(&pf_queue->lock); 269 if (pf_queue->tail != pf_queue->head) { 270 desc = (const struct xe_guc_pagefault_desc *) 271 (pf_queue->data + pf_queue->tail); 272 273 pf->fault_level = FIELD_GET(PFD_FAULT_LEVEL, desc->dw0); 274 pf->trva_fault = FIELD_GET(XE2_PFD_TRVA_FAULT, desc->dw0); 275 pf->engine_class = FIELD_GET(PFD_ENG_CLASS, desc->dw0); 276 pf->engine_instance = FIELD_GET(PFD_ENG_INSTANCE, desc->dw0); 277 pf->pdata = FIELD_GET(PFD_PDATA_HI, desc->dw1) << 278 PFD_PDATA_HI_SHIFT; 279 pf->pdata |= FIELD_GET(PFD_PDATA_LO, desc->dw0); 280 pf->asid = FIELD_GET(PFD_ASID, desc->dw1); 281 pf->vfid = FIELD_GET(PFD_VFID, desc->dw2); 282 pf->access_type = FIELD_GET(PFD_ACCESS_TYPE, desc->dw2); 283 pf->fault_type = FIELD_GET(PFD_FAULT_TYPE, desc->dw2); 284 pf->page_addr = (u64)(FIELD_GET(PFD_VIRTUAL_ADDR_HI, desc->dw3)) << 285 PFD_VIRTUAL_ADDR_HI_SHIFT; 286 pf->page_addr |= FIELD_GET(PFD_VIRTUAL_ADDR_LO, desc->dw2) << 287 PFD_VIRTUAL_ADDR_LO_SHIFT; 288 289 pf_queue->tail = (pf_queue->tail + PF_MSG_LEN_DW) % 290 pf_queue->num_dw; 291 ret = true; 292 } 293 spin_unlock_irq(&pf_queue->lock); 294 295 return ret; 296 } 297 298 static bool pf_queue_full(struct pf_queue *pf_queue) 299 { 300 lockdep_assert_held(&pf_queue->lock); 301 302 return CIRC_SPACE(pf_queue->head, pf_queue->tail, 303 pf_queue->num_dw) <= 304 PF_MSG_LEN_DW; 305 } 306 307 int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len) 308 { 309 struct xe_gt *gt = guc_to_gt(guc); 310 struct xe_device *xe = gt_to_xe(gt); 311 struct pf_queue *pf_queue; 312 unsigned long flags; 313 u32 asid; 314 bool full; 315 316 if (unlikely(len != PF_MSG_LEN_DW)) 317 return -EPROTO; 318 319 asid = FIELD_GET(PFD_ASID, msg[1]); 320 pf_queue = gt->usm.pf_queue + (asid % NUM_PF_QUEUE); 321 322 /* 323 * The below logic doesn't work unless PF_QUEUE_NUM_DW % PF_MSG_LEN_DW == 0 324 */ 325 xe_gt_assert(gt, !(pf_queue->num_dw % PF_MSG_LEN_DW)); 326 327 spin_lock_irqsave(&pf_queue->lock, flags); 328 full = pf_queue_full(pf_queue); 329 if (!full) { 330 memcpy(pf_queue->data + pf_queue->head, msg, len * sizeof(u32)); 331 pf_queue->head = (pf_queue->head + len) % 332 pf_queue->num_dw; 333 queue_work(gt->usm.pf_wq, &pf_queue->worker); 334 } else { 335 drm_warn(&xe->drm, "PF Queue full, shouldn't be possible"); 336 } 337 spin_unlock_irqrestore(&pf_queue->lock, flags); 338 339 return full ? -ENOSPC : 0; 340 } 341 342 #define USM_QUEUE_MAX_RUNTIME_MS 20 343 344 static void pf_queue_work_func(struct work_struct *w) 345 { 346 struct pf_queue *pf_queue = container_of(w, struct pf_queue, worker); 347 struct xe_gt *gt = pf_queue->gt; 348 struct xe_device *xe = gt_to_xe(gt); 349 struct xe_guc_pagefault_reply reply = {}; 350 struct pagefault pf = {}; 351 unsigned long threshold; 352 int ret; 353 354 threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS); 355 356 while (get_pagefault(pf_queue, &pf)) { 357 ret = handle_pagefault(gt, &pf); 358 if (unlikely(ret)) { 359 print_pagefault(xe, &pf); 360 pf.fault_unsuccessful = 1; 361 drm_dbg(&xe->drm, "Fault response: Unsuccessful %d\n", ret); 362 } 363 364 reply.dw0 = FIELD_PREP(PFR_VALID, 1) | 365 FIELD_PREP(PFR_SUCCESS, pf.fault_unsuccessful) | 366 FIELD_PREP(PFR_REPLY, PFR_ACCESS) | 367 FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) | 368 FIELD_PREP(PFR_ASID, pf.asid); 369 370 reply.dw1 = FIELD_PREP(PFR_VFID, pf.vfid) | 371 FIELD_PREP(PFR_ENG_INSTANCE, pf.engine_instance) | 372 FIELD_PREP(PFR_ENG_CLASS, pf.engine_class) | 373 FIELD_PREP(PFR_PDATA, pf.pdata); 374 375 send_pagefault_reply(>->uc.guc, &reply); 376 377 if (time_after(jiffies, threshold) && 378 pf_queue->tail != pf_queue->head) { 379 queue_work(gt->usm.pf_wq, w); 380 break; 381 } 382 } 383 } 384 385 static void acc_queue_work_func(struct work_struct *w); 386 387 static void pagefault_fini(void *arg) 388 { 389 struct xe_gt *gt = arg; 390 struct xe_device *xe = gt_to_xe(gt); 391 392 if (!xe->info.has_usm) 393 return; 394 395 destroy_workqueue(gt->usm.acc_wq); 396 destroy_workqueue(gt->usm.pf_wq); 397 } 398 399 static int xe_alloc_pf_queue(struct xe_gt *gt, struct pf_queue *pf_queue) 400 { 401 struct xe_device *xe = gt_to_xe(gt); 402 xe_dss_mask_t all_dss; 403 int num_dss, num_eus; 404 405 bitmap_or(all_dss, gt->fuse_topo.g_dss_mask, gt->fuse_topo.c_dss_mask, 406 XE_MAX_DSS_FUSE_BITS); 407 408 num_dss = bitmap_weight(all_dss, XE_MAX_DSS_FUSE_BITS); 409 num_eus = bitmap_weight(gt->fuse_topo.eu_mask_per_dss, 410 XE_MAX_EU_FUSE_BITS) * num_dss; 411 412 /* user can issue separate page faults per EU and per CS */ 413 pf_queue->num_dw = 414 (num_eus + XE_NUM_HW_ENGINES) * PF_MSG_LEN_DW; 415 416 pf_queue->gt = gt; 417 pf_queue->data = devm_kcalloc(xe->drm.dev, pf_queue->num_dw, 418 sizeof(u32), GFP_KERNEL); 419 if (!pf_queue->data) 420 return -ENOMEM; 421 422 spin_lock_init(&pf_queue->lock); 423 INIT_WORK(&pf_queue->worker, pf_queue_work_func); 424 425 return 0; 426 } 427 428 int xe_gt_pagefault_init(struct xe_gt *gt) 429 { 430 struct xe_device *xe = gt_to_xe(gt); 431 int i, ret = 0; 432 433 if (!xe->info.has_usm) 434 return 0; 435 436 for (i = 0; i < NUM_PF_QUEUE; ++i) { 437 ret = xe_alloc_pf_queue(gt, >->usm.pf_queue[i]); 438 if (ret) 439 return ret; 440 } 441 for (i = 0; i < NUM_ACC_QUEUE; ++i) { 442 gt->usm.acc_queue[i].gt = gt; 443 spin_lock_init(>->usm.acc_queue[i].lock); 444 INIT_WORK(>->usm.acc_queue[i].worker, acc_queue_work_func); 445 } 446 447 gt->usm.pf_wq = alloc_workqueue("xe_gt_page_fault_work_queue", 448 WQ_UNBOUND | WQ_HIGHPRI, NUM_PF_QUEUE); 449 if (!gt->usm.pf_wq) 450 return -ENOMEM; 451 452 gt->usm.acc_wq = alloc_workqueue("xe_gt_access_counter_work_queue", 453 WQ_UNBOUND | WQ_HIGHPRI, 454 NUM_ACC_QUEUE); 455 if (!gt->usm.acc_wq) { 456 destroy_workqueue(gt->usm.pf_wq); 457 return -ENOMEM; 458 } 459 460 return devm_add_action_or_reset(xe->drm.dev, pagefault_fini, gt); 461 } 462 463 void xe_gt_pagefault_reset(struct xe_gt *gt) 464 { 465 struct xe_device *xe = gt_to_xe(gt); 466 int i; 467 468 if (!xe->info.has_usm) 469 return; 470 471 for (i = 0; i < NUM_PF_QUEUE; ++i) { 472 spin_lock_irq(>->usm.pf_queue[i].lock); 473 gt->usm.pf_queue[i].head = 0; 474 gt->usm.pf_queue[i].tail = 0; 475 spin_unlock_irq(>->usm.pf_queue[i].lock); 476 } 477 478 for (i = 0; i < NUM_ACC_QUEUE; ++i) { 479 spin_lock(>->usm.acc_queue[i].lock); 480 gt->usm.acc_queue[i].head = 0; 481 gt->usm.acc_queue[i].tail = 0; 482 spin_unlock(>->usm.acc_queue[i].lock); 483 } 484 } 485 486 static int granularity_in_byte(int val) 487 { 488 switch (val) { 489 case 0: 490 return SZ_128K; 491 case 1: 492 return SZ_2M; 493 case 2: 494 return SZ_16M; 495 case 3: 496 return SZ_64M; 497 default: 498 return 0; 499 } 500 } 501 502 static int sub_granularity_in_byte(int val) 503 { 504 return (granularity_in_byte(val) / 32); 505 } 506 507 static void print_acc(struct xe_device *xe, struct acc *acc) 508 { 509 drm_warn(&xe->drm, "Access counter request:\n" 510 "\tType: %s\n" 511 "\tASID: %d\n" 512 "\tVFID: %d\n" 513 "\tEngine: %d:%d\n" 514 "\tGranularity: 0x%x KB Region/ %d KB sub-granularity\n" 515 "\tSub_Granularity Vector: 0x%08x\n" 516 "\tVA Range base: 0x%016llx\n", 517 acc->access_type ? "AC_NTFY_VAL" : "AC_TRIG_VAL", 518 acc->asid, acc->vfid, acc->engine_class, acc->engine_instance, 519 granularity_in_byte(acc->granularity) / SZ_1K, 520 sub_granularity_in_byte(acc->granularity) / SZ_1K, 521 acc->sub_granularity, acc->va_range_base); 522 } 523 524 static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc) 525 { 526 u64 page_va = acc->va_range_base + (ffs(acc->sub_granularity) - 1) * 527 sub_granularity_in_byte(acc->granularity); 528 529 return xe_vm_find_overlapping_vma(vm, page_va, SZ_4K); 530 } 531 532 static int handle_acc(struct xe_gt *gt, struct acc *acc) 533 { 534 struct xe_device *xe = gt_to_xe(gt); 535 struct xe_tile *tile = gt_to_tile(gt); 536 struct drm_exec exec; 537 struct xe_vm *vm; 538 struct xe_vma *vma; 539 int ret = 0; 540 541 /* We only support ACC_TRIGGER at the moment */ 542 if (acc->access_type != ACC_TRIGGER) 543 return -EINVAL; 544 545 /* ASID to VM */ 546 mutex_lock(&xe->usm.lock); 547 vm = xa_load(&xe->usm.asid_to_vm, acc->asid); 548 if (vm) 549 xe_vm_get(vm); 550 mutex_unlock(&xe->usm.lock); 551 if (!vm || !xe_vm_in_fault_mode(vm)) 552 return -EINVAL; 553 554 down_read(&vm->lock); 555 556 /* Lookup VMA */ 557 vma = get_acc_vma(vm, acc); 558 if (!vma) { 559 ret = -EINVAL; 560 goto unlock_vm; 561 } 562 563 trace_xe_vma_acc(vma); 564 565 /* Userptr or null can't be migrated, nothing to do */ 566 if (xe_vma_has_no_bo(vma)) 567 goto unlock_vm; 568 569 /* Lock VM and BOs dma-resv */ 570 drm_exec_init(&exec, 0, 0); 571 drm_exec_until_all_locked(&exec) { 572 ret = xe_pf_begin(&exec, vma, true, tile->id); 573 drm_exec_retry_on_contention(&exec); 574 if (ret) 575 break; 576 } 577 578 drm_exec_fini(&exec); 579 unlock_vm: 580 up_read(&vm->lock); 581 xe_vm_put(vm); 582 583 return ret; 584 } 585 586 #define make_u64(hi__, low__) ((u64)(hi__) << 32 | (u64)(low__)) 587 588 #define ACC_MSG_LEN_DW 4 589 590 static bool get_acc(struct acc_queue *acc_queue, struct acc *acc) 591 { 592 const struct xe_guc_acc_desc *desc; 593 bool ret = false; 594 595 spin_lock(&acc_queue->lock); 596 if (acc_queue->tail != acc_queue->head) { 597 desc = (const struct xe_guc_acc_desc *) 598 (acc_queue->data + acc_queue->tail); 599 600 acc->granularity = FIELD_GET(ACC_GRANULARITY, desc->dw2); 601 acc->sub_granularity = FIELD_GET(ACC_SUBG_HI, desc->dw1) << 31 | 602 FIELD_GET(ACC_SUBG_LO, desc->dw0); 603 acc->engine_class = FIELD_GET(ACC_ENG_CLASS, desc->dw1); 604 acc->engine_instance = FIELD_GET(ACC_ENG_INSTANCE, desc->dw1); 605 acc->asid = FIELD_GET(ACC_ASID, desc->dw1); 606 acc->vfid = FIELD_GET(ACC_VFID, desc->dw2); 607 acc->access_type = FIELD_GET(ACC_TYPE, desc->dw0); 608 acc->va_range_base = make_u64(desc->dw3 & ACC_VIRTUAL_ADDR_RANGE_HI, 609 desc->dw2 & ACC_VIRTUAL_ADDR_RANGE_LO); 610 611 acc_queue->tail = (acc_queue->tail + ACC_MSG_LEN_DW) % 612 ACC_QUEUE_NUM_DW; 613 ret = true; 614 } 615 spin_unlock(&acc_queue->lock); 616 617 return ret; 618 } 619 620 static void acc_queue_work_func(struct work_struct *w) 621 { 622 struct acc_queue *acc_queue = container_of(w, struct acc_queue, worker); 623 struct xe_gt *gt = acc_queue->gt; 624 struct xe_device *xe = gt_to_xe(gt); 625 struct acc acc = {}; 626 unsigned long threshold; 627 int ret; 628 629 threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS); 630 631 while (get_acc(acc_queue, &acc)) { 632 ret = handle_acc(gt, &acc); 633 if (unlikely(ret)) { 634 print_acc(xe, &acc); 635 drm_warn(&xe->drm, "ACC: Unsuccessful %d\n", ret); 636 } 637 638 if (time_after(jiffies, threshold) && 639 acc_queue->tail != acc_queue->head) { 640 queue_work(gt->usm.acc_wq, w); 641 break; 642 } 643 } 644 } 645 646 static bool acc_queue_full(struct acc_queue *acc_queue) 647 { 648 lockdep_assert_held(&acc_queue->lock); 649 650 return CIRC_SPACE(acc_queue->head, acc_queue->tail, ACC_QUEUE_NUM_DW) <= 651 ACC_MSG_LEN_DW; 652 } 653 654 int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len) 655 { 656 struct xe_gt *gt = guc_to_gt(guc); 657 struct acc_queue *acc_queue; 658 u32 asid; 659 bool full; 660 661 /* 662 * The below logic doesn't work unless ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0 663 */ 664 BUILD_BUG_ON(ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW); 665 666 if (unlikely(len != ACC_MSG_LEN_DW)) 667 return -EPROTO; 668 669 asid = FIELD_GET(ACC_ASID, msg[1]); 670 acc_queue = >->usm.acc_queue[asid % NUM_ACC_QUEUE]; 671 672 spin_lock(&acc_queue->lock); 673 full = acc_queue_full(acc_queue); 674 if (!full) { 675 memcpy(acc_queue->data + acc_queue->head, msg, 676 len * sizeof(u32)); 677 acc_queue->head = (acc_queue->head + len) % ACC_QUEUE_NUM_DW; 678 queue_work(gt->usm.acc_wq, &acc_queue->worker); 679 } else { 680 drm_warn(>_to_xe(gt)->drm, "ACC Queue full, dropping ACC"); 681 } 682 spin_unlock(&acc_queue->lock); 683 684 return full ? -ENOSPC : 0; 685 } 686