1 // SPDX-License-Identifier: MIT 2 /* 3 * Copyright © 2022 Intel Corporation 4 */ 5 6 #include "xe_gt_pagefault.h" 7 8 #include <linux/bitfield.h> 9 #include <linux/circ_buf.h> 10 11 #include <drm/drm_exec.h> 12 #include <drm/drm_managed.h> 13 #include <drm/ttm/ttm_execbuf_util.h> 14 15 #include "abi/guc_actions_abi.h" 16 #include "xe_bo.h" 17 #include "xe_gt.h" 18 #include "xe_gt_tlb_invalidation.h" 19 #include "xe_guc.h" 20 #include "xe_guc_ct.h" 21 #include "xe_migrate.h" 22 #include "xe_trace_bo.h" 23 #include "xe_vm.h" 24 25 struct pagefault { 26 u64 page_addr; 27 u32 asid; 28 u16 pdata; 29 u8 vfid; 30 u8 access_type; 31 u8 fault_type; 32 u8 fault_level; 33 u8 engine_class; 34 u8 engine_instance; 35 u8 fault_unsuccessful; 36 bool trva_fault; 37 }; 38 39 enum access_type { 40 ACCESS_TYPE_READ = 0, 41 ACCESS_TYPE_WRITE = 1, 42 ACCESS_TYPE_ATOMIC = 2, 43 ACCESS_TYPE_RESERVED = 3, 44 }; 45 46 enum fault_type { 47 NOT_PRESENT = 0, 48 WRITE_ACCESS_VIOLATION = 1, 49 ATOMIC_ACCESS_VIOLATION = 2, 50 }; 51 52 struct acc { 53 u64 va_range_base; 54 u32 asid; 55 u32 sub_granularity; 56 u8 granularity; 57 u8 vfid; 58 u8 access_type; 59 u8 engine_class; 60 u8 engine_instance; 61 }; 62 63 static bool access_is_atomic(enum access_type access_type) 64 { 65 return access_type == ACCESS_TYPE_ATOMIC; 66 } 67 68 static bool vma_is_valid(struct xe_tile *tile, struct xe_vma *vma) 69 { 70 return BIT(tile->id) & vma->tile_present && 71 !(BIT(tile->id) & vma->tile_invalidated); 72 } 73 74 static bool vma_matches(struct xe_vma *vma, u64 page_addr) 75 { 76 if (page_addr > xe_vma_end(vma) - 1 || 77 page_addr + SZ_4K - 1 < xe_vma_start(vma)) 78 return false; 79 80 return true; 81 } 82 83 static struct xe_vma *lookup_vma(struct xe_vm *vm, u64 page_addr) 84 { 85 struct xe_vma *vma = NULL; 86 87 if (vm->usm.last_fault_vma) { /* Fast lookup */ 88 if (vma_matches(vm->usm.last_fault_vma, page_addr)) 89 vma = vm->usm.last_fault_vma; 90 } 91 if (!vma) 92 vma = xe_vm_find_overlapping_vma(vm, page_addr, SZ_4K); 93 94 return vma; 95 } 96 97 static int xe_pf_begin(struct drm_exec *exec, struct xe_vma *vma, 98 bool atomic, unsigned int id) 99 { 100 struct xe_bo *bo = xe_vma_bo(vma); 101 struct xe_vm *vm = xe_vma_vm(vma); 102 int err; 103 104 err = xe_vm_lock_vma(exec, vma); 105 if (err) 106 return err; 107 108 if (atomic && IS_DGFX(vm->xe)) { 109 if (xe_vma_is_userptr(vma)) { 110 err = -EACCES; 111 return err; 112 } 113 114 /* Migrate to VRAM, move should invalidate the VMA first */ 115 err = xe_bo_migrate(bo, XE_PL_VRAM0 + id); 116 if (err) 117 return err; 118 } else if (bo) { 119 /* Create backing store if needed */ 120 err = xe_bo_validate(bo, vm, true); 121 if (err) 122 return err; 123 } 124 125 return 0; 126 } 127 128 static int handle_vma_pagefault(struct xe_tile *tile, struct pagefault *pf, 129 struct xe_vma *vma) 130 { 131 struct xe_vm *vm = xe_vma_vm(vma); 132 struct drm_exec exec; 133 struct dma_fence *fence; 134 ktime_t end = 0; 135 int err; 136 bool atomic; 137 138 trace_xe_vma_pagefault(vma); 139 atomic = access_is_atomic(pf->access_type); 140 141 /* Check if VMA is valid */ 142 if (vma_is_valid(tile, vma) && !atomic) 143 return 0; 144 145 retry_userptr: 146 if (xe_vma_is_userptr(vma) && 147 xe_vma_userptr_check_repin(to_userptr_vma(vma))) { 148 struct xe_userptr_vma *uvma = to_userptr_vma(vma); 149 150 err = xe_vma_userptr_pin_pages(uvma); 151 if (err) 152 return err; 153 } 154 155 /* Lock VM and BOs dma-resv */ 156 drm_exec_init(&exec, 0, 0); 157 drm_exec_until_all_locked(&exec) { 158 err = xe_pf_begin(&exec, vma, atomic, tile->id); 159 drm_exec_retry_on_contention(&exec); 160 if (xe_vm_validate_should_retry(&exec, err, &end)) 161 err = -EAGAIN; 162 if (err) 163 goto unlock_dma_resv; 164 165 /* Bind VMA only to the GT that has faulted */ 166 trace_xe_vma_pf_bind(vma); 167 fence = xe_vma_rebind(vm, vma, BIT(tile->id)); 168 if (IS_ERR(fence)) { 169 err = PTR_ERR(fence); 170 if (xe_vm_validate_should_retry(&exec, err, &end)) 171 err = -EAGAIN; 172 goto unlock_dma_resv; 173 } 174 } 175 176 dma_fence_wait(fence, false); 177 dma_fence_put(fence); 178 vma->tile_invalidated &= ~BIT(tile->id); 179 180 unlock_dma_resv: 181 drm_exec_fini(&exec); 182 if (err == -EAGAIN) 183 goto retry_userptr; 184 185 return err; 186 } 187 188 static int handle_pagefault(struct xe_gt *gt, struct pagefault *pf) 189 { 190 struct xe_device *xe = gt_to_xe(gt); 191 struct xe_tile *tile = gt_to_tile(gt); 192 struct xe_vm *vm; 193 struct xe_vma *vma = NULL; 194 int err; 195 196 /* SW isn't expected to handle TRTT faults */ 197 if (pf->trva_fault) 198 return -EFAULT; 199 200 /* ASID to VM */ 201 mutex_lock(&xe->usm.lock); 202 vm = xa_load(&xe->usm.asid_to_vm, pf->asid); 203 if (vm && xe_vm_in_fault_mode(vm)) 204 xe_vm_get(vm); 205 else 206 vm = NULL; 207 mutex_unlock(&xe->usm.lock); 208 if (!vm) 209 return -EINVAL; 210 211 /* 212 * TODO: Change to read lock? Using write lock for simplicity. 213 */ 214 down_write(&vm->lock); 215 vma = lookup_vma(vm, pf->page_addr); 216 if (!vma) { 217 err = -EINVAL; 218 goto unlock_vm; 219 } 220 221 err = handle_vma_pagefault(tile, pf, vma); 222 223 unlock_vm: 224 if (!err) 225 vm->usm.last_fault_vma = vma; 226 up_write(&vm->lock); 227 xe_vm_put(vm); 228 229 return err; 230 } 231 232 static int send_pagefault_reply(struct xe_guc *guc, 233 struct xe_guc_pagefault_reply *reply) 234 { 235 u32 action[] = { 236 XE_GUC_ACTION_PAGE_FAULT_RES_DESC, 237 reply->dw0, 238 reply->dw1, 239 }; 240 241 return xe_guc_ct_send(&guc->ct, action, ARRAY_SIZE(action), 0, 0); 242 } 243 244 static void print_pagefault(struct xe_device *xe, struct pagefault *pf) 245 { 246 drm_dbg(&xe->drm, "\n\tASID: %d\n" 247 "\tVFID: %d\n" 248 "\tPDATA: 0x%04x\n" 249 "\tFaulted Address: 0x%08x%08x\n" 250 "\tFaultType: %d\n" 251 "\tAccessType: %d\n" 252 "\tFaultLevel: %d\n" 253 "\tEngineClass: %d\n" 254 "\tEngineInstance: %d\n", 255 pf->asid, pf->vfid, pf->pdata, upper_32_bits(pf->page_addr), 256 lower_32_bits(pf->page_addr), 257 pf->fault_type, pf->access_type, pf->fault_level, 258 pf->engine_class, pf->engine_instance); 259 } 260 261 #define PF_MSG_LEN_DW 4 262 263 static bool get_pagefault(struct pf_queue *pf_queue, struct pagefault *pf) 264 { 265 const struct xe_guc_pagefault_desc *desc; 266 bool ret = false; 267 268 spin_lock_irq(&pf_queue->lock); 269 if (pf_queue->tail != pf_queue->head) { 270 desc = (const struct xe_guc_pagefault_desc *) 271 (pf_queue->data + pf_queue->tail); 272 273 pf->fault_level = FIELD_GET(PFD_FAULT_LEVEL, desc->dw0); 274 pf->trva_fault = FIELD_GET(XE2_PFD_TRVA_FAULT, desc->dw0); 275 pf->engine_class = FIELD_GET(PFD_ENG_CLASS, desc->dw0); 276 pf->engine_instance = FIELD_GET(PFD_ENG_INSTANCE, desc->dw0); 277 pf->pdata = FIELD_GET(PFD_PDATA_HI, desc->dw1) << 278 PFD_PDATA_HI_SHIFT; 279 pf->pdata |= FIELD_GET(PFD_PDATA_LO, desc->dw0); 280 pf->asid = FIELD_GET(PFD_ASID, desc->dw1); 281 pf->vfid = FIELD_GET(PFD_VFID, desc->dw2); 282 pf->access_type = FIELD_GET(PFD_ACCESS_TYPE, desc->dw2); 283 pf->fault_type = FIELD_GET(PFD_FAULT_TYPE, desc->dw2); 284 pf->page_addr = (u64)(FIELD_GET(PFD_VIRTUAL_ADDR_HI, desc->dw3)) << 285 PFD_VIRTUAL_ADDR_HI_SHIFT; 286 pf->page_addr |= FIELD_GET(PFD_VIRTUAL_ADDR_LO, desc->dw2) << 287 PFD_VIRTUAL_ADDR_LO_SHIFT; 288 289 pf_queue->tail = (pf_queue->tail + PF_MSG_LEN_DW) % 290 PF_QUEUE_NUM_DW; 291 ret = true; 292 } 293 spin_unlock_irq(&pf_queue->lock); 294 295 return ret; 296 } 297 298 static bool pf_queue_full(struct pf_queue *pf_queue) 299 { 300 lockdep_assert_held(&pf_queue->lock); 301 302 return CIRC_SPACE(pf_queue->head, pf_queue->tail, PF_QUEUE_NUM_DW) <= 303 PF_MSG_LEN_DW; 304 } 305 306 int xe_guc_pagefault_handler(struct xe_guc *guc, u32 *msg, u32 len) 307 { 308 struct xe_gt *gt = guc_to_gt(guc); 309 struct xe_device *xe = gt_to_xe(gt); 310 struct pf_queue *pf_queue; 311 unsigned long flags; 312 u32 asid; 313 bool full; 314 315 /* 316 * The below logic doesn't work unless PF_QUEUE_NUM_DW % PF_MSG_LEN_DW == 0 317 */ 318 BUILD_BUG_ON(PF_QUEUE_NUM_DW % PF_MSG_LEN_DW); 319 320 if (unlikely(len != PF_MSG_LEN_DW)) 321 return -EPROTO; 322 323 asid = FIELD_GET(PFD_ASID, msg[1]); 324 pf_queue = gt->usm.pf_queue + (asid % NUM_PF_QUEUE); 325 326 spin_lock_irqsave(&pf_queue->lock, flags); 327 full = pf_queue_full(pf_queue); 328 if (!full) { 329 memcpy(pf_queue->data + pf_queue->head, msg, len * sizeof(u32)); 330 pf_queue->head = (pf_queue->head + len) % PF_QUEUE_NUM_DW; 331 queue_work(gt->usm.pf_wq, &pf_queue->worker); 332 } else { 333 drm_warn(&xe->drm, "PF Queue full, shouldn't be possible"); 334 } 335 spin_unlock_irqrestore(&pf_queue->lock, flags); 336 337 return full ? -ENOSPC : 0; 338 } 339 340 #define USM_QUEUE_MAX_RUNTIME_MS 20 341 342 static void pf_queue_work_func(struct work_struct *w) 343 { 344 struct pf_queue *pf_queue = container_of(w, struct pf_queue, worker); 345 struct xe_gt *gt = pf_queue->gt; 346 struct xe_device *xe = gt_to_xe(gt); 347 struct xe_guc_pagefault_reply reply = {}; 348 struct pagefault pf = {}; 349 unsigned long threshold; 350 int ret; 351 352 threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS); 353 354 while (get_pagefault(pf_queue, &pf)) { 355 ret = handle_pagefault(gt, &pf); 356 if (unlikely(ret)) { 357 print_pagefault(xe, &pf); 358 pf.fault_unsuccessful = 1; 359 drm_dbg(&xe->drm, "Fault response: Unsuccessful %d\n", ret); 360 } 361 362 reply.dw0 = FIELD_PREP(PFR_VALID, 1) | 363 FIELD_PREP(PFR_SUCCESS, pf.fault_unsuccessful) | 364 FIELD_PREP(PFR_REPLY, PFR_ACCESS) | 365 FIELD_PREP(PFR_DESC_TYPE, FAULT_RESPONSE_DESC) | 366 FIELD_PREP(PFR_ASID, pf.asid); 367 368 reply.dw1 = FIELD_PREP(PFR_VFID, pf.vfid) | 369 FIELD_PREP(PFR_ENG_INSTANCE, pf.engine_instance) | 370 FIELD_PREP(PFR_ENG_CLASS, pf.engine_class) | 371 FIELD_PREP(PFR_PDATA, pf.pdata); 372 373 send_pagefault_reply(>->uc.guc, &reply); 374 375 if (time_after(jiffies, threshold) && 376 pf_queue->tail != pf_queue->head) { 377 queue_work(gt->usm.pf_wq, w); 378 break; 379 } 380 } 381 } 382 383 static void acc_queue_work_func(struct work_struct *w); 384 385 static void pagefault_fini(void *arg) 386 { 387 struct xe_gt *gt = arg; 388 struct xe_device *xe = gt_to_xe(gt); 389 390 if (!xe->info.has_usm) 391 return; 392 393 destroy_workqueue(gt->usm.acc_wq); 394 destroy_workqueue(gt->usm.pf_wq); 395 } 396 397 int xe_gt_pagefault_init(struct xe_gt *gt) 398 { 399 struct xe_device *xe = gt_to_xe(gt); 400 int i; 401 402 if (!xe->info.has_usm) 403 return 0; 404 405 for (i = 0; i < NUM_PF_QUEUE; ++i) { 406 gt->usm.pf_queue[i].gt = gt; 407 spin_lock_init(>->usm.pf_queue[i].lock); 408 INIT_WORK(>->usm.pf_queue[i].worker, pf_queue_work_func); 409 } 410 for (i = 0; i < NUM_ACC_QUEUE; ++i) { 411 gt->usm.acc_queue[i].gt = gt; 412 spin_lock_init(>->usm.acc_queue[i].lock); 413 INIT_WORK(>->usm.acc_queue[i].worker, acc_queue_work_func); 414 } 415 416 gt->usm.pf_wq = alloc_workqueue("xe_gt_page_fault_work_queue", 417 WQ_UNBOUND | WQ_HIGHPRI, NUM_PF_QUEUE); 418 if (!gt->usm.pf_wq) 419 return -ENOMEM; 420 421 gt->usm.acc_wq = alloc_workqueue("xe_gt_access_counter_work_queue", 422 WQ_UNBOUND | WQ_HIGHPRI, 423 NUM_ACC_QUEUE); 424 if (!gt->usm.acc_wq) { 425 destroy_workqueue(gt->usm.pf_wq); 426 return -ENOMEM; 427 } 428 429 return devm_add_action_or_reset(xe->drm.dev, pagefault_fini, gt); 430 } 431 432 void xe_gt_pagefault_reset(struct xe_gt *gt) 433 { 434 struct xe_device *xe = gt_to_xe(gt); 435 int i; 436 437 if (!xe->info.has_usm) 438 return; 439 440 for (i = 0; i < NUM_PF_QUEUE; ++i) { 441 spin_lock_irq(>->usm.pf_queue[i].lock); 442 gt->usm.pf_queue[i].head = 0; 443 gt->usm.pf_queue[i].tail = 0; 444 spin_unlock_irq(>->usm.pf_queue[i].lock); 445 } 446 447 for (i = 0; i < NUM_ACC_QUEUE; ++i) { 448 spin_lock(>->usm.acc_queue[i].lock); 449 gt->usm.acc_queue[i].head = 0; 450 gt->usm.acc_queue[i].tail = 0; 451 spin_unlock(>->usm.acc_queue[i].lock); 452 } 453 } 454 455 static int granularity_in_byte(int val) 456 { 457 switch (val) { 458 case 0: 459 return SZ_128K; 460 case 1: 461 return SZ_2M; 462 case 2: 463 return SZ_16M; 464 case 3: 465 return SZ_64M; 466 default: 467 return 0; 468 } 469 } 470 471 static int sub_granularity_in_byte(int val) 472 { 473 return (granularity_in_byte(val) / 32); 474 } 475 476 static void print_acc(struct xe_device *xe, struct acc *acc) 477 { 478 drm_warn(&xe->drm, "Access counter request:\n" 479 "\tType: %s\n" 480 "\tASID: %d\n" 481 "\tVFID: %d\n" 482 "\tEngine: %d:%d\n" 483 "\tGranularity: 0x%x KB Region/ %d KB sub-granularity\n" 484 "\tSub_Granularity Vector: 0x%08x\n" 485 "\tVA Range base: 0x%016llx\n", 486 acc->access_type ? "AC_NTFY_VAL" : "AC_TRIG_VAL", 487 acc->asid, acc->vfid, acc->engine_class, acc->engine_instance, 488 granularity_in_byte(acc->granularity) / SZ_1K, 489 sub_granularity_in_byte(acc->granularity) / SZ_1K, 490 acc->sub_granularity, acc->va_range_base); 491 } 492 493 static struct xe_vma *get_acc_vma(struct xe_vm *vm, struct acc *acc) 494 { 495 u64 page_va = acc->va_range_base + (ffs(acc->sub_granularity) - 1) * 496 sub_granularity_in_byte(acc->granularity); 497 498 return xe_vm_find_overlapping_vma(vm, page_va, SZ_4K); 499 } 500 501 static int handle_acc(struct xe_gt *gt, struct acc *acc) 502 { 503 struct xe_device *xe = gt_to_xe(gt); 504 struct xe_tile *tile = gt_to_tile(gt); 505 struct drm_exec exec; 506 struct xe_vm *vm; 507 struct xe_vma *vma; 508 int ret = 0; 509 510 /* We only support ACC_TRIGGER at the moment */ 511 if (acc->access_type != ACC_TRIGGER) 512 return -EINVAL; 513 514 /* ASID to VM */ 515 mutex_lock(&xe->usm.lock); 516 vm = xa_load(&xe->usm.asid_to_vm, acc->asid); 517 if (vm) 518 xe_vm_get(vm); 519 mutex_unlock(&xe->usm.lock); 520 if (!vm || !xe_vm_in_fault_mode(vm)) 521 return -EINVAL; 522 523 down_read(&vm->lock); 524 525 /* Lookup VMA */ 526 vma = get_acc_vma(vm, acc); 527 if (!vma) { 528 ret = -EINVAL; 529 goto unlock_vm; 530 } 531 532 trace_xe_vma_acc(vma); 533 534 /* Userptr or null can't be migrated, nothing to do */ 535 if (xe_vma_has_no_bo(vma)) 536 goto unlock_vm; 537 538 /* Lock VM and BOs dma-resv */ 539 drm_exec_init(&exec, 0, 0); 540 drm_exec_until_all_locked(&exec) { 541 ret = xe_pf_begin(&exec, vma, true, tile->id); 542 drm_exec_retry_on_contention(&exec); 543 if (ret) 544 break; 545 } 546 547 drm_exec_fini(&exec); 548 unlock_vm: 549 up_read(&vm->lock); 550 xe_vm_put(vm); 551 552 return ret; 553 } 554 555 #define make_u64(hi__, low__) ((u64)(hi__) << 32 | (u64)(low__)) 556 557 #define ACC_MSG_LEN_DW 4 558 559 static bool get_acc(struct acc_queue *acc_queue, struct acc *acc) 560 { 561 const struct xe_guc_acc_desc *desc; 562 bool ret = false; 563 564 spin_lock(&acc_queue->lock); 565 if (acc_queue->tail != acc_queue->head) { 566 desc = (const struct xe_guc_acc_desc *) 567 (acc_queue->data + acc_queue->tail); 568 569 acc->granularity = FIELD_GET(ACC_GRANULARITY, desc->dw2); 570 acc->sub_granularity = FIELD_GET(ACC_SUBG_HI, desc->dw1) << 31 | 571 FIELD_GET(ACC_SUBG_LO, desc->dw0); 572 acc->engine_class = FIELD_GET(ACC_ENG_CLASS, desc->dw1); 573 acc->engine_instance = FIELD_GET(ACC_ENG_INSTANCE, desc->dw1); 574 acc->asid = FIELD_GET(ACC_ASID, desc->dw1); 575 acc->vfid = FIELD_GET(ACC_VFID, desc->dw2); 576 acc->access_type = FIELD_GET(ACC_TYPE, desc->dw0); 577 acc->va_range_base = make_u64(desc->dw3 & ACC_VIRTUAL_ADDR_RANGE_HI, 578 desc->dw2 & ACC_VIRTUAL_ADDR_RANGE_LO); 579 580 acc_queue->tail = (acc_queue->tail + ACC_MSG_LEN_DW) % 581 ACC_QUEUE_NUM_DW; 582 ret = true; 583 } 584 spin_unlock(&acc_queue->lock); 585 586 return ret; 587 } 588 589 static void acc_queue_work_func(struct work_struct *w) 590 { 591 struct acc_queue *acc_queue = container_of(w, struct acc_queue, worker); 592 struct xe_gt *gt = acc_queue->gt; 593 struct xe_device *xe = gt_to_xe(gt); 594 struct acc acc = {}; 595 unsigned long threshold; 596 int ret; 597 598 threshold = jiffies + msecs_to_jiffies(USM_QUEUE_MAX_RUNTIME_MS); 599 600 while (get_acc(acc_queue, &acc)) { 601 ret = handle_acc(gt, &acc); 602 if (unlikely(ret)) { 603 print_acc(xe, &acc); 604 drm_warn(&xe->drm, "ACC: Unsuccessful %d\n", ret); 605 } 606 607 if (time_after(jiffies, threshold) && 608 acc_queue->tail != acc_queue->head) { 609 queue_work(gt->usm.acc_wq, w); 610 break; 611 } 612 } 613 } 614 615 static bool acc_queue_full(struct acc_queue *acc_queue) 616 { 617 lockdep_assert_held(&acc_queue->lock); 618 619 return CIRC_SPACE(acc_queue->head, acc_queue->tail, ACC_QUEUE_NUM_DW) <= 620 ACC_MSG_LEN_DW; 621 } 622 623 int xe_guc_access_counter_notify_handler(struct xe_guc *guc, u32 *msg, u32 len) 624 { 625 struct xe_gt *gt = guc_to_gt(guc); 626 struct acc_queue *acc_queue; 627 u32 asid; 628 bool full; 629 630 /* 631 * The below logic doesn't work unless ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW == 0 632 */ 633 BUILD_BUG_ON(ACC_QUEUE_NUM_DW % ACC_MSG_LEN_DW); 634 635 if (unlikely(len != ACC_MSG_LEN_DW)) 636 return -EPROTO; 637 638 asid = FIELD_GET(ACC_ASID, msg[1]); 639 acc_queue = >->usm.acc_queue[asid % NUM_ACC_QUEUE]; 640 641 spin_lock(&acc_queue->lock); 642 full = acc_queue_full(acc_queue); 643 if (!full) { 644 memcpy(acc_queue->data + acc_queue->head, msg, 645 len * sizeof(u32)); 646 acc_queue->head = (acc_queue->head + len) % ACC_QUEUE_NUM_DW; 647 queue_work(gt->usm.acc_wq, &acc_queue->worker); 648 } else { 649 drm_warn(>_to_xe(gt)->drm, "ACC Queue full, dropping ACC"); 650 } 651 spin_unlock(&acc_queue->lock); 652 653 return full ? -ENOSPC : 0; 654 } 655