1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (C) 2025 Icenowy Zheng <uwu@icenowy.me> 4 * 5 * Based on vs_dc_hw.h, which is: 6 * Copyright (C) 2023 VeriSilicon Holdings Co., Ltd. 7 */ 8 9 #ifndef _VS_CRTC_REGS_H_ 10 #define _VS_CRTC_REGS_H_ 11 12 #include <linux/bits.h> 13 14 #define VSDC_DISP_DITHER_CONFIG(n) (0x1410 + 0x4 * (n)) 15 16 #define VSDC_DISP_DITHER_TABLE_LOW(n) (0x1420 + 0x4 * (n)) 17 #define VSDC_DISP_DITHER_TABLE_LOW_DEFAULT 0x7B48F3C0 18 19 #define VSDC_DISP_DITHER_TABLE_HIGH(n) (0x1428 + 0x4 * (n)) 20 #define VSDC_DISP_DITHER_TABLE_HIGH_DEFAULT 0x596AD1E2 21 22 #define VSDC_DISP_HSIZE(n) (0x1430 + 0x4 * (n)) 23 #define VSDC_DISP_HSIZE_DISP_MASK GENMASK(14, 0) 24 #define VSDC_DISP_HSIZE_DISP(v) ((v) << 0) 25 #define VSDC_DISP_HSIZE_TOTAL_MASK GENMASK(30, 16) 26 #define VSDC_DISP_HSIZE_TOTAL(v) ((v) << 16) 27 28 #define VSDC_DISP_HSYNC(n) (0x1438 + 0x4 * (n)) 29 #define VSDC_DISP_HSYNC_START_MASK GENMASK(14, 0) 30 #define VSDC_DISP_HSYNC_START(v) ((v) << 0) 31 #define VSDC_DISP_HSYNC_END_MASK GENMASK(29, 15) 32 #define VSDC_DISP_HSYNC_END(v) ((v) << 15) 33 #define VSDC_DISP_HSYNC_EN BIT(30) 34 #define VSDC_DISP_HSYNC_POL BIT(31) 35 36 #define VSDC_DISP_VSIZE(n) (0x1440 + 0x4 * (n)) 37 #define VSDC_DISP_VSIZE_DISP_MASK GENMASK(14, 0) 38 #define VSDC_DISP_VSIZE_DISP(v) ((v) << 0) 39 #define VSDC_DISP_VSIZE_TOTAL_MASK GENMASK(30, 16) 40 #define VSDC_DISP_VSIZE_TOTAL(v) ((v) << 16) 41 42 #define VSDC_DISP_VSYNC(n) (0x1448 + 0x4 * (n)) 43 #define VSDC_DISP_VSYNC_START_MASK GENMASK(14, 0) 44 #define VSDC_DISP_VSYNC_START(v) ((v) << 0) 45 #define VSDC_DISP_VSYNC_END_MASK GENMASK(29, 15) 46 #define VSDC_DISP_VSYNC_END(v) ((v) << 15) 47 #define VSDC_DISP_VSYNC_EN BIT(30) 48 #define VSDC_DISP_VSYNC_POL BIT(31) 49 50 #define VSDC_DISP_CURRENT_LOCATION(n) (0x1450 + 0x4 * (n)) 51 52 #define VSDC_DISP_GAMMA_INDEX(n) (0x1458 + 0x4 * (n)) 53 54 #define VSDC_DISP_GAMMA_DATA(n) (0x1460 + 0x4 * (n)) 55 56 #define VSDC_DISP_IRQ_STA 0x147C 57 58 #define VSDC_DISP_IRQ_EN 0x1480 59 60 #endif /* _VS_CRTC_REGS_H_ */ 61