1 // SPDX-License-Identifier: GPL-2.0 2 /* Copyright 2019 Collabora ltd. */ 3 4 #include <linux/clk.h> 5 #include <linux/devfreq.h> 6 #include <linux/devfreq_cooling.h> 7 #include <linux/nvmem-consumer.h> 8 #include <linux/platform_device.h> 9 #include <linux/pm_opp.h> 10 11 #include <drm/drm_print.h> 12 13 #include "panfrost_device.h" 14 #include "panfrost_devfreq.h" 15 16 static void panfrost_devfreq_update_utilization(struct panfrost_devfreq *pfdevfreq) 17 { 18 ktime_t now, last; 19 20 now = ktime_get(); 21 last = pfdevfreq->time_last_update; 22 23 if (pfdevfreq->busy_count > 0) 24 pfdevfreq->busy_time += ktime_sub(now, last); 25 else 26 pfdevfreq->idle_time += ktime_sub(now, last); 27 28 pfdevfreq->time_last_update = now; 29 } 30 31 static int panfrost_devfreq_target(struct device *dev, unsigned long *freq, 32 u32 flags) 33 { 34 struct panfrost_device *pfdev = dev_get_drvdata(dev); 35 struct dev_pm_opp *opp; 36 int err; 37 38 opp = devfreq_recommended_opp(dev, freq, flags); 39 if (IS_ERR(opp)) 40 return PTR_ERR(opp); 41 dev_pm_opp_put(opp); 42 43 err = dev_pm_opp_set_rate(dev, *freq); 44 if (!err) 45 pfdev->pfdevfreq.current_frequency = *freq; 46 47 return err; 48 } 49 50 static void panfrost_devfreq_reset(struct panfrost_devfreq *pfdevfreq) 51 { 52 pfdevfreq->busy_time = 0; 53 pfdevfreq->idle_time = 0; 54 pfdevfreq->time_last_update = ktime_get(); 55 } 56 57 static int panfrost_devfreq_get_dev_status(struct device *dev, 58 struct devfreq_dev_status *status) 59 { 60 struct panfrost_device *pfdev = dev_get_drvdata(dev); 61 struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq; 62 unsigned long irqflags; 63 64 status->current_frequency = clk_get_rate(pfdev->clock); 65 66 spin_lock_irqsave(&pfdevfreq->lock, irqflags); 67 68 panfrost_devfreq_update_utilization(pfdevfreq); 69 70 status->total_time = ktime_to_ns(ktime_add(pfdevfreq->busy_time, 71 pfdevfreq->idle_time)); 72 73 status->busy_time = ktime_to_ns(pfdevfreq->busy_time); 74 75 panfrost_devfreq_reset(pfdevfreq); 76 77 spin_unlock_irqrestore(&pfdevfreq->lock, irqflags); 78 79 dev_dbg(pfdev->base.dev, "busy %lu total %lu %lu %% freq %lu MHz\n", 80 status->busy_time, status->total_time, 81 status->busy_time / (status->total_time / 100), 82 status->current_frequency / 1000 / 1000); 83 84 return 0; 85 } 86 87 static struct devfreq_dev_profile panfrost_devfreq_profile = { 88 .timer = DEVFREQ_TIMER_DELAYED, 89 .polling_ms = 50, /* ~3 frames */ 90 .target = panfrost_devfreq_target, 91 .get_dev_status = panfrost_devfreq_get_dev_status, 92 }; 93 94 static int panfrost_read_speedbin(struct device *dev) 95 { 96 u32 val; 97 int ret; 98 99 ret = nvmem_cell_read_variable_le_u32(dev, "speed-bin", &val); 100 if (ret) { 101 /* 102 * -ENOENT means that this platform doesn't support speedbins 103 * as it didn't declare any speed-bin nvmem: in this case, we 104 * keep going without it; any other error means that we are 105 * supposed to read the bin value, but we failed doing so. 106 */ 107 if (ret != -ENOENT && ret != -EOPNOTSUPP) { 108 DRM_DEV_ERROR(dev, "Cannot read speed-bin (%d).", ret); 109 return ret; 110 } 111 112 return 0; 113 } 114 DRM_DEV_DEBUG(dev, "Using speed-bin = 0x%x\n", val); 115 116 return devm_pm_opp_set_supported_hw(dev, &val, 1); 117 } 118 119 int panfrost_devfreq_init(struct panfrost_device *pfdev) 120 { 121 int ret; 122 struct dev_pm_opp *opp; 123 unsigned long cur_freq; 124 struct device *dev = pfdev->base.dev; 125 struct devfreq *devfreq; 126 struct thermal_cooling_device *cooling; 127 struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq; 128 unsigned long freq = ULONG_MAX; 129 130 if (pfdev->comp->num_supplies > 1) { 131 /* 132 * GPUs with more than 1 supply require platform-specific handling: 133 * continue without devfreq 134 */ 135 DRM_DEV_INFO(dev, "More than 1 supply is not supported yet\n"); 136 return 0; 137 } 138 139 ret = panfrost_read_speedbin(dev); 140 if (ret) 141 return ret; 142 143 ret = devm_pm_opp_set_regulators(dev, pfdev->comp->supply_names); 144 if (ret) { 145 /* Continue if the optional regulator is missing */ 146 if (ret != -ENODEV) { 147 if (ret != -EPROBE_DEFER) 148 DRM_DEV_ERROR(dev, "Couldn't set OPP regulators\n"); 149 return ret; 150 } 151 } 152 153 ret = devm_pm_opp_of_add_table(dev); 154 if (ret) { 155 /* Optional, continue without devfreq */ 156 if (ret == -ENODEV) 157 ret = 0; 158 return ret; 159 } 160 pfdevfreq->opp_of_table_added = true; 161 162 spin_lock_init(&pfdevfreq->lock); 163 164 panfrost_devfreq_reset(pfdevfreq); 165 166 cur_freq = clk_get_rate(pfdev->clock); 167 168 opp = devfreq_recommended_opp(dev, &cur_freq, 0); 169 if (IS_ERR(opp)) 170 return PTR_ERR(opp); 171 172 panfrost_devfreq_profile.initial_freq = cur_freq; 173 174 /* 175 * We could wait until panfrost_devfreq_target() to set this value, but 176 * since the simple_ondemand governor works asynchronously, there's a 177 * chance by the time someone opens the device's fdinfo file, current 178 * frequency hasn't been updated yet, so let's just do an early set. 179 */ 180 pfdevfreq->current_frequency = cur_freq; 181 182 /* 183 * Set the recommend OPP this will enable and configure the regulator 184 * if any and will avoid a switch off by regulator_late_cleanup() 185 */ 186 ret = dev_pm_opp_set_opp(dev, opp); 187 dev_pm_opp_put(opp); 188 if (ret) { 189 DRM_DEV_ERROR(dev, "Couldn't set recommended OPP\n"); 190 return ret; 191 } 192 193 /* Find the fastest defined rate */ 194 opp = dev_pm_opp_find_freq_floor(dev, &freq); 195 if (IS_ERR(opp)) 196 return PTR_ERR(opp); 197 pfdevfreq->fast_rate = freq; 198 199 dev_pm_opp_put(opp); 200 201 /* 202 * Setup default thresholds for the simple_ondemand governor. 203 * The values are chosen based on experiments. 204 */ 205 pfdevfreq->gov_data.upthreshold = 45; 206 pfdevfreq->gov_data.downdifferential = 5; 207 208 devfreq = devm_devfreq_add_device(dev, &panfrost_devfreq_profile, 209 DEVFREQ_GOV_SIMPLE_ONDEMAND, 210 &pfdevfreq->gov_data); 211 if (IS_ERR(devfreq)) { 212 DRM_DEV_ERROR(dev, "Couldn't initialize GPU devfreq\n"); 213 return PTR_ERR(devfreq); 214 } 215 pfdevfreq->devfreq = devfreq; 216 217 cooling = devfreq_cooling_em_register(devfreq, NULL); 218 if (IS_ERR(cooling)) 219 DRM_DEV_INFO(dev, "Failed to register cooling device\n"); 220 else 221 pfdevfreq->cooling = cooling; 222 223 return 0; 224 } 225 226 void panfrost_devfreq_fini(struct panfrost_device *pfdev) 227 { 228 struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq; 229 230 if (pfdevfreq->cooling) { 231 devfreq_cooling_unregister(pfdevfreq->cooling); 232 pfdevfreq->cooling = NULL; 233 } 234 } 235 236 void panfrost_devfreq_resume(struct panfrost_device *pfdev) 237 { 238 struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq; 239 240 if (!pfdevfreq->devfreq) 241 return; 242 243 panfrost_devfreq_reset(pfdevfreq); 244 245 devfreq_resume_device(pfdevfreq->devfreq); 246 } 247 248 void panfrost_devfreq_suspend(struct panfrost_device *pfdev) 249 { 250 struct panfrost_devfreq *pfdevfreq = &pfdev->pfdevfreq; 251 252 if (!pfdevfreq->devfreq) 253 return; 254 255 devfreq_suspend_device(pfdevfreq->devfreq); 256 } 257 258 void panfrost_devfreq_record_busy(struct panfrost_devfreq *pfdevfreq) 259 { 260 unsigned long irqflags; 261 262 if (!pfdevfreq->devfreq) 263 return; 264 265 spin_lock_irqsave(&pfdevfreq->lock, irqflags); 266 267 panfrost_devfreq_update_utilization(pfdevfreq); 268 269 pfdevfreq->busy_count++; 270 271 spin_unlock_irqrestore(&pfdevfreq->lock, irqflags); 272 } 273 274 void panfrost_devfreq_record_idle(struct panfrost_devfreq *pfdevfreq) 275 { 276 unsigned long irqflags; 277 278 if (!pfdevfreq->devfreq) 279 return; 280 281 spin_lock_irqsave(&pfdevfreq->lock, irqflags); 282 283 panfrost_devfreq_update_utilization(pfdevfreq); 284 285 WARN_ON(--pfdevfreq->busy_count < 0); 286 287 spin_unlock_irqrestore(&pfdevfreq->lock, irqflags); 288 } 289