1*284ad706SBen Skeggs /* SPDX-License-Identifier: MIT 2*284ad706SBen Skeggs * 3*284ad706SBen Skeggs * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4*284ad706SBen Skeggs */ 5*284ad706SBen Skeggs #include "priv.h" 6*284ad706SBen Skeggs 7*284ad706SBen Skeggs #include <nvhw/drf.h> 8*284ad706SBen Skeggs #include <nvhw/ref/gb202/dev_therm.h> 9*284ad706SBen Skeggs 10*284ad706SBen Skeggs static int 11*284ad706SBen Skeggs gb202_fsp_wait_secure_boot(struct nvkm_fsp *fsp) 12*284ad706SBen Skeggs { 13*284ad706SBen Skeggs struct nvkm_device *device = fsp->subdev.device; 14*284ad706SBen Skeggs unsigned timeout_ms = 4000; 15*284ad706SBen Skeggs 16*284ad706SBen Skeggs do { 17*284ad706SBen Skeggs u32 status = NVKM_RD32(device, NV_THERM, I2CS_SCRATCH, FSP_BOOT_COMPLETE_STATUS); 18*284ad706SBen Skeggs 19*284ad706SBen Skeggs if (status == NV_THERM_I2CS_SCRATCH_FSP_BOOT_COMPLETE_STATUS_SUCCESS) 20*284ad706SBen Skeggs return 0; 21*284ad706SBen Skeggs 22*284ad706SBen Skeggs usleep_range(1000, 2000); 23*284ad706SBen Skeggs } while (timeout_ms--); 24*284ad706SBen Skeggs 25*284ad706SBen Skeggs return -ETIMEDOUT; 26*284ad706SBen Skeggs } 27*284ad706SBen Skeggs 28*284ad706SBen Skeggs static const struct nvkm_fsp_func 29*284ad706SBen Skeggs gb202_fsp = { 30*284ad706SBen Skeggs .wait_secure_boot = gb202_fsp_wait_secure_boot, 31*284ad706SBen Skeggs .cot = { 32*284ad706SBen Skeggs .version = 2, 33*284ad706SBen Skeggs .size_hash = 48, 34*284ad706SBen Skeggs .size_pkey = 97, 35*284ad706SBen Skeggs .size_sig = 96, 36*284ad706SBen Skeggs .boot_gsp_fmc = gh100_fsp_boot_gsp_fmc, 37*284ad706SBen Skeggs }, 38*284ad706SBen Skeggs }; 39*284ad706SBen Skeggs 40*284ad706SBen Skeggs int 41*284ad706SBen Skeggs gb202_fsp_new(struct nvkm_device *device, 42*284ad706SBen Skeggs enum nvkm_subdev_type type, int inst, struct nvkm_fsp **pfsp) 43*284ad706SBen Skeggs { 44*284ad706SBen Skeggs return nvkm_fsp_new_(&gb202_fsp, device, type, inst, pfsp); 45*284ad706SBen Skeggs } 46