1 /* 2 * Copyright 2012 Red Hat Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: Ben Skeggs 23 */ 24 #include "nv50.h" 25 26 #include <nvif/class.h> 27 28 /******************************************************************************* 29 * EVO master channel object 30 ******************************************************************************/ 31 32 static const struct nv50_disp_mthd_list 33 gk104_disp_core_mthd_head = { 34 .mthd = 0x0300, 35 .addr = 0x000300, 36 .data = { 37 { 0x0400, 0x660400 }, 38 { 0x0404, 0x660404 }, 39 { 0x0408, 0x660408 }, 40 { 0x040c, 0x66040c }, 41 { 0x0410, 0x660410 }, 42 { 0x0414, 0x660414 }, 43 { 0x0418, 0x660418 }, 44 { 0x041c, 0x66041c }, 45 { 0x0420, 0x660420 }, 46 { 0x0424, 0x660424 }, 47 { 0x0428, 0x660428 }, 48 { 0x042c, 0x66042c }, 49 { 0x0430, 0x660430 }, 50 { 0x0434, 0x660434 }, 51 { 0x0438, 0x660438 }, 52 { 0x0440, 0x660440 }, 53 { 0x0444, 0x660444 }, 54 { 0x0448, 0x660448 }, 55 { 0x044c, 0x66044c }, 56 { 0x0450, 0x660450 }, 57 { 0x0454, 0x660454 }, 58 { 0x0458, 0x660458 }, 59 { 0x045c, 0x66045c }, 60 { 0x0460, 0x660460 }, 61 { 0x0468, 0x660468 }, 62 { 0x046c, 0x66046c }, 63 { 0x0470, 0x660470 }, 64 { 0x0474, 0x660474 }, 65 { 0x047c, 0x66047c }, 66 { 0x0480, 0x660480 }, 67 { 0x0484, 0x660484 }, 68 { 0x0488, 0x660488 }, 69 { 0x048c, 0x66048c }, 70 { 0x0490, 0x660490 }, 71 { 0x0494, 0x660494 }, 72 { 0x0498, 0x660498 }, 73 { 0x04a0, 0x6604a0 }, 74 { 0x04b0, 0x6604b0 }, 75 { 0x04b8, 0x6604b8 }, 76 { 0x04bc, 0x6604bc }, 77 { 0x04c0, 0x6604c0 }, 78 { 0x04c4, 0x6604c4 }, 79 { 0x04c8, 0x6604c8 }, 80 { 0x04d0, 0x6604d0 }, 81 { 0x04d4, 0x6604d4 }, 82 { 0x04e0, 0x6604e0 }, 83 { 0x04e4, 0x6604e4 }, 84 { 0x04e8, 0x6604e8 }, 85 { 0x04ec, 0x6604ec }, 86 { 0x04f0, 0x6604f0 }, 87 { 0x04f4, 0x6604f4 }, 88 { 0x04f8, 0x6604f8 }, 89 { 0x04fc, 0x6604fc }, 90 { 0x0500, 0x660500 }, 91 { 0x0504, 0x660504 }, 92 { 0x0508, 0x660508 }, 93 { 0x050c, 0x66050c }, 94 { 0x0510, 0x660510 }, 95 { 0x0514, 0x660514 }, 96 { 0x0518, 0x660518 }, 97 { 0x051c, 0x66051c }, 98 { 0x0520, 0x660520 }, 99 { 0x0524, 0x660524 }, 100 { 0x052c, 0x66052c }, 101 { 0x0530, 0x660530 }, 102 { 0x054c, 0x66054c }, 103 { 0x0550, 0x660550 }, 104 { 0x0554, 0x660554 }, 105 { 0x0558, 0x660558 }, 106 { 0x055c, 0x66055c }, 107 {} 108 } 109 }; 110 111 const struct nv50_disp_mthd_chan 112 gk104_disp_core_mthd_chan = { 113 .name = "Core", 114 .addr = 0x000000, 115 .data = { 116 { "Global", 1, &gf110_disp_core_mthd_base }, 117 { "DAC", 3, &gf110_disp_core_mthd_dac }, 118 { "SOR", 8, &gf110_disp_core_mthd_sor }, 119 { "PIOR", 4, &gf110_disp_core_mthd_pior }, 120 { "HEAD", 4, &gk104_disp_core_mthd_head }, 121 {} 122 } 123 }; 124 125 /******************************************************************************* 126 * EVO overlay channel objects 127 ******************************************************************************/ 128 129 static const struct nv50_disp_mthd_list 130 gk104_disp_ovly_mthd_base = { 131 .mthd = 0x0000, 132 .data = { 133 { 0x0080, 0x665080 }, 134 { 0x0084, 0x665084 }, 135 { 0x0088, 0x665088 }, 136 { 0x008c, 0x66508c }, 137 { 0x0090, 0x665090 }, 138 { 0x0094, 0x665094 }, 139 { 0x00a0, 0x6650a0 }, 140 { 0x00a4, 0x6650a4 }, 141 { 0x00b0, 0x6650b0 }, 142 { 0x00b4, 0x6650b4 }, 143 { 0x00b8, 0x6650b8 }, 144 { 0x00c0, 0x6650c0 }, 145 { 0x00c4, 0x6650c4 }, 146 { 0x00e0, 0x6650e0 }, 147 { 0x00e4, 0x6650e4 }, 148 { 0x00e8, 0x6650e8 }, 149 { 0x0100, 0x665100 }, 150 { 0x0104, 0x665104 }, 151 { 0x0108, 0x665108 }, 152 { 0x010c, 0x66510c }, 153 { 0x0110, 0x665110 }, 154 { 0x0118, 0x665118 }, 155 { 0x011c, 0x66511c }, 156 { 0x0120, 0x665120 }, 157 { 0x0124, 0x665124 }, 158 { 0x0130, 0x665130 }, 159 { 0x0134, 0x665134 }, 160 { 0x0138, 0x665138 }, 161 { 0x013c, 0x66513c }, 162 { 0x0140, 0x665140 }, 163 { 0x0144, 0x665144 }, 164 { 0x0148, 0x665148 }, 165 { 0x014c, 0x66514c }, 166 { 0x0150, 0x665150 }, 167 { 0x0154, 0x665154 }, 168 { 0x0158, 0x665158 }, 169 { 0x015c, 0x66515c }, 170 { 0x0160, 0x665160 }, 171 { 0x0164, 0x665164 }, 172 { 0x0168, 0x665168 }, 173 { 0x016c, 0x66516c }, 174 { 0x0400, 0x665400 }, 175 { 0x0404, 0x665404 }, 176 { 0x0408, 0x665408 }, 177 { 0x040c, 0x66540c }, 178 { 0x0410, 0x665410 }, 179 {} 180 } 181 }; 182 183 const struct nv50_disp_mthd_chan 184 gk104_disp_ovly_mthd_chan = { 185 .name = "Overlay", 186 .addr = 0x001000, 187 .data = { 188 { "Global", 1, &gk104_disp_ovly_mthd_base }, 189 {} 190 } 191 }; 192 193 /******************************************************************************* 194 * Base display object 195 ******************************************************************************/ 196 197 static struct nvkm_oclass 198 gk104_disp_sclass[] = { 199 { GK104_DISP_CORE_CHANNEL_DMA, &gf110_disp_core_ofuncs.base }, 200 { GK104_DISP_BASE_CHANNEL_DMA, &gf110_disp_base_ofuncs.base }, 201 { GK104_DISP_OVERLAY_CONTROL_DMA, &gf110_disp_ovly_ofuncs.base }, 202 { GK104_DISP_OVERLAY, &gf110_disp_oimm_ofuncs.base }, 203 { GK104_DISP_CURSOR, &gf110_disp_curs_ofuncs.base }, 204 {} 205 }; 206 207 static struct nvkm_oclass 208 gk104_disp_main_oclass[] = { 209 { GK104_DISP, &gf110_disp_main_ofuncs }, 210 {} 211 }; 212 213 /******************************************************************************* 214 * Display engine implementation 215 ******************************************************************************/ 216 217 static int 218 gk104_disp_ctor(struct nvkm_object *parent, struct nvkm_object *engine, 219 struct nvkm_oclass *oclass, void *data, u32 size, 220 struct nvkm_object **pobject) 221 { 222 struct nv50_disp_priv *priv; 223 int heads = nv_rd32(parent, 0x022448); 224 int ret; 225 226 ret = nvkm_disp_create(parent, engine, oclass, heads, 227 "PDISP", "display", &priv); 228 *pobject = nv_object(priv); 229 if (ret) 230 return ret; 231 232 ret = nvkm_event_init(&gf110_disp_chan_uevent, 1, 17, &priv->uevent); 233 if (ret) 234 return ret; 235 236 nv_engine(priv)->sclass = gk104_disp_main_oclass; 237 nv_engine(priv)->cclass = &nv50_disp_cclass; 238 nv_subdev(priv)->intr = gf110_disp_intr; 239 INIT_WORK(&priv->supervisor, gf110_disp_intr_supervisor); 240 priv->sclass = gk104_disp_sclass; 241 priv->head.nr = heads; 242 priv->dac.nr = 3; 243 priv->sor.nr = 4; 244 priv->dac.power = nv50_dac_power; 245 priv->dac.sense = nv50_dac_sense; 246 priv->sor.power = nv50_sor_power; 247 priv->sor.hda_eld = gf110_hda_eld; 248 priv->sor.hdmi = gk104_hdmi_ctrl; 249 return 0; 250 } 251 252 struct nvkm_oclass * 253 gk104_disp_oclass = &(struct nv50_disp_impl) { 254 .base.base.handle = NV_ENGINE(DISP, 0x91), 255 .base.base.ofuncs = &(struct nvkm_ofuncs) { 256 .ctor = gk104_disp_ctor, 257 .dtor = _nvkm_disp_dtor, 258 .init = _nvkm_disp_init, 259 .fini = _nvkm_disp_fini, 260 }, 261 .base.vblank = &gf110_disp_vblank_func, 262 .base.outp = gf110_disp_outp_sclass, 263 .mthd.core = &gk104_disp_core_mthd_chan, 264 .mthd.base = &gf110_disp_base_mthd_chan, 265 .mthd.ovly = &gk104_disp_ovly_mthd_chan, 266 .mthd.prev = -0x020000, 267 .head.scanoutpos = gf110_disp_main_scanoutpos, 268 }.base.base; 269