1 /*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24 #include "priv.h"
25 #include "chan.h"
26 #include "hdmi.h"
27 #include "head.h"
28 #include "ior.h"
29
30 #include <nvif/class.h>
31
32 void
gk104_sor_hdmi_infoframe_vsi(struct nvkm_ior * ior,int head,void * data,u32 size)33 gk104_sor_hdmi_infoframe_vsi(struct nvkm_ior *ior, int head, void *data, u32 size)
34 {
35 struct nvkm_device *device = ior->disp->engine.subdev.device;
36 struct packed_hdmi_infoframe vsi;
37 const u32 hoff = head * 0x400;
38
39 pack_hdmi_infoframe(&vsi, data, size);
40
41 /* GENERIC(?) / Vendor InfoFrame? */
42 nvkm_mask(device, 0x690100 + hoff, 0x00010001, 0x00000000);
43 if (!size)
44 return;
45
46 nvkm_wr32(device, 0x690108 + hoff, vsi.header);
47 nvkm_wr32(device, 0x69010c + hoff, vsi.subpack0_low);
48 nvkm_wr32(device, 0x690110 + hoff, vsi.subpack0_high);
49 /* Is there a second (or further?) set of subpack registers here? */
50 nvkm_mask(device, 0x690100 + hoff, 0x00000001, 0x00000001);
51 }
52
53 void
gk104_sor_hdmi_infoframe_avi(struct nvkm_ior * ior,int head,void * data,u32 size)54 gk104_sor_hdmi_infoframe_avi(struct nvkm_ior *ior, int head, void *data, u32 size)
55 {
56 struct nvkm_device *device = ior->disp->engine.subdev.device;
57 struct packed_hdmi_infoframe avi;
58 const u32 hoff = head * 0x400;
59
60 pack_hdmi_infoframe(&avi, data, size);
61
62 /* AVI InfoFrame */
63 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000000);
64 if (!size)
65 return;
66
67 nvkm_wr32(device, 0x690008 + hoff, avi.header);
68 nvkm_wr32(device, 0x69000c + hoff, avi.subpack0_low);
69 nvkm_wr32(device, 0x690010 + hoff, avi.subpack0_high);
70 nvkm_wr32(device, 0x690014 + hoff, avi.subpack1_low);
71 nvkm_wr32(device, 0x690018 + hoff, avi.subpack1_high);
72
73 nvkm_mask(device, 0x690000 + hoff, 0x00000001, 0x00000001);
74 }
75
76 void
gk104_sor_hdmi_ctrl(struct nvkm_ior * ior,int head,bool enable,u8 max_ac_packet,u8 rekey)77 gk104_sor_hdmi_ctrl(struct nvkm_ior *ior, int head, bool enable, u8 max_ac_packet, u8 rekey)
78 {
79 struct nvkm_device *device = ior->disp->engine.subdev.device;
80 const u32 ctrl = 0x40000000 * enable |
81 max_ac_packet << 16 |
82 rekey;
83 const u32 hoff = head * 0x800;
84 const u32 hdmi = head * 0x400;
85
86 if (!(ctrl & 0x40000000)) {
87 nvkm_mask(device, 0x616798 + hoff, 0x40000000, 0x00000000);
88 nvkm_mask(device, 0x690100 + hdmi, 0x00000001, 0x00000000);
89 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
90 nvkm_mask(device, 0x690000 + hdmi, 0x00000001, 0x00000000);
91 return;
92 }
93
94 /* ??? InfoFrame? */
95 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000000);
96 nvkm_wr32(device, 0x6900cc + hdmi, 0x00000010);
97 nvkm_mask(device, 0x6900c0 + hdmi, 0x00000001, 0x00000001);
98
99 /* ??? */
100 nvkm_wr32(device, 0x690080 + hdmi, 0x82000000);
101
102 /* HDMI_CTRL */
103 nvkm_mask(device, 0x616798 + hoff, 0x401f007f, ctrl);
104 }
105
106 const struct nvkm_ior_func_hdmi
107 gk104_sor_hdmi = {
108 .ctrl = gk104_sor_hdmi_ctrl,
109 .infoframe_avi = gk104_sor_hdmi_infoframe_avi,
110 .infoframe_vsi = gk104_sor_hdmi_infoframe_vsi,
111 };
112
113 static const struct nvkm_ior_func
114 gk104_sor = {
115 .state = gf119_sor_state,
116 .power = nv50_sor_power,
117 .clock = gf119_sor_clock,
118 .bl = >215_sor_bl,
119 .hdmi = &gk104_sor_hdmi,
120 .dp = &gf119_sor_dp,
121 .hda = &gf119_sor_hda,
122 };
123
124 int
gk104_sor_new(struct nvkm_disp * disp,int id)125 gk104_sor_new(struct nvkm_disp *disp, int id)
126 {
127 return nvkm_ior_new_(&gk104_sor, disp, SOR, id, true);
128 }
129
130 static const struct nvkm_disp_mthd_list
131 gk104_disp_ovly_mthd_base = {
132 .mthd = 0x0000,
133 .data = {
134 { 0x0080, 0x665080 },
135 { 0x0084, 0x665084 },
136 { 0x0088, 0x665088 },
137 { 0x008c, 0x66508c },
138 { 0x0090, 0x665090 },
139 { 0x0094, 0x665094 },
140 { 0x00a0, 0x6650a0 },
141 { 0x00a4, 0x6650a4 },
142 { 0x00b0, 0x6650b0 },
143 { 0x00b4, 0x6650b4 },
144 { 0x00b8, 0x6650b8 },
145 { 0x00c0, 0x6650c0 },
146 { 0x00c4, 0x6650c4 },
147 { 0x00e0, 0x6650e0 },
148 { 0x00e4, 0x6650e4 },
149 { 0x00e8, 0x6650e8 },
150 { 0x0100, 0x665100 },
151 { 0x0104, 0x665104 },
152 { 0x0108, 0x665108 },
153 { 0x010c, 0x66510c },
154 { 0x0110, 0x665110 },
155 { 0x0118, 0x665118 },
156 { 0x011c, 0x66511c },
157 { 0x0120, 0x665120 },
158 { 0x0124, 0x665124 },
159 { 0x0130, 0x665130 },
160 { 0x0134, 0x665134 },
161 { 0x0138, 0x665138 },
162 { 0x013c, 0x66513c },
163 { 0x0140, 0x665140 },
164 { 0x0144, 0x665144 },
165 { 0x0148, 0x665148 },
166 { 0x014c, 0x66514c },
167 { 0x0150, 0x665150 },
168 { 0x0154, 0x665154 },
169 { 0x0158, 0x665158 },
170 { 0x015c, 0x66515c },
171 { 0x0160, 0x665160 },
172 { 0x0164, 0x665164 },
173 { 0x0168, 0x665168 },
174 { 0x016c, 0x66516c },
175 { 0x0400, 0x665400 },
176 { 0x0404, 0x665404 },
177 { 0x0408, 0x665408 },
178 { 0x040c, 0x66540c },
179 { 0x0410, 0x665410 },
180 {}
181 }
182 };
183
184 const struct nvkm_disp_chan_mthd
185 gk104_disp_ovly_mthd = {
186 .name = "Overlay",
187 .addr = 0x001000,
188 .prev = -0x020000,
189 .data = {
190 { "Global", 1, &gk104_disp_ovly_mthd_base },
191 {}
192 }
193 };
194
195 const struct nvkm_disp_chan_user
196 gk104_disp_ovly = {
197 .func = &gf119_disp_dmac_func,
198 .ctrl = 5,
199 .user = 5,
200 .mthd = &gk104_disp_ovly_mthd,
201 };
202
203 static const struct nvkm_disp_mthd_list
204 gk104_disp_core_mthd_head = {
205 .mthd = 0x0300,
206 .addr = 0x000300,
207 .data = {
208 { 0x0400, 0x660400 },
209 { 0x0404, 0x660404 },
210 { 0x0408, 0x660408 },
211 { 0x040c, 0x66040c },
212 { 0x0410, 0x660410 },
213 { 0x0414, 0x660414 },
214 { 0x0418, 0x660418 },
215 { 0x041c, 0x66041c },
216 { 0x0420, 0x660420 },
217 { 0x0424, 0x660424 },
218 { 0x0428, 0x660428 },
219 { 0x042c, 0x66042c },
220 { 0x0430, 0x660430 },
221 { 0x0434, 0x660434 },
222 { 0x0438, 0x660438 },
223 { 0x0440, 0x660440 },
224 { 0x0444, 0x660444 },
225 { 0x0448, 0x660448 },
226 { 0x044c, 0x66044c },
227 { 0x0450, 0x660450 },
228 { 0x0454, 0x660454 },
229 { 0x0458, 0x660458 },
230 { 0x045c, 0x66045c },
231 { 0x0460, 0x660460 },
232 { 0x0468, 0x660468 },
233 { 0x046c, 0x66046c },
234 { 0x0470, 0x660470 },
235 { 0x0474, 0x660474 },
236 { 0x047c, 0x66047c },
237 { 0x0480, 0x660480 },
238 { 0x0484, 0x660484 },
239 { 0x0488, 0x660488 },
240 { 0x048c, 0x66048c },
241 { 0x0490, 0x660490 },
242 { 0x0494, 0x660494 },
243 { 0x0498, 0x660498 },
244 { 0x04a0, 0x6604a0 },
245 { 0x04b0, 0x6604b0 },
246 { 0x04b8, 0x6604b8 },
247 { 0x04bc, 0x6604bc },
248 { 0x04c0, 0x6604c0 },
249 { 0x04c4, 0x6604c4 },
250 { 0x04c8, 0x6604c8 },
251 { 0x04d0, 0x6604d0 },
252 { 0x04d4, 0x6604d4 },
253 { 0x04e0, 0x6604e0 },
254 { 0x04e4, 0x6604e4 },
255 { 0x04e8, 0x6604e8 },
256 { 0x04ec, 0x6604ec },
257 { 0x04f0, 0x6604f0 },
258 { 0x04f4, 0x6604f4 },
259 { 0x04f8, 0x6604f8 },
260 { 0x04fc, 0x6604fc },
261 { 0x0500, 0x660500 },
262 { 0x0504, 0x660504 },
263 { 0x0508, 0x660508 },
264 { 0x050c, 0x66050c },
265 { 0x0510, 0x660510 },
266 { 0x0514, 0x660514 },
267 { 0x0518, 0x660518 },
268 { 0x051c, 0x66051c },
269 { 0x0520, 0x660520 },
270 { 0x0524, 0x660524 },
271 { 0x052c, 0x66052c },
272 { 0x0530, 0x660530 },
273 { 0x054c, 0x66054c },
274 { 0x0550, 0x660550 },
275 { 0x0554, 0x660554 },
276 { 0x0558, 0x660558 },
277 { 0x055c, 0x66055c },
278 {}
279 }
280 };
281
282 const struct nvkm_disp_chan_mthd
283 gk104_disp_core_mthd = {
284 .name = "Core",
285 .addr = 0x000000,
286 .prev = -0x020000,
287 .data = {
288 { "Global", 1, &gf119_disp_core_mthd_base },
289 { "DAC", 3, &gf119_disp_core_mthd_dac },
290 { "SOR", 8, &gf119_disp_core_mthd_sor },
291 { "PIOR", 4, &gf119_disp_core_mthd_pior },
292 { "HEAD", 4, &gk104_disp_core_mthd_head },
293 {}
294 }
295 };
296
297 const struct nvkm_disp_chan_user
298 gk104_disp_core = {
299 .func = &gf119_disp_core_func,
300 .ctrl = 0,
301 .user = 0,
302 .mthd = &gk104_disp_core_mthd,
303 };
304
305 static const struct nvkm_disp_func
306 gk104_disp = {
307 .oneinit = nv50_disp_oneinit,
308 .init = gf119_disp_init,
309 .fini = gf119_disp_fini,
310 .intr = gf119_disp_intr,
311 .intr_error = gf119_disp_intr_error,
312 .super = gf119_disp_super,
313 .uevent = &gf119_disp_chan_uevent,
314 .head = { .cnt = gf119_head_cnt, .new = gf119_head_new },
315 .dac = { .cnt = gf119_dac_cnt, .new = gf119_dac_new },
316 .sor = { .cnt = gf119_sor_cnt, .new = gk104_sor_new },
317 .root = { 0,0,GK104_DISP },
318 .user = {
319 {{0,0,GK104_DISP_CURSOR }, nvkm_disp_chan_new, &gf119_disp_curs },
320 {{0,0,GK104_DISP_OVERLAY }, nvkm_disp_chan_new, &gf119_disp_oimm },
321 {{0,0,GK104_DISP_BASE_CHANNEL_DMA }, nvkm_disp_chan_new, &gf119_disp_base },
322 {{0,0,GK104_DISP_CORE_CHANNEL_DMA }, nvkm_disp_core_new, &gk104_disp_core },
323 {{0,0,GK104_DISP_OVERLAY_CONTROL_DMA}, nvkm_disp_chan_new, &gk104_disp_ovly },
324 {}
325 },
326 };
327
328 int
gk104_disp_new(struct nvkm_device * device,enum nvkm_subdev_type type,int inst,struct nvkm_disp ** pdisp)329 gk104_disp_new(struct nvkm_device *device, enum nvkm_subdev_type type, int inst,
330 struct nvkm_disp **pdisp)
331 {
332 return nvkm_disp_new_(&gk104_disp, device, type, inst, pdisp);
333 }
334