xref: /linux/drivers/gpu/drm/nouveau/nvif/chan906f.c (revision b08494a8f7416e5f09907318c5460ad6f6e2a548)
1 /* SPDX-License-Identifier: MIT
2  *
3  * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved.
4  */
5 #include <nvif/chan.h>
6 #include <nvif/user.h>
7 #include <nvif/push906f.h>
8 
9 #include <nvhw/class/cl906f.h>
10 
11 /* Limits GPFIFO size to 1MiB, and "main" push buffer size to 64KiB. */
12 #define NVIF_CHAN906F_PBPTR_BITS  15
13 #define NVIF_CHAN906F_PBPTR_MASK  ((1 << NVIF_CHAN906F_PBPTR_BITS) - 1)
14 
15 #define NVIF_CHAN906F_GPPTR_SHIFT NVIF_CHAN906F_PBPTR_BITS
16 #define NVIF_CHAN906F_GPPTR_BITS  (32 - NVIF_CHAN906F_PBPTR_BITS)
17 #define NVIF_CHAN906F_GPPTR_MASK  ((1 << NVIF_CHAN906F_GPPTR_BITS) - 1)
18 
19 #define NVIF_CHAN906F_SEM_RELEASE_SIZE 5
20 
21 static int
22 nvif_chan906f_sem_release(struct nvif_chan *chan, u64 addr, u32 data)
23 {
24 	struct nvif_push *push = &chan->push;
25 	int ret;
26 
27 	ret = PUSH_WAIT(push, NVIF_CHAN906F_SEM_RELEASE_SIZE);
28 	if (ret)
29 		return ret;
30 
31 	PUSH_MTHD(push, NV906F, SEMAPHOREA,
32 		  NVVAL(NV906F, SEMAPHOREA, OFFSET_UPPER, upper_32_bits(addr)),
33 
34 				SEMAPHOREB, lower_32_bits(addr),
35 
36 				SEMAPHOREC, data,
37 
38 				SEMAPHORED,
39 		  NVDEF(NV906F, SEMAPHORED, OPERATION, RELEASE) |
40 		  NVDEF(NV906F, SEMAPHORED, RELEASE_WFI, DIS) |
41 		  NVDEF(NV906F, SEMAPHORED, RELEASE_SIZE, 16BYTE));
42 
43 	return 0;
44 }
45 
46 int
47 nvif_chan906f_gpfifo_post(struct nvif_chan *chan, u32 gpptr, u32 pbptr)
48 {
49 	return chan->func->sem.release(chan, chan->sema.addr,
50 				       (gpptr << NVIF_CHAN906F_GPPTR_SHIFT) | pbptr);
51 }
52 
53 u32
54 nvif_chan906f_gpfifo_read_get(struct nvif_chan *chan)
55 {
56 	return nvif_rd32(&chan->sema, 0) >> NVIF_CHAN906F_GPPTR_SHIFT;
57 }
58 
59 u32
60 nvif_chan906f_read_get(struct nvif_chan *chan)
61 {
62 	return nvif_rd32(&chan->sema, 0) & NVIF_CHAN906F_PBPTR_MASK;
63 }
64 
65 static const struct nvif_chan_func
66 nvif_chan906f = {
67 	.push.read_get = nvif_chan906f_read_get,
68 	.gpfifo.read_get = nvif_chan906f_gpfifo_read_get,
69 	.gpfifo.push = nvif_chan506f_gpfifo_push,
70 	.gpfifo.kick = nvif_chan506f_gpfifo_kick,
71 	.gpfifo.post = nvif_chan906f_gpfifo_post,
72 	.gpfifo.post_size = NVIF_CHAN906F_SEM_RELEASE_SIZE,
73 	.sem.release = nvif_chan906f_sem_release,
74 };
75 
76 int
77 nvif_chan906f_ctor_(const struct nvif_chan_func *func, void *userd, void *gpfifo, u32 gpfifo_size,
78 		    void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr,
79 		    struct nvif_chan *chan)
80 {
81 	nvif_chan_gpfifo_ctor(func, userd, gpfifo, gpfifo_size, push, push_addr, push_size, chan);
82 	chan->sema.map.ptr = sema;
83 	chan->sema.addr = sema_addr;
84 	return 0;
85 }
86 
87 int
88 nvif_chan906f_ctor(struct nvif_chan *chan, void *userd, void *gpfifo, u32 gpfifo_size,
89 		   void *push, u64 push_addr, u32 push_size, void *sema, u64 sema_addr)
90 {
91 	return nvif_chan906f_ctor_(&nvif_chan906f, userd, gpfifo, gpfifo_size,
92 				   push, push_addr, push_size, sema, sema_addr, chan);
93 }
94