1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #ifndef __gh100_dev_fsp_pri_h__ 6 #define __gh100_dev_fsp_pri_h__ 7 8 #define NV_PFSP 0x8F3FFF:0x8F0000 /* RW--D */ 9 10 #define NV_PFSP_MSGQ_HEAD(i) (0x008F2c80+(i)*8) /* RW-4A */ 11 #define NV_PFSP_MSGQ_HEAD__SIZE_1 8 /* */ 12 #define NV_PFSP_MSGQ_HEAD_VAL 31:0 /* RWIUF */ 13 #define NV_PFSP_MSGQ_HEAD_VAL_INIT 0x00000000 /* RWI-V */ 14 #define NV_PFSP_MSGQ_TAIL(i) (0x008F2c84+(i)*8) /* RW-4A */ 15 #define NV_PFSP_MSGQ_TAIL__SIZE_1 8 /* */ 16 #define NV_PFSP_MSGQ_TAIL_VAL 31:0 /* RWIUF */ 17 #define NV_PFSP_MSGQ_TAIL_VAL_INIT 0x00000000 /* RWI-V */ 18 19 #define NV_PFSP_QUEUE_HEAD(i) (0x008F2c00+(i)*8) /* RW-4A */ 20 #define NV_PFSP_QUEUE_HEAD__SIZE_1 8 /* */ 21 #define NV_PFSP_QUEUE_HEAD_ADDRESS 31:0 /* RWIVF */ 22 #define NV_PFSP_QUEUE_HEAD_ADDRESS_INIT 0x00000000 /* RWI-V */ 23 #define NV_PFSP_QUEUE_TAIL(i) (0x008F2c04+(i)*8) /* RW-4A */ 24 #define NV_PFSP_QUEUE_TAIL__SIZE_1 8 /* */ 25 #define NV_PFSP_QUEUE_TAIL_ADDRESS 31:0 /* RWIVF */ 26 #define NV_PFSP_QUEUE_TAIL_ADDRESS_INIT 0x00000000 /* RWI-V */ 27 28 #endif // __gh100_dev_fsp_pri_h__ 29