1 /* SPDX-License-Identifier: MIT 2 * 3 * Copyright (c) 2025, NVIDIA CORPORATION. All rights reserved. 4 */ 5 #ifndef __gh100_dev_falcon_v4_h__ 6 #define __gh100_dev_falcon_v4_h__ 7 8 #define NV_PFALCON_FALCON_MAILBOX0 0x00000040 /* RW-4R */ 9 #define NV_PFALCON_FALCON_MAILBOX0_DATA 31:0 /* RWIVF */ 10 #define NV_PFALCON_FALCON_MAILBOX0_DATA_INIT 0x00000000 /* RWI-V */ 11 #define NV_PFALCON_FALCON_MAILBOX1 0x00000044 /* RW-4R */ 12 #define NV_PFALCON_FALCON_MAILBOX1_DATA 31:0 /* RWIVF */ 13 #define NV_PFALCON_FALCON_MAILBOX1_DATA_INIT 0x00000000 /* RWI-V */ 14 15 #define NV_PFALCON_FALCON_HWCFG2 0x000000f4 /* R--4R */ 16 #define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN 13:13 /* R--VF */ 17 #define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_LOCK 0x00000001 /* R---V */ 18 #define NV_PFALCON_FALCON_HWCFG2_RISCV_BR_PRIV_LOCKDOWN_UNLOCK 0x00000000 /* R---V */ 19 20 #endif // __gh100_dev_falcon_v4_h__ 21