1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6 7<!-- 8 NOTE: also see mdss_hdmi_util.h.. newer devices using MDSS appear 9 to have the same HDMI block (or maybe a newer version?) but for 10 some reason duplicate the code under drivers/video/msm/mdss 11 --> 12 13<domain name="HDMI" width="32"> 14 <enum name="hdmi_hdcp_key_state"> 15 <value name="HDCP_KEYS_STATE_NO_KEYS" value="0"/> 16 <value name="HDCP_KEYS_STATE_NOT_CHECKED" value="1"/> 17 <value name="HDCP_KEYS_STATE_CHECKING" value="2"/> 18 <value name="HDCP_KEYS_STATE_VALID" value="3"/> 19 <value name="HDCP_KEYS_STATE_AKSV_NOT_VALID" value="4"/> 20 <value name="HDCP_KEYS_STATE_CHKSUM_MISMATCH" value="5"/> 21 <value name="HDCP_KEYS_STATE_PROD_AKSV" value="6"/> 22 <value name="HDCP_KEYS_STATE_RESERVED" value="7"/> 23 </enum> 24 <enum name="hdmi_ddc_read_write"> 25 <value name="DDC_WRITE" value="0"/> 26 <value name="DDC_READ" value="1"/> 27 </enum> 28 <enum name="hdmi_acr_cts"> 29 <value name="ACR_NONE" value="0"/> 30 <value name="ACR_32" value="1"/> 31 <value name="ACR_44" value="2"/> 32 <value name="ACR_48" value="3"/> 33 </enum> 34 35 <enum name="hdmi_cec_tx_status"> 36 <value name="CEC_TX_OK" value="0"/> 37 <value name="CEC_TX_NACK" value="1"/> 38 <value name="CEC_TX_ARB_LOSS" value="2"/> 39 <value name="CEC_TX_MAX_RETRIES" value="3"/> 40 </enum> 41 42 <reg32 offset="0x00000" name="CTRL"> 43 <bitfield name="ENABLE" pos="0" type="boolean"/> 44 <bitfield name="HDMI" pos="1" type="boolean"/> 45 <bitfield name="ENCRYPTED" pos="2" type="boolean"/> 46 </reg32> 47 <reg32 offset="0x00020" name="AUDIO_PKT_CTRL1"> 48 <bitfield name="AUDIO_SAMPLE_SEND" pos="0" type="boolean"/> 49 </reg32> 50 <reg32 offset="0x00024" name="ACR_PKT_CTRL"> 51 <!-- 52 Guessing on order of bitfields from these comments: 53 /* AUDIO_PRIORITY | SOURCE */ 54 acr_pck_ctrl_reg |= 0x80000100; 55 /* N_MULTIPLE(multiplier) */ 56 acr_pck_ctrl_reg |= (multiplier & 7) << 16; 57 /* SEND | CONT */ 58 acr_pck_ctrl_reg |= 0x00000003; 59 --> 60 <bitfield name="CONT" pos="0" type="boolean"/> 61 <bitfield name="SEND" pos="1" type="boolean"/> 62 <bitfield name="SELECT" low="4" high="5" type="hdmi_acr_cts"/> 63 <bitfield name="SOURCE" pos="8" type="boolean"/> 64 <bitfield name="N_MULTIPLIER" low="16" high="18" type="uint"/> 65 <bitfield name="AUDIO_PRIORITY" pos="31" type="boolean"/> 66 </reg32> 67 <reg32 offset="0x0028" name="VBI_PKT_CTRL"> 68 <!-- 69 Guessing on the order of bits from: 70 /* GC packet enable (every frame) */ 71 /* HDMI_VBI_PKT_CTRL[0x0028] */ 72 hdmi_msm_rmw32or(0x0028, 3 << 4); 73 /* HDMI_VBI_PKT_CTRL[0x0028] */ 74 /* ISRC Send + Continuous */ 75 hdmi_msm_rmw32or(0x0028, 3 << 8); 76 /* HDMI_VBI_PKT_CTRL[0x0028] */ 77 /* ACP send, s/w source */ 78 hdmi_msm_rmw32or(0x0028, 3 << 12); 79 --> 80 <bitfield name="GC_ENABLE" pos="4" type="boolean"/> 81 <bitfield name="GC_EVERY_FRAME" pos="5" type="boolean"/> 82 <bitfield name="ISRC_SEND" pos="8" type="boolean"/> 83 <bitfield name="ISRC_CONTINUOUS" pos="9" type="boolean"/> 84 <bitfield name="ACP_SEND" pos="12" type="boolean"/> 85 <bitfield name="ACP_SRC_SW" pos="13" type="boolean"/> 86 </reg32> 87 <reg32 offset="0x0002c" name="INFOFRAME_CTRL0"> 88 <!-- 89 Guessing on the order of these flags, from this comment: 90 /* Set these flags */ 91 /* AUDIO_INFO_UPDATE | AUDIO_INFO_SOURCE | AUDIO_INFO_CONT 92 | AUDIO_INFO_SEND */ 93 audio_info_ctrl_reg |= 0x000000F0; 94 /* 0x3 for AVI InfFrame enable (every frame) */ 95 HDMI_OUTP(0x002C, HDMI_INP(0x002C) | 0x00000003L); 96 --> 97 <bitfield name="AVI_SEND" pos="0" type="boolean"/> 98 <bitfield name="AVI_CONT" pos="1" type="boolean"/> <!-- every frame --> 99 <bitfield name="AUDIO_INFO_SEND" pos="4" type="boolean"/> 100 <bitfield name="AUDIO_INFO_CONT" pos="5" type="boolean"/> <!-- every frame --> 101 <bitfield name="AUDIO_INFO_SOURCE" pos="6" type="boolean"/> 102 <bitfield name="AUDIO_INFO_UPDATE" pos="7" type="boolean"/> 103 </reg32> 104 <reg32 offset="0x00030" name="INFOFRAME_CTRL1"> 105 <bitfield name="AVI_INFO_LINE" low="0" high="5" type="uint"/> 106 <bitfield name="AUDIO_INFO_LINE" low="8" high="13" type="uint"/> 107 <bitfield name="MPEG_INFO_LINE" low="16" high="21" type="uint"/> 108 <bitfield name="VENSPEC_INFO_LINE" low="24" high="29" type="uint"/> 109 </reg32> 110 <reg32 offset="0x00034" name="GEN_PKT_CTRL"> 111 <!-- 112 0x0034 GEN_PKT_CTRL 113 GENERIC0_SEND 0 0 = Disable Generic0 Packet Transmission 114 1 = Enable Generic0 Packet Transmission 115 GENERIC0_CONT 1 0 = Send Generic0 Packet on next frame only 116 1 = Send Generic0 Packet on every frame 117 GENERIC0_UPDATE 2 NUM 118 GENERIC1_SEND 4 0 = Disable Generic1 Packet Transmission 119 1 = Enable Generic1 Packet Transmission 120 GENERIC1_CONT 5 0 = Send Generic1 Packet on next frame only 121 1 = Send Generic1 Packet on every frame 122 GENERIC0_LINE 21:16 NUM 123 GENERIC1_LINE 29:24 NUM 124 125 GENERIC0_LINE | GENERIC0_UPDATE | GENERIC0_CONT | GENERIC0_SEND 126 Setup HDMI TX generic packet control 127 Enable this packet to transmit every frame 128 Enable this packet to transmit every frame 129 Enable HDMI TX engine to transmit Generic packet 0 130 HDMI_OUTP(0x0034, (1 << 16) | (1 << 2) | BIT(1) | BIT(0)); 131 --> 132 <bitfield name="GENERIC0_SEND" pos="0" type="boolean"/> 133 <bitfield name="GENERIC0_CONT" pos="1" type="boolean"/> 134 <bitfield name="GENERIC0_UPDATE" low="2" high="3" type="uint"/> <!-- ??? --> 135 <bitfield name="GENERIC1_SEND" pos="4" type="boolean"/> 136 <bitfield name="GENERIC1_CONT" pos="5" type="boolean"/> 137 <bitfield name="GENERIC0_LINE" low="16" high="21" type="uint"/> 138 <bitfield name="GENERIC1_LINE" low="24" high="29" type="uint"/> 139 </reg32> 140 <reg32 offset="0x00040" name="GC"> 141 <bitfield name="MUTE" pos="0" type="boolean"/> 142 </reg32> 143 <reg32 offset="0x00044" name="AUDIO_PKT_CTRL2"> 144 <bitfield name="OVERRIDE" pos="0" type="boolean"/> 145 <bitfield name="LAYOUT" pos="1" type="boolean"/> <!-- 1 for >2 channels --> 146 </reg32> 147 148 <!-- 149 AVI_INFO appears to be the infoframe in a slightly weird order.. 150 starts with PB0 (checksum), and ends with version.. 151 --> 152 <reg32 offset="0x0006c" name="AVI_INFO" stride="4" length="4"/> 153 154 <reg32 offset="0x00084" name="GENERIC0_HDR"/> 155 <reg32 offset="0x00088" name="GENERIC0" stride="4" length="7"/> 156 157 <reg32 offset="0x000a4" name="GENERIC1_HDR"/> 158 <reg32 offset="0x000a8" name="GENERIC1" stride="4" length="7"/> 159 160 <!-- 161 TODO add a way to show symbolic offsets into array: hdmi_acr_cts-1 162 --> 163 <array offset="0x00c4" name="ACR" length="3" stride="8" index="hdmi_acr_cts"> 164 <reg32 offset="0" name="0"> 165 <bitfield name="CTS" low="12" high="31" type="uint"/> 166 </reg32> 167 <reg32 offset="4" name="1"> 168 <!-- not sure the actual # of bits.. --> 169 <bitfield name="N" low="0" high="31" type="uint"/> 170 </reg32> 171 </array> 172 173 <reg32 offset="0x000e4" name="AUDIO_INFO0"> 174 <bitfield name="CHECKSUM" low="0" high="7"/> 175 <bitfield name="CC" low="8" high="10" type="uint"/> <!-- channel count --> 176 </reg32> 177 <reg32 offset="0x000e8" name="AUDIO_INFO1"> 178 <bitfield name="CA" low="0" high="7"/> <!-- Channel Allocation --> 179 <bitfield name="LSV" low="11" high="14"/> <!-- Level Shift --> 180 <bitfield name="DM_INH" pos="15" type="boolean"/> <!-- down-mix inhibit flag --> 181 </reg32> 182 <reg32 offset="0x00110" name="HDCP_CTRL"> 183 <bitfield name="ENABLE" pos="0" type="boolean"/> 184 <bitfield name="ENCRYPTION_ENABLE" pos="8" type="boolean"/> 185 </reg32> 186 <reg32 offset="0x00114" name="HDCP_DEBUG_CTRL"> 187 <bitfield name="RNG_CIPHER" pos="2" type="boolean"/> 188 </reg32> 189 <reg32 offset="0x00118" name="HDCP_INT_CTRL"> 190 <bitfield name="AUTH_SUCCESS_INT" pos="0" type="boolean"/> 191 <bitfield name="AUTH_SUCCESS_ACK" pos="1" type="boolean"/> 192 <bitfield name="AUTH_SUCCESS_MASK" pos="2" type="boolean"/> 193 <bitfield name="AUTH_FAIL_INT" pos="4" type="boolean"/> 194 <bitfield name="AUTH_FAIL_ACK" pos="5" type="boolean"/> 195 <bitfield name="AUTH_FAIL_MASK" pos="6" type="boolean"/> 196 <bitfield name="AUTH_FAIL_INFO_ACK" pos="7" type="boolean"/> 197 <bitfield name="AUTH_XFER_REQ_INT" pos="8" type="boolean"/> 198 <bitfield name="AUTH_XFER_REQ_ACK" pos="9" type="boolean"/> 199 <bitfield name="AUTH_XFER_REQ_MASK" pos="10" type="boolean"/> 200 <bitfield name="AUTH_XFER_DONE_INT" pos="12" type="boolean"/> 201 <bitfield name="AUTH_XFER_DONE_ACK" pos="13" type="boolean"/> 202 <bitfield name="AUTH_XFER_DONE_MASK" pos="14" type="boolean"/> 203 </reg32> 204 <reg32 offset="0x0011c" name="HDCP_LINK0_STATUS"> 205 <bitfield name="AN_0_READY" pos="8" type="boolean"/> 206 <bitfield name="AN_1_READY" pos="9" type="boolean"/> 207 <bitfield name="RI_MATCHES" pos="12" type="boolean"/> 208 <bitfield name="V_MATCHES" pos="20" type="boolean"/> 209 <bitfield name="KEY_STATE" low="28" high="30" type="hdmi_hdcp_key_state"/> 210 </reg32> 211 <reg32 offset="0x00120" name="HDCP_DDC_CTRL_0"> 212 <bitfield name="DISABLE" pos="0" type="boolean"/> 213 </reg32> 214 <reg32 offset="0x00124" name="HDCP_DDC_CTRL_1"> 215 <bitfield name="FAILED_ACK" pos="0" type="boolean"/> 216 </reg32> 217 <reg32 offset="0x00128" name="HDCP_DDC_STATUS"> 218 <bitfield name="XFER_REQ" pos="4" type="boolean"/> 219 <bitfield name="XFER_DONE" pos="10" type="boolean"/> 220 <bitfield name="ABORTED" pos="12" type="boolean"/> 221 <bitfield name="TIMEOUT" pos="13" type="boolean"/> 222 <bitfield name="NACK0" pos="14" type="boolean"/> 223 <bitfield name="NACK1" pos="15" type="boolean"/> 224 <bitfield name="FAILED" pos="16" type="boolean"/> 225 </reg32> 226 227 <reg32 offset="0x0012c" name="HDCP_ENTROPY_CTRL0"/> 228 <reg32 offset="0x0025c" name="HDCP_ENTROPY_CTRL1"/> 229 230 <reg32 offset="0x00130" name="HDCP_RESET"> 231 <bitfield name="LINK0_DEAUTHENTICATE" pos="0" type="boolean"/> 232 </reg32> 233 234 <reg32 offset="0x00134" name="HDCP_RCVPORT_DATA0"/> 235 <reg32 offset="0x00138" name="HDCP_RCVPORT_DATA1"/> 236 <reg32 offset="0x0013C" name="HDCP_RCVPORT_DATA2_0"/> 237 <reg32 offset="0x00140" name="HDCP_RCVPORT_DATA2_1"/> 238 <reg32 offset="0x00144" name="HDCP_RCVPORT_DATA3"/> 239 <reg32 offset="0x00148" name="HDCP_RCVPORT_DATA4"/> 240 <reg32 offset="0x0014c" name="HDCP_RCVPORT_DATA5"/> 241 <reg32 offset="0x00150" name="HDCP_RCVPORT_DATA6"/> 242 <reg32 offset="0x00154" name="HDCP_RCVPORT_DATA7"/> 243 <reg32 offset="0x00158" name="HDCP_RCVPORT_DATA8"/> 244 <reg32 offset="0x0015c" name="HDCP_RCVPORT_DATA9"/> 245 <reg32 offset="0x00160" name="HDCP_RCVPORT_DATA10"/> 246 <reg32 offset="0x00164" name="HDCP_RCVPORT_DATA11"/> 247 <reg32 offset="0x00168" name="HDCP_RCVPORT_DATA12"/> 248 249 <reg32 offset="0x0016c" name="VENSPEC_INFO0"/> 250 <reg32 offset="0x00170" name="VENSPEC_INFO1"/> 251 <reg32 offset="0x00174" name="VENSPEC_INFO2"/> 252 <reg32 offset="0x00178" name="VENSPEC_INFO3"/> 253 <reg32 offset="0x0017c" name="VENSPEC_INFO4"/> 254 <reg32 offset="0x00180" name="VENSPEC_INFO5"/> 255 <reg32 offset="0x00184" name="VENSPEC_INFO6"/> 256 257 <reg32 offset="0x001d0" name="AUDIO_CFG"> 258 <bitfield name="ENGINE_ENABLE" pos="0" type="boolean"/> 259 <bitfield name="FIFO_WATERMARK" low="4" high="7" type="uint"/> 260 </reg32> 261 262 <reg32 offset="0x00208" name="USEC_REFTIMER"/> 263 <reg32 offset="0x0020c" name="DDC_CTRL"> 264 <!-- 265 0x020C HDMI_DDC_CTRL 266 [21:20] TRANSACTION_CNT 267 Number of transactions to be done in current transfer. 268 * 0x0: transaction0 only 269 * 0x1: transaction0, transaction1 270 * 0x2: transaction0, transaction1, transaction2 271 * 0x3: transaction0, transaction1, transaction2, transaction3 272 [3] SW_STATUS_RESET 273 Write 1 to reset HDMI_DDC_SW_STATUS flags, will reset SW_DONE, 274 ABORTED, TIMEOUT, SW_INTERRUPTED, BUFFER_OVERFLOW, 275 STOPPED_ON_NACK, NACK0, NACK1, NACK2, NACK3 276 [2] SEND_RESET Set to 1 to send reset sequence (9 clocks with no 277 data) at start of transfer. This sequence is sent after GO is 278 written to 1, before the first transaction only. 279 [1] SOFT_RESET Write 1 to reset DDC controller 280 [0] GO WRITE ONLY. Write 1 to start DDC transfer. 281 --> 282 <bitfield name="GO" pos="0" type="boolean"/> 283 <bitfield name="SOFT_RESET" pos="1" type="boolean"/> 284 <bitfield name="SEND_RESET" pos="2" type="boolean"/> 285 <bitfield name="SW_STATUS_RESET" pos="3" type="boolean"/> 286 <bitfield name="TRANSACTION_CNT" low="20" high="21" type="uint"/> 287 </reg32> 288 <reg32 offset="0x00210" name="DDC_ARBITRATION"> 289 <bitfield name="HW_ARBITRATION" pos="4" type="boolean"/> 290 </reg32> 291 <reg32 offset="0x00214" name="DDC_INT_CTRL"> 292 <!-- 293 HDMI_DDC_INT_CTRL[0x0214] 294 [2] SW_DONE_MK Mask bit for SW_DONE_INT. Set to 1 to enable 295 interrupt. 296 [1] SW_DONE_ACK WRITE ONLY. Acknowledge bit for SW_DONE_INT. 297 Write 1 to clear interrupt. 298 [0] SW_DONE_INT READ ONLY. SW_DONE interrupt status */ 299 --> 300 <bitfield name="SW_DONE_INT" pos="0" type="boolean"/> 301 <bitfield name="SW_DONE_ACK" pos="1" type="boolean"/> 302 <bitfield name="SW_DONE_MASK" pos="2" type="boolean"/> 303 </reg32> 304 <reg32 offset="0x00218" name="DDC_SW_STATUS"> 305 <bitfield name="NACK0" pos="12" type="boolean"/> 306 <bitfield name="NACK1" pos="13" type="boolean"/> 307 <bitfield name="NACK2" pos="14" type="boolean"/> 308 <bitfield name="NACK3" pos="15" type="boolean"/> 309 </reg32> 310 <reg32 offset="0x0021c" name="DDC_HW_STATUS"> 311 <bitfield name="DONE" pos="3" type="boolean"/> 312 </reg32> 313 <reg32 offset="0x00220" name="DDC_SPEED"> 314 <!-- 315 0x0220 HDMI_DDC_SPEED 316 [31:16] PRESCALE prescale = (m * xtal_frequency) / 317 (desired_i2c_speed), where m is multiply 318 factor, default: m = 1 319 [1:0] THRESHOLD Select threshold to use to determine whether value 320 sampled on SDA is a 1 or 0. Specified in terms of the ratio 321 between the number of sampled ones and the total number of times 322 SDA is sampled. 323 * 0x0: >0 324 * 0x1: 1/4 of total samples 325 * 0x2: 1/2 of total samples 326 * 0x3: 3/4 of total samples */ 327 --> 328 <bitfield name="THRESHOLD" low="0" high="1" type="uint"/> 329 <bitfield name="PRESCALE" low="16" high="31" type="uint"/> 330 </reg32> 331 <reg32 offset="0x00224" name="DDC_SETUP"> 332 <!-- 333 * 0x0224 HDMI_DDC_SETUP 334 * Setting 31:24 bits : Time units to wait before timeout 335 * when clock is being stalled by external sink device 336 --> 337 <bitfield name="TIMEOUT" low="24" high="31" type="uint"/> 338 </reg32> 339 <!-- Guessing length is 4, as elsewhere the are references to trans0 thru trans3 --> 340 <array offset="0x00228" name="I2C_TRANSACTION" length="4" stride="4"> 341 <reg32 offset="0" name="REG"> 342 <!-- 343 0x0228 HDMI_DDC_TRANS0 344 [23:16] CNT0 Byte count for first transaction (excluding the first 345 byte, which is usually the address). 346 [13] STOP0 Determines whether a stop bit will be sent after the first 347 transaction 348 * 0: NO STOP 349 * 1: STOP 350 [12] START0 Determines whether a start bit will be sent before the 351 first transaction 352 * 0: NO START 353 * 1: START 354 [8] STOP_ON_NACK0 Determines whether the current transfer will stop 355 if a NACK is received during the first transaction (current 356 transaction always stops). 357 * 0: STOP CURRENT TRANSACTION, GO TO NEXT TRANSACTION 358 * 1: STOP ALL TRANSACTIONS, SEND STOP BIT 359 [0] RW0 Read/write indicator for first transaction - set to 0 for 360 write, 1 for read. This bit only controls HDMI_DDC behaviour - 361 the R/W bit in the transaction is programmed into the DDC buffer 362 as the LSB of the address byte. 363 * 0: WRITE 364 * 1: READ 365 --> 366 <bitfield name="RW" pos="0" type="hdmi_ddc_read_write"/> 367 <bitfield name="STOP_ON_NACK" pos="8" type="boolean"/> 368 <bitfield name="START" pos="12" type="boolean"/> 369 <bitfield name="STOP" pos="13" type="boolean"/> 370 <bitfield name="CNT" low="16" high="23" type="uint"/> 371 </reg32> 372 </array> 373 <reg32 offset="0x00238" name="DDC_DATA"> 374 <!-- 375 0x0238 HDMI_DDC_DATA 376 [31] INDEX_WRITE WRITE ONLY. To write index field, set this bit to 377 1 while writing HDMI_DDC_DATA. 378 [23:16] INDEX Use to set index into DDC buffer for next read or 379 current write, or to read index of current read or next write. 380 Writable only when INDEX_WRITE=1. 381 [15:8] DATA Use to fill or read the DDC buffer 382 [0] DATA_RW Select whether buffer access will be a read or write. 383 For writes, address auto-increments on write to HDMI_DDC_DATA. 384 For reads, address autoincrements on reads to HDMI_DDC_DATA. 385 * 0: Write 386 * 1: Read 387 --> 388 <bitfield name="DATA_RW" pos="0" type="hdmi_ddc_read_write"/> 389 <bitfield name="DATA" low="8" high="15" type="uint"/> 390 <bitfield name="INDEX" low="16" high="23" type="uint"/> 391 <bitfield name="INDEX_WRITE" pos="31" type="boolean"/> 392 </reg32> 393 394 <reg32 offset="0x0023c" name="HDCP_SHA_CTRL"/> 395 <reg32 offset="0x00240" name="HDCP_SHA_STATUS"> 396 <bitfield name="BLOCK_DONE" pos="0" type="boolean"/> 397 <bitfield name="COMP_DONE" pos="4" type="boolean"/> 398 </reg32> 399 <reg32 offset="0x00244" name="HDCP_SHA_DATA"> 400 <bitfield name="DONE" pos="0" type="boolean"/> 401 </reg32> 402 403 <reg32 offset="0x00250" name="HPD_INT_STATUS"> 404 <bitfield name="INT" pos="0" type="boolean"/> <!-- an irq has occurred --> 405 <bitfield name="CABLE_DETECTED" pos="1" type="boolean"/> 406 </reg32> 407 <reg32 offset="0x00254" name="HPD_INT_CTRL"> 408 <!-- (this useful comment was removed in df6b645.. git archaeology is fun) 409 HPD_INT_CTRL[0x0254] 410 31:10 Reserved 411 9 RCV_PLUGIN_DET_MASK receiver plug in interrupt mask. 412 When programmed to 1, 413 RCV_PLUGIN_DET_INT will toggle 414 the interrupt line 415 8:6 Reserved 416 5 RX_INT_EN Panel RX interrupt enable 417 0: Disable 418 1: Enable 419 4 RX_INT_ACK WRITE ONLY. Panel RX interrupt 420 ack 421 3 Reserved 422 2 INT_EN Panel interrupt control 423 0: Disable 424 1: Enable 425 1 INT_POLARITY Panel interrupt polarity 426 0: generate interrupt on disconnect 427 1: generate interrupt on connect 428 0 INT_ACK WRITE ONLY. Panel interrupt ack 429 --> 430 <bitfield name="INT_ACK" pos="0" type="boolean"/> 431 <bitfield name="INT_CONNECT" pos="1" type="boolean"/> 432 <bitfield name="INT_EN" pos="2" type="boolean"/> 433 <bitfield name="RX_INT_ACK" pos="4" type="boolean"/> 434 <bitfield name="RX_INT_EN" pos="5" type="boolean"/> 435 <bitfield name="RCV_PLUGIN_DET_MASK" pos="9" type="boolean"/> 436 </reg32> 437 <reg32 offset="0x00258" name="HPD_CTRL"> 438 <bitfield name="TIMEOUT" low="0" high="12" type="uint"/> 439 <bitfield name="ENABLE" pos="28" type="boolean"/> 440 </reg32> 441 <reg32 offset="0x0027c" name="DDC_REF"> 442 <!-- 443 0x027C HDMI_DDC_REF 444 [16] REFTIMER_ENABLE Enable the timer 445 * 0: Disable 446 * 1: Enable 447 [15:0] REFTIMER Value to set the register in order to generate 448 DDC strobe. This register counts on HDCP application clock 449 450 /* Enable reference timer 451 * 27 micro-seconds */ 452 HDMI_OUTP_ND(0x027C, (1 << 16) | (27 << 0)); 453 --> 454 <bitfield name="REFTIMER_ENABLE" pos="16" type="boolean"/> 455 <bitfield name="REFTIMER" low="0" high="15" type="uint"/> 456 </reg32> 457 458 <reg32 offset="0x00284" name="HDCP_SW_UPPER_AKSV"/> 459 <reg32 offset="0x00288" name="HDCP_SW_LOWER_AKSV"/> 460 461 <reg32 offset="0x0028c" name="CEC_CTRL"> 462 <bitfield name="ENABLE" pos="0" type="boolean"/> 463 <bitfield name="SEND_TRIGGER" pos="1" type="boolean"/> 464 <bitfield name="FRAME_SIZE" low="4" high="8" type="uint"/> 465 <bitfield name="LINE_OE" pos="9" type="boolean"/> 466 </reg32> 467 <reg32 offset="0x00290" name="CEC_WR_DATA"> 468 <bitfield name="BROADCAST" pos="0" type="boolean"/> 469 <bitfield name="DATA" low="8" high="15" type="uint"/> 470 </reg32> 471 <reg32 offset="0x00294" name="CEC_RETRANSMIT"> 472 <bitfield name="ENABLE" pos="0" type="boolean"/> 473 <bitfield name="COUNT" low="1" high="7" type="uint"/> 474 </reg32> 475 <reg32 offset="0x00298" name="CEC_STATUS"> 476 <bitfield name="BUSY" pos="0" type="boolean"/> 477 <bitfield name="TX_FRAME_DONE" pos="3" type="boolean"/> 478 <bitfield name="TX_STATUS" low="4" high="7" type="hdmi_cec_tx_status"/> 479 </reg32> 480 <reg32 offset="0x0029c" name="CEC_INT"> 481 <bitfield name="TX_DONE" pos="0" type="boolean"/> 482 <bitfield name="TX_DONE_MASK" pos="1" type="boolean"/> 483 <bitfield name="TX_ERROR" pos="2" type="boolean"/> 484 <bitfield name="TX_ERROR_MASK" pos="3" type="boolean"/> 485 <bitfield name="MONITOR" pos="4" type="boolean"/> 486 <bitfield name="MONITOR_MASK" pos="5" type="boolean"/> 487 <bitfield name="RX_DONE" pos="6" type="boolean"/> 488 <bitfield name="RX_DONE_MASK" pos="7" type="boolean"/> 489 </reg32> 490 <reg32 offset="0x002a0" name="CEC_ADDR"/> 491 <reg32 offset="0x002a4" name="CEC_TIME"> 492 <bitfield name="ENABLE" pos="0" type="boolean"/> 493 <bitfield name="SIGNAL_FREE_TIME" low="7" high="15" type="uint"/> 494 </reg32> 495 <reg32 offset="0x002a8" name="CEC_REFTIMER"> 496 <bitfield name="REFTIMER" low="0" high="15" type="uint"/> 497 <bitfield name="ENABLE" pos="16" type="boolean"/> 498 </reg32> 499 <reg32 offset="0x002ac" name="CEC_RD_DATA"> 500 <bitfield name="DATA" low="0" high="7" type="uint"/> 501 <bitfield name="SIZE" low="8" high="12" type="uint"/> 502 </reg32> 503 <reg32 offset="0x002b0" name="CEC_RD_FILTER"/> 504 505 <reg32 offset="0x002b4" name="ACTIVE_HSYNC"> 506 <bitfield name="START" low="0" high="12" type="uint"/> 507 <bitfield name="END" low="16" high="27" type="uint"/> 508 </reg32> 509 <reg32 offset="0x002b8" name="ACTIVE_VSYNC"> 510 <bitfield name="START" low="0" high="12" type="uint"/> 511 <bitfield name="END" low="16" high="28" type="uint"/> 512 </reg32> 513 <reg32 offset="0x002bc" name="VSYNC_ACTIVE_F2"> 514 <!-- interlaced, frame 2 --> 515 <bitfield name="START" low="0" high="12" type="uint"/> 516 <bitfield name="END" low="16" high="28" type="uint"/> 517 </reg32> 518 <reg32 offset="0x002c0" name="TOTAL"> 519 <bitfield name="H_TOTAL" low="0" high="12" type="uint"/> 520 <bitfield name="V_TOTAL" low="16" high="28" type="uint"/> 521 </reg32> 522 <reg32 offset="0x002c4" name="VSYNC_TOTAL_F2"> 523 <!-- interlaced, frame 2 --> 524 <bitfield name="V_TOTAL" low="0" high="12" type="uint"/> 525 </reg32> 526 <reg32 offset="0x002c8" name="FRAME_CTRL"> 527 <bitfield name="RGB_MUX_SEL_BGR" pos="12" type="boolean"/> 528 <bitfield name="VSYNC_LOW" pos="28" type="boolean"/> 529 <bitfield name="HSYNC_LOW" pos="29" type="boolean"/> 530 <bitfield name="INTERLACED_EN" pos="31" type="boolean"/> 531 </reg32> 532 <reg32 offset="0x002cc" name="AUD_INT"> 533 <!-- 534 HDMI_AUD_INT[0x02CC] 535 [3] AUD_SAM_DROP_MASK [R/W] 536 [2] AUD_SAM_DROP_ACK [W], AUD_SAM_DROP_INT [R] 537 [1] AUD_FIFO_URUN_MASK [R/W] 538 [0] AUD_FIFO_URUN_ACK [W], AUD_FIFO_URUN_INT [R] 539 --> 540 <bitfield name="AUD_FIFO_URUN_INT" pos="0" type="boolean"/> <!-- write to ack irq --> 541 <bitfield name="AUD_FIFO_URAN_MASK" pos="1" type="boolean"/> <!-- r/w, enables irq --> 542 <bitfield name="AUD_SAM_DROP_INT" pos="2" type="boolean"/> <!-- write to ack irq --> 543 <bitfield name="AUD_SAM_DROP_MASK" pos="3" type="boolean"/> <!-- r/w, enables irq --> 544 </reg32> 545 <reg32 offset="0x002d4" name="PHY_CTRL"> 546 <!-- 547 in hdmi_phy_reset() it appears to be toggling SW_RESET/ 548 SW_RESET_PLL based on the value of the bit above, so 549 I'm guessing the bit above is a polarit bit 550 --> 551 <bitfield name="SW_RESET_PLL" pos="0" type="boolean"/> 552 <bitfield name="SW_RESET_PLL_LOW" pos="1" type="boolean"/> 553 <bitfield name="SW_RESET" pos="2" type="boolean"/> 554 <bitfield name="SW_RESET_LOW" pos="3" type="boolean"/> 555 </reg32> 556 <reg32 offset="0x002dc" name="CEC_WR_RANGE"/> 557 <reg32 offset="0x002e0" name="CEC_RD_RANGE"/> 558 <reg32 offset="0x002e4" name="VERSION"/> 559 <reg32 offset="0x00360" name="CEC_COMPL_CTL"/> 560 <reg32 offset="0x00364" name="CEC_RD_START_RANGE"/> 561 <reg32 offset="0x00368" name="CEC_RD_TOTAL_RANGE"/> 562 <reg32 offset="0x0036c" name="CEC_RD_ERR_RESP_LO"/> 563 <reg32 offset="0x00370" name="CEC_WR_CHECK_CONFIG"/> 564 565</domain> 566 567<domain name="HDMI_8x60" width="32"> 568 <reg32 offset="0x00000" name="PHY_REG0"> 569 <bitfield name="DESER_DEL_CTRL" low="2" high="4" type="uint"/> 570 </reg32> 571 <reg32 offset="0x00004" name="PHY_REG1"> 572 <bitfield name="DTEST_MUX_SEL" low="4" high="7" type="uint"/> 573 <bitfield name="OUTVOL_SWING_CTRL" low="0" high="3" type="uint"/> 574 </reg32> 575 <reg32 offset="0x00008" name="PHY_REG2"> 576 <bitfield name="PD_DESER" pos="0" type="boolean"/> 577 <bitfield name="PD_DRIVE_1" pos="1" type="boolean"/> 578 <bitfield name="PD_DRIVE_2" pos="2" type="boolean"/> 579 <bitfield name="PD_DRIVE_3" pos="3" type="boolean"/> 580 <bitfield name="PD_DRIVE_4" pos="4" type="boolean"/> 581 <bitfield name="PD_PLL" pos="5" type="boolean"/> 582 <bitfield name="PD_PWRGEN" pos="6" type="boolean"/> 583 <bitfield name="RCV_SENSE_EN" pos="7" type="boolean"/> 584 </reg32> 585 <reg32 offset="0x0000c" name="PHY_REG3"> 586 <bitfield name="PLL_ENABLE" pos="0" type="boolean"/> 587 </reg32> 588 <reg32 offset="0x00010" name="PHY_REG4"/> 589 <reg32 offset="0x00014" name="PHY_REG5"/> 590 <reg32 offset="0x00018" name="PHY_REG6"/> 591 <reg32 offset="0x0001c" name="PHY_REG7"/> 592 <reg32 offset="0x00020" name="PHY_REG8"/> 593 <reg32 offset="0x00024" name="PHY_REG9"/> 594 <reg32 offset="0x00028" name="PHY_REG10"/> 595 <reg32 offset="0x0002c" name="PHY_REG11"/> 596 <reg32 offset="0x00030" name="PHY_REG12"> 597 <bitfield name="RETIMING_EN" pos="0" type="boolean"/> 598 <bitfield name="PLL_LOCK_DETECT_EN" pos="1" type="boolean"/> 599 <bitfield name="FORCE_LOCK" pos="4" type="boolean"/> 600 </reg32> 601</domain> 602 603<domain name="HDMI_8960" width="32"> 604 <!-- 605 some of the bitfields may be same as 8x60.. but no helpful comments 606 in msm_dss_io_8960.c 607 --> 608 <reg32 offset="0x00000" name="PHY_REG0"/> 609 <reg32 offset="0x00004" name="PHY_REG1"/> 610 <reg32 offset="0x00008" name="PHY_REG2"/> 611 <reg32 offset="0x0000c" name="PHY_REG3"/> 612 <reg32 offset="0x00010" name="PHY_REG4"/> 613 <reg32 offset="0x00014" name="PHY_REG5"/> 614 <reg32 offset="0x00018" name="PHY_REG6"/> 615 <reg32 offset="0x0001c" name="PHY_REG7"/> 616 <reg32 offset="0x00020" name="PHY_REG8"/> 617 <reg32 offset="0x00024" name="PHY_REG9"/> 618 <reg32 offset="0x00028" name="PHY_REG10"/> 619 <reg32 offset="0x0002c" name="PHY_REG11"/> 620 <reg32 offset="0x00030" name="PHY_REG12"> 621 <bitfield name="SW_RESET" pos="5" type="boolean"/> 622 <bitfield name="PWRDN_B" pos="7" type="boolean"/> 623 </reg32> 624 <reg32 offset="0x00034" name="PHY_REG_BIST_CFG"/> 625 <reg32 offset="0x00038" name="PHY_DEBUG_BUS_SEL"/> 626 <reg32 offset="0x0003c" name="PHY_REG_MISC0"/> 627 <reg32 offset="0x00040" name="PHY_REG13"/> 628 <reg32 offset="0x00044" name="PHY_REG14"/> 629 <reg32 offset="0x00048" name="PHY_REG15"/> 630</domain> 631 632<domain name="HDMI_8960_PHY_PLL" width="32"> 633 <reg32 offset="0x00000" name="REFCLK_CFG"/> 634 <reg32 offset="0x00004" name="CHRG_PUMP_CFG"/> 635 <reg32 offset="0x00008" name="LOOP_FLT_CFG0"/> 636 <reg32 offset="0x0000c" name="LOOP_FLT_CFG1"/> 637 <reg32 offset="0x00010" name="IDAC_ADJ_CFG"/> 638 <reg32 offset="0x00014" name="I_VI_KVCO_CFG"/> 639 <reg32 offset="0x00018" name="PWRDN_B"> 640 <bitfield name="PD_PLL" pos="1" type="boolean"/> 641 <bitfield name="PLL_PWRDN_B" pos="3" type="boolean"/> 642 </reg32> 643 <reg32 offset="0x0001c" name="SDM_CFG0"/> 644 <reg32 offset="0x00020" name="SDM_CFG1"/> 645 <reg32 offset="0x00024" name="SDM_CFG2"/> 646 <reg32 offset="0x00028" name="SDM_CFG3"/> 647 <reg32 offset="0x0002c" name="SDM_CFG4"/> 648 <reg32 offset="0x00030" name="SSC_CFG0"/> 649 <reg32 offset="0x00034" name="SSC_CFG1"/> 650 <reg32 offset="0x00038" name="SSC_CFG2"/> 651 <reg32 offset="0x0003c" name="SSC_CFG3"/> 652 <reg32 offset="0x00040" name="LOCKDET_CFG0"/> 653 <reg32 offset="0x00044" name="LOCKDET_CFG1"/> 654 <reg32 offset="0x00048" name="LOCKDET_CFG2"/> 655 <reg32 offset="0x0004c" name="VCOCAL_CFG0"/> 656 <reg32 offset="0x00050" name="VCOCAL_CFG1"/> 657 <reg32 offset="0x00054" name="VCOCAL_CFG2"/> 658 <reg32 offset="0x00058" name="VCOCAL_CFG3"/> 659 <reg32 offset="0x0005c" name="VCOCAL_CFG4"/> 660 <reg32 offset="0x00060" name="VCOCAL_CFG5"/> 661 <reg32 offset="0x00064" name="VCOCAL_CFG6"/> 662 <reg32 offset="0x00068" name="VCOCAL_CFG7"/> 663 <reg32 offset="0x0006c" name="DEBUG_SEL"/> 664 <reg32 offset="0x00070" name="MISC0"/> 665 <reg32 offset="0x00074" name="MISC1"/> 666 <reg32 offset="0x00078" name="MISC2"/> 667 <reg32 offset="0x0007c" name="MISC3"/> 668 <reg32 offset="0x00080" name="MISC4"/> 669 <reg32 offset="0x00084" name="MISC5"/> 670 <reg32 offset="0x00088" name="MISC6"/> 671 <reg32 offset="0x0008c" name="DEBUG_BUS0"/> 672 <reg32 offset="0x00090" name="DEBUG_BUS1"/> 673 <reg32 offset="0x00094" name="DEBUG_BUS2"/> 674 <reg32 offset="0x00098" name="STATUS0"> 675 <bitfield name="PLL_LOCK" pos="0" type="boolean"/> 676 </reg32> 677 <reg32 offset="0x0009c" name="STATUS1"/> 678</domain> 679 680<domain name="HDMI_8x74" width="32"> 681 <!-- 682 seems to be all mdp5+ have same? 683 --> 684 <reg32 offset="0x00000" name="ANA_CFG0"/> 685 <reg32 offset="0x00004" name="ANA_CFG1"/> 686 <reg32 offset="0x00008" name="ANA_CFG2"/> 687 <reg32 offset="0x0000c" name="ANA_CFG3"/> 688 <reg32 offset="0x00010" name="PD_CTRL0"/> 689 <reg32 offset="0x00014" name="PD_CTRL1"/> 690 <reg32 offset="0x00018" name="GLB_CFG"/> 691 <reg32 offset="0x0001c" name="DCC_CFG0"/> 692 <reg32 offset="0x00020" name="DCC_CFG1"/> 693 <reg32 offset="0x00024" name="TXCAL_CFG0"/> 694 <reg32 offset="0x00028" name="TXCAL_CFG1"/> 695 <reg32 offset="0x0002c" name="TXCAL_CFG2"/> 696 <reg32 offset="0x00030" name="TXCAL_CFG3"/> 697 <reg32 offset="0x00034" name="BIST_CFG0"/> 698 <reg32 offset="0x0003c" name="BIST_PATN0"/> 699 <reg32 offset="0x00040" name="BIST_PATN1"/> 700 <reg32 offset="0x00044" name="BIST_PATN2"/> 701 <reg32 offset="0x00048" name="BIST_PATN3"/> 702 <reg32 offset="0x0005c" name="STATUS"/> 703</domain> 704 705<domain name="HDMI_28nm_PHY_PLL" width="32"> 706 <reg32 offset="0x00000" name="REFCLK_CFG"/> 707 <reg32 offset="0x00004" name="POSTDIV1_CFG"/> 708 <reg32 offset="0x00008" name="CHGPUMP_CFG"/> 709 <reg32 offset="0x0000C" name="VCOLPF_CFG"/> 710 <reg32 offset="0x00010" name="VREG_CFG"/> 711 <reg32 offset="0x00014" name="PWRGEN_CFG"/> 712 <reg32 offset="0x00018" name="DMUX_CFG"/> 713 <reg32 offset="0x0001C" name="AMUX_CFG"/> 714 <reg32 offset="0x00020" name="GLB_CFG"> 715 <bitfield name="PLL_PWRDN_B" pos="0" type="boolean"/> 716 <bitfield name="PLL_LDO_PWRDN_B" pos="1" type="boolean"/> 717 <bitfield name="PLL_PWRGEN_PWRDN_B" pos="2" type="boolean"/> 718 <bitfield name="PLL_ENABLE" pos="3" type="boolean"/> 719 </reg32> 720 <reg32 offset="0x00024" name="POSTDIV2_CFG"/> 721 <reg32 offset="0x00028" name="POSTDIV3_CFG"/> 722 <reg32 offset="0x0002C" name="LPFR_CFG"/> 723 <reg32 offset="0x00030" name="LPFC1_CFG"/> 724 <reg32 offset="0x00034" name="LPFC2_CFG"/> 725 <reg32 offset="0x00038" name="SDM_CFG0"/> 726 <reg32 offset="0x0003C" name="SDM_CFG1"/> 727 <reg32 offset="0x00040" name="SDM_CFG2"/> 728 <reg32 offset="0x00044" name="SDM_CFG3"/> 729 <reg32 offset="0x00048" name="SDM_CFG4"/> 730 <reg32 offset="0x0004C" name="SSC_CFG0"/> 731 <reg32 offset="0x00050" name="SSC_CFG1"/> 732 <reg32 offset="0x00054" name="SSC_CFG2"/> 733 <reg32 offset="0x00058" name="SSC_CFG3"/> 734 <reg32 offset="0x0005C" name="LKDET_CFG0"/> 735 <reg32 offset="0x00060" name="LKDET_CFG1"/> 736 <reg32 offset="0x00064" name="LKDET_CFG2"/> 737 <reg32 offset="0x00068" name="TEST_CFG"> 738 <bitfield name="PLL_SW_RESET" pos="0" type="boolean"/> 739 </reg32> 740 <reg32 offset="0x0006C" name="CAL_CFG0"/> 741 <reg32 offset="0x00070" name="CAL_CFG1"/> 742 <reg32 offset="0x00074" name="CAL_CFG2"/> 743 <reg32 offset="0x00078" name="CAL_CFG3"/> 744 <reg32 offset="0x0007C" name="CAL_CFG4"/> 745 <reg32 offset="0x00080" name="CAL_CFG5"/> 746 <reg32 offset="0x00084" name="CAL_CFG6"/> 747 <reg32 offset="0x00088" name="CAL_CFG7"/> 748 <reg32 offset="0x0008C" name="CAL_CFG8"/> 749 <reg32 offset="0x00090" name="CAL_CFG9"/> 750 <reg32 offset="0x00094" name="CAL_CFG10"/> 751 <reg32 offset="0x00098" name="CAL_CFG11"/> 752 <reg32 offset="0x0009C" name="EFUSE_CFG"/> 753 <reg32 offset="0x000A0" name="DEBUG_BUS_SEL"/> 754 <reg32 offset="0x000C0" name="STATUS"/> 755</domain> 756 757<domain name="HDMI_8996_PHY" width="32"> 758 <reg32 offset="0x00000" name="CFG"/> 759 <reg32 offset="0x00004" name="PD_CTL"/> 760 <reg32 offset="0x00008" name="MODE"/> 761 <reg32 offset="0x0000C" name="MISR_CLEAR"/> 762 <reg32 offset="0x00010" name="TX0_TX1_BIST_CFG0"/> 763 <reg32 offset="0x00014" name="TX0_TX1_BIST_CFG1"/> 764 <reg32 offset="0x00018" name="TX0_TX1_PRBS_SEED_BYTE0"/> 765 <reg32 offset="0x0001C" name="TX0_TX1_PRBS_SEED_BYTE1"/> 766 <reg32 offset="0x00020" name="TX0_TX1_BIST_PATTERN0"/> 767 <reg32 offset="0x00024" name="TX0_TX1_BIST_PATTERN1"/> 768 <reg32 offset="0x00028" name="TX2_TX3_BIST_CFG0"/> 769 <reg32 offset="0x0002C" name="TX2_TX3_BIST_CFG1"/> 770 <reg32 offset="0x00030" name="TX2_TX3_PRBS_SEED_BYTE0"/> 771 <reg32 offset="0x00034" name="TX2_TX3_PRBS_SEED_BYTE1"/> 772 <reg32 offset="0x00038" name="TX2_TX3_BIST_PATTERN0"/> 773 <reg32 offset="0x0003C" name="TX2_TX3_BIST_PATTERN1"/> 774 <reg32 offset="0x00040" name="DEBUG_BUS_SEL"/> 775 <reg32 offset="0x00044" name="TXCAL_CFG0"/> 776 <reg32 offset="0x00048" name="TXCAL_CFG1"/> 777 <reg32 offset="0x0004C" name="TX0_TX1_LANE_CTL"/> 778 <reg32 offset="0x00050" name="TX2_TX3_LANE_CTL"/> 779 <reg32 offset="0x00054" name="LANE_BIST_CONFIG"/> 780 <reg32 offset="0x00058" name="CLOCK"/> 781 <reg32 offset="0x0005C" name="MISC1"/> 782 <reg32 offset="0x00060" name="MISC2"/> 783 <reg32 offset="0x00064" name="TX0_TX1_BIST_STATUS0"/> 784 <reg32 offset="0x00068" name="TX0_TX1_BIST_STATUS1"/> 785 <reg32 offset="0x0006C" name="TX0_TX1_BIST_STATUS2"/> 786 <reg32 offset="0x00070" name="TX2_TX3_BIST_STATUS0"/> 787 <reg32 offset="0x00074" name="TX2_TX3_BIST_STATUS1"/> 788 <reg32 offset="0x00078" name="TX2_TX3_BIST_STATUS2"/> 789 <reg32 offset="0x0007C" name="PRE_MISR_STATUS0"/> 790 <reg32 offset="0x00080" name="PRE_MISR_STATUS1"/> 791 <reg32 offset="0x00084" name="PRE_MISR_STATUS2"/> 792 <reg32 offset="0x00088" name="PRE_MISR_STATUS3"/> 793 <reg32 offset="0x0008C" name="POST_MISR_STATUS0"/> 794 <reg32 offset="0x00090" name="POST_MISR_STATUS1"/> 795 <reg32 offset="0x00094" name="POST_MISR_STATUS2"/> 796 <reg32 offset="0x00098" name="POST_MISR_STATUS3"/> 797 <reg32 offset="0x0009C" name="STATUS"/> 798 <reg32 offset="0x000A0" name="MISC3_STATUS"/> 799 <reg32 offset="0x000A4" name="MISC4_STATUS"/> 800 <reg32 offset="0x000A8" name="DEBUG_BUS0"/> 801 <reg32 offset="0x000AC" name="DEBUG_BUS1"/> 802 <reg32 offset="0x000B0" name="DEBUG_BUS2"/> 803 <reg32 offset="0x000B4" name="DEBUG_BUS3"/> 804 <reg32 offset="0x000B8" name="PHY_REVISION_ID0"/> 805 <reg32 offset="0x000BC" name="PHY_REVISION_ID1"/> 806 <reg32 offset="0x000C0" name="PHY_REVISION_ID2"/> 807 <reg32 offset="0x000C4" name="PHY_REVISION_ID3"/> 808</domain> 809 810<domain name="HDMI_PHY_QSERDES_COM" width="32"> 811 <reg32 offset="0x00000" name="ATB_SEL1"/> 812 <reg32 offset="0x00004" name="ATB_SEL2"/> 813 <reg32 offset="0x00008" name="FREQ_UPDATE"/> 814 <reg32 offset="0x0000C" name="BG_TIMER"/> 815 <reg32 offset="0x00010" name="SSC_EN_CENTER"/> 816 <reg32 offset="0x00014" name="SSC_ADJ_PER1"/> 817 <reg32 offset="0x00018" name="SSC_ADJ_PER2"/> 818 <reg32 offset="0x0001C" name="SSC_PER1"/> 819 <reg32 offset="0x00020" name="SSC_PER2"/> 820 <reg32 offset="0x00024" name="SSC_STEP_SIZE1"/> 821 <reg32 offset="0x00028" name="SSC_STEP_SIZE2"/> 822 <reg32 offset="0x0002C" name="POST_DIV"/> 823 <reg32 offset="0x00030" name="POST_DIV_MUX"/> 824 <reg32 offset="0x00034" name="BIAS_EN_CLKBUFLR_EN"/> 825 <reg32 offset="0x00038" name="CLK_ENABLE1"/> 826 <reg32 offset="0x0003C" name="SYS_CLK_CTRL"/> 827 <reg32 offset="0x00040" name="SYSCLK_BUF_ENABLE"/> 828 <reg32 offset="0x00044" name="PLL_EN"/> 829 <reg32 offset="0x00048" name="PLL_IVCO"/> 830 <reg32 offset="0x0004C" name="LOCK_CMP1_MODE0"/> 831 <reg32 offset="0x00050" name="LOCK_CMP2_MODE0"/> 832 <reg32 offset="0x00054" name="LOCK_CMP3_MODE0"/> 833 <reg32 offset="0x00058" name="LOCK_CMP1_MODE1"/> 834 <reg32 offset="0x0005C" name="LOCK_CMP2_MODE1"/> 835 <reg32 offset="0x00060" name="LOCK_CMP3_MODE1"/> 836 <reg32 offset="0x00064" name="LOCK_CMP1_MODE2"/> 837 <reg32 offset="0x00064" name="CMN_RSVD0"/> 838 <reg32 offset="0x00068" name="LOCK_CMP2_MODE2"/> 839 <reg32 offset="0x00068" name="EP_CLOCK_DETECT_CTRL"/> 840 <reg32 offset="0x0006C" name="LOCK_CMP3_MODE2"/> 841 <reg32 offset="0x0006C" name="SYSCLK_DET_COMP_STATUS"/> 842 <reg32 offset="0x00070" name="BG_TRIM"/> 843 <reg32 offset="0x00074" name="CLK_EP_DIV"/> 844 <reg32 offset="0x00078" name="CP_CTRL_MODE0"/> 845 <reg32 offset="0x0007C" name="CP_CTRL_MODE1"/> 846 <reg32 offset="0x00080" name="CP_CTRL_MODE2"/> 847 <reg32 offset="0x00080" name="CMN_RSVD1"/> 848 <reg32 offset="0x00084" name="PLL_RCTRL_MODE0"/> 849 <reg32 offset="0x00088" name="PLL_RCTRL_MODE1"/> 850 <reg32 offset="0x0008C" name="PLL_RCTRL_MODE2"/> 851 <reg32 offset="0x0008C" name="CMN_RSVD2"/> 852 <reg32 offset="0x00090" name="PLL_CCTRL_MODE0"/> 853 <reg32 offset="0x00094" name="PLL_CCTRL_MODE1"/> 854 <reg32 offset="0x00098" name="PLL_CCTRL_MODE2"/> 855 <reg32 offset="0x00098" name="CMN_RSVD3"/> 856 <reg32 offset="0x0009C" name="PLL_CNTRL"/> 857 <reg32 offset="0x000A0" name="PHASE_SEL_CTRL"/> 858 <reg32 offset="0x000A4" name="PHASE_SEL_DC"/> 859 <reg32 offset="0x000A8" name="CORE_CLK_IN_SYNC_SEL"/> 860 <reg32 offset="0x000A8" name="BIAS_EN_CTRL_BY_PSM"/> 861 <reg32 offset="0x000AC" name="SYSCLK_EN_SEL"/> 862 <reg32 offset="0x000B0" name="CML_SYSCLK_SEL"/> 863 <reg32 offset="0x000B4" name="RESETSM_CNTRL"/> 864 <reg32 offset="0x000B8" name="RESETSM_CNTRL2"/> 865 <reg32 offset="0x000BC" name="RESTRIM_CTRL"/> 866 <reg32 offset="0x000C0" name="RESTRIM_CTRL2"/> 867 <reg32 offset="0x000C4" name="RESCODE_DIV_NUM"/> 868 <reg32 offset="0x000C8" name="LOCK_CMP_EN"/> 869 <reg32 offset="0x000CC" name="LOCK_CMP_CFG"/> 870 <reg32 offset="0x000D0" name="DEC_START_MODE0"/> 871 <reg32 offset="0x000D4" name="DEC_START_MODE1"/> 872 <reg32 offset="0x000D8" name="DEC_START_MODE2"/> 873 <reg32 offset="0x000D8" name="VCOCAL_DEADMAN_CTRL"/> 874 <reg32 offset="0x000DC" name="DIV_FRAC_START1_MODE0"/> 875 <reg32 offset="0x000E0" name="DIV_FRAC_START2_MODE0"/> 876 <reg32 offset="0x000E4" name="DIV_FRAC_START3_MODE0"/> 877 <reg32 offset="0x000E8" name="DIV_FRAC_START1_MODE1"/> 878 <reg32 offset="0x000EC" name="DIV_FRAC_START2_MODE1"/> 879 <reg32 offset="0x000F0" name="DIV_FRAC_START3_MODE1"/> 880 <reg32 offset="0x000F4" name="DIV_FRAC_START1_MODE2"/> 881 <reg32 offset="0x000F4" name="VCO_TUNE_MINVAL1"/> 882 <reg32 offset="0x000F8" name="DIV_FRAC_START2_MODE2"/> 883 <reg32 offset="0x000F8" name="VCO_TUNE_MINVAL2"/> 884 <reg32 offset="0x000FC" name="DIV_FRAC_START3_MODE2"/> 885 <reg32 offset="0x000FC" name="CMN_RSVD4"/> 886 <reg32 offset="0x00100" name="INTEGLOOP_INITVAL"/> 887 <reg32 offset="0x00104" name="INTEGLOOP_EN"/> 888 <reg32 offset="0x00108" name="INTEGLOOP_GAIN0_MODE0"/> 889 <reg32 offset="0x0010C" name="INTEGLOOP_GAIN1_MODE0"/> 890 <reg32 offset="0x00110" name="INTEGLOOP_GAIN0_MODE1"/> 891 <reg32 offset="0x00114" name="INTEGLOOP_GAIN1_MODE1"/> 892 <reg32 offset="0x00118" name="INTEGLOOP_GAIN0_MODE2"/> 893 <reg32 offset="0x00118" name="VCO_TUNE_MAXVAL1"/> 894 <reg32 offset="0x0011C" name="INTEGLOOP_GAIN1_MODE2"/> 895 <reg32 offset="0x0011C" name="VCO_TUNE_MAXVAL2"/> 896 <reg32 offset="0x00120" name="RES_TRIM_CONTROL2"/> 897 <reg32 offset="0x00124" name="VCO_TUNE_CTRL"/> 898 <reg32 offset="0x00128" name="VCO_TUNE_MAP"/> 899 <reg32 offset="0x0012C" name="VCO_TUNE1_MODE0"/> 900 <reg32 offset="0x00130" name="VCO_TUNE2_MODE0"/> 901 <reg32 offset="0x00134" name="VCO_TUNE1_MODE1"/> 902 <reg32 offset="0x00138" name="VCO_TUNE2_MODE1"/> 903 <reg32 offset="0x0013C" name="VCO_TUNE1_MODE2"/> 904 <reg32 offset="0x0013C" name="VCO_TUNE_INITVAL1"/> 905 <reg32 offset="0x00140" name="VCO_TUNE2_MODE2"/> 906 <reg32 offset="0x00140" name="VCO_TUNE_INITVAL2"/> 907 <reg32 offset="0x00144" name="VCO_TUNE_TIMER1"/> 908 <reg32 offset="0x00148" name="VCO_TUNE_TIMER2"/> 909 <reg32 offset="0x0014C" name="SAR"/> 910 <reg32 offset="0x00150" name="SAR_CLK"/> 911 <reg32 offset="0x00154" name="SAR_CODE_OUT_STATUS"/> 912 <reg32 offset="0x00158" name="SAR_CODE_READY_STATUS"/> 913 <reg32 offset="0x0015C" name="CMN_STATUS"/> 914 <reg32 offset="0x00160" name="RESET_SM_STATUS"/> 915 <reg32 offset="0x00164" name="RESTRIM_CODE_STATUS"/> 916 <reg32 offset="0x00168" name="PLLCAL_CODE1_STATUS"/> 917 <reg32 offset="0x0016C" name="PLLCAL_CODE2_STATUS"/> 918 <reg32 offset="0x00170" name="BG_CTRL"/> 919 <reg32 offset="0x00174" name="CLK_SELECT"/> 920 <reg32 offset="0x00178" name="HSCLK_SEL"/> 921 <reg32 offset="0x0017C" name="INTEGLOOP_BINCODE_STATUS"/> 922 <reg32 offset="0x00180" name="PLL_ANALOG"/> 923 <reg32 offset="0x00184" name="CORECLK_DIV"/> 924 <reg32 offset="0x00188" name="SW_RESET"/> 925 <reg32 offset="0x0018C" name="CORE_CLK_EN"/> 926 <reg32 offset="0x00190" name="C_READY_STATUS"/> 927 <reg32 offset="0x00194" name="CMN_CONFIG"/> 928 <reg32 offset="0x00198" name="CMN_RATE_OVERRIDE"/> 929 <reg32 offset="0x0019C" name="SVS_MODE_CLK_SEL"/> 930 <reg32 offset="0x001A0" name="DEBUG_BUS0"/> 931 <reg32 offset="0x001A4" name="DEBUG_BUS1"/> 932 <reg32 offset="0x001A8" name="DEBUG_BUS2"/> 933 <reg32 offset="0x001AC" name="DEBUG_BUS3"/> 934 <reg32 offset="0x001B0" name="DEBUG_BUS_SEL"/> 935 <reg32 offset="0x001B4" name="CMN_MISC1"/> 936 <reg32 offset="0x001B8" name="CMN_MISC2"/> 937 <reg32 offset="0x001BC" name="CORECLK_DIV_MODE1"/> 938 <reg32 offset="0x001C0" name="CORECLK_DIV_MODE2"/> 939 <reg32 offset="0x001C4" name="CMN_RSVD5"/> 940</domain> 941 942 943<domain name="HDMI_PHY_QSERDES_TX_LX" width="32"> 944 <reg32 offset="0x00000" name="BIST_MODE_LANENO"/> 945 <reg32 offset="0x00004" name="BIST_INVERT"/> 946 <reg32 offset="0x00008" name="CLKBUF_ENABLE"/> 947 <reg32 offset="0x0000C" name="CMN_CONTROL_ONE"/> 948 <reg32 offset="0x00010" name="CMN_CONTROL_TWO"/> 949 <reg32 offset="0x00014" name="CMN_CONTROL_THREE"/> 950 <reg32 offset="0x00018" name="TX_EMP_POST1_LVL"/> 951 <reg32 offset="0x0001C" name="TX_POST2_EMPH"/> 952 <reg32 offset="0x00020" name="TX_BOOST_LVL_UP_DN"/> 953 <reg32 offset="0x00024" name="HP_PD_ENABLES"/> 954 <reg32 offset="0x00028" name="TX_IDLE_LVL_LARGE_AMP"/> 955 <reg32 offset="0x0002C" name="TX_DRV_LVL"/> 956 <reg32 offset="0x00030" name="TX_DRV_LVL_OFFSET"/> 957 <reg32 offset="0x00034" name="RESET_TSYNC_EN"/> 958 <reg32 offset="0x00038" name="PRE_STALL_LDO_BOOST_EN"/> 959 <reg32 offset="0x0003C" name="TX_BAND"/> 960 <reg32 offset="0x00040" name="SLEW_CNTL"/> 961 <reg32 offset="0x00044" name="INTERFACE_SELECT"/> 962 <reg32 offset="0x00048" name="LPB_EN"/> 963 <reg32 offset="0x0004C" name="RES_CODE_LANE_TX"/> 964 <reg32 offset="0x00050" name="RES_CODE_LANE_RX"/> 965 <reg32 offset="0x00054" name="RES_CODE_LANE_OFFSET"/> 966 <reg32 offset="0x00058" name="PERL_LENGTH1"/> 967 <reg32 offset="0x0005C" name="PERL_LENGTH2"/> 968 <reg32 offset="0x00060" name="SERDES_BYP_EN_OUT"/> 969 <reg32 offset="0x00064" name="DEBUG_BUS_SEL"/> 970 <reg32 offset="0x00068" name="HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN"/> 971 <reg32 offset="0x0006C" name="TX_POL_INV"/> 972 <reg32 offset="0x00070" name="PARRATE_REC_DETECT_IDLE_EN"/> 973 <reg32 offset="0x00074" name="BIST_PATTERN1"/> 974 <reg32 offset="0x00078" name="BIST_PATTERN2"/> 975 <reg32 offset="0x0007C" name="BIST_PATTERN3"/> 976 <reg32 offset="0x00080" name="BIST_PATTERN4"/> 977 <reg32 offset="0x00084" name="BIST_PATTERN5"/> 978 <reg32 offset="0x00088" name="BIST_PATTERN6"/> 979 <reg32 offset="0x0008C" name="BIST_PATTERN7"/> 980 <reg32 offset="0x00090" name="BIST_PATTERN8"/> 981 <reg32 offset="0x00094" name="LANE_MODE"/> 982 <reg32 offset="0x00098" name="IDAC_CAL_LANE_MODE"/> 983 <reg32 offset="0x0009C" name="IDAC_CAL_LANE_MODE_CONFIGURATION"/> 984 <reg32 offset="0x000A0" name="ATB_SEL1"/> 985 <reg32 offset="0x000A4" name="ATB_SEL2"/> 986 <reg32 offset="0x000A8" name="RCV_DETECT_LVL"/> 987 <reg32 offset="0x000AC" name="RCV_DETECT_LVL_2"/> 988 <reg32 offset="0x000B0" name="PRBS_SEED1"/> 989 <reg32 offset="0x000B4" name="PRBS_SEED2"/> 990 <reg32 offset="0x000B8" name="PRBS_SEED3"/> 991 <reg32 offset="0x000BC" name="PRBS_SEED4"/> 992 <reg32 offset="0x000C0" name="RESET_GEN"/> 993 <reg32 offset="0x000C4" name="RESET_GEN_MUXES"/> 994 <reg32 offset="0x000C8" name="TRAN_DRVR_EMP_EN"/> 995 <reg32 offset="0x000CC" name="TX_INTERFACE_MODE"/> 996 <reg32 offset="0x000D0" name="PWM_CTRL"/> 997 <reg32 offset="0x000D4" name="PWM_ENCODED_OR_DATA"/> 998 <reg32 offset="0x000D8" name="PWM_GEAR_1_DIVIDER_BAND2"/> 999 <reg32 offset="0x000DC" name="PWM_GEAR_2_DIVIDER_BAND2"/> 1000 <reg32 offset="0x000E0" name="PWM_GEAR_3_DIVIDER_BAND2"/> 1001 <reg32 offset="0x000E4" name="PWM_GEAR_4_DIVIDER_BAND2"/> 1002 <reg32 offset="0x000E8" name="PWM_GEAR_1_DIVIDER_BAND0_1"/> 1003 <reg32 offset="0x000EC" name="PWM_GEAR_2_DIVIDER_BAND0_1"/> 1004 <reg32 offset="0x000F0" name="PWM_GEAR_3_DIVIDER_BAND0_1"/> 1005 <reg32 offset="0x000F4" name="PWM_GEAR_4_DIVIDER_BAND0_1"/> 1006 <reg32 offset="0x000F8" name="VMODE_CTRL1"/> 1007 <reg32 offset="0x000FC" name="VMODE_CTRL2"/> 1008 <reg32 offset="0x00100" name="TX_ALOG_INTF_OBSV_CNTL"/> 1009 <reg32 offset="0x00104" name="BIST_STATUS"/> 1010 <reg32 offset="0x00108" name="BIST_ERROR_COUNT1"/> 1011 <reg32 offset="0x0010C" name="BIST_ERROR_COUNT2"/> 1012 <reg32 offset="0x00110" name="TX_ALOG_INTF_OBSV"/> 1013</domain> 1014 1015<domain name="HDMI_8998_PHY" width="32"> 1016 <reg32 offset="0x00000" name="CFG"/> 1017 <reg32 offset="0x00004" name="PD_CTL"/> 1018 <reg32 offset="0x00010" name="MODE"/> 1019 <reg32 offset="0x0005C" name="CLOCK"/> 1020 <reg32 offset="0x00068" name="CMN_CTRL"/> 1021 <reg32 offset="0x000B4" name="STATUS"/> 1022</domain> 1023 1024<domain name="HDMI_8998_PHY_QSERDES_COM" width="32"> 1025 <reg32 offset="0x0000" name="ATB_SEL1"/> 1026 <reg32 offset="0x0004" name="ATB_SEL2"/> 1027 <reg32 offset="0x0008" name="FREQ_UPDATE"/> 1028 <reg32 offset="0x000C" name="BG_TIMER"/> 1029 <reg32 offset="0x0010" name="SSC_EN_CENTER"/> 1030 <reg32 offset="0x0014" name="SSC_ADJ_PER1"/> 1031 <reg32 offset="0x0018" name="SSC_ADJ_PER2"/> 1032 <reg32 offset="0x001C" name="SSC_PER1"/> 1033 <reg32 offset="0x0020" name="SSC_PER2"/> 1034 <reg32 offset="0x0024" name="SSC_STEP_SIZE1"/> 1035 <reg32 offset="0x0028" name="SSC_STEP_SIZE2"/> 1036 <reg32 offset="0x002C" name="POST_DIV"/> 1037 <reg32 offset="0x0030" name="POST_DIV_MUX"/> 1038 <reg32 offset="0x0034" name="BIAS_EN_CLKBUFLR_EN"/> 1039 <reg32 offset="0x0038" name="CLK_ENABLE1"/> 1040 <reg32 offset="0x003C" name="SYS_CLK_CTRL"/> 1041 <reg32 offset="0x0040" name="SYSCLK_BUF_ENABLE"/> 1042 <reg32 offset="0x0044" name="PLL_EN"/> 1043 <reg32 offset="0x0048" name="PLL_IVCO"/> 1044 <reg32 offset="0x004C" name="CMN_IETRIM"/> 1045 <reg32 offset="0x0050" name="CMN_IPTRIM"/> 1046 <reg32 offset="0x0060" name="CP_CTRL_MODE0"/> 1047 <reg32 offset="0x0064" name="CP_CTRL_MODE1"/> 1048 <reg32 offset="0x0068" name="PLL_RCTRL_MODE0"/> 1049 <reg32 offset="0x006C" name="PLL_RCTRL_MODE1"/> 1050 <reg32 offset="0x0070" name="PLL_CCTRL_MODE0"/> 1051 <reg32 offset="0x0074" name="PLL_CCTRL_MODE1"/> 1052 <reg32 offset="0x0078" name="PLL_CNTRL"/> 1053 <reg32 offset="0x007C" name="BIAS_EN_CTRL_BY_PSM"/> 1054 <reg32 offset="0x0080" name="SYSCLK_EN_SEL"/> 1055 <reg32 offset="0x0084" name="CML_SYSCLK_SEL"/> 1056 <reg32 offset="0x0088" name="RESETSM_CNTRL"/> 1057 <reg32 offset="0x008C" name="RESETSM_CNTRL2"/> 1058 <reg32 offset="0x0090" name="LOCK_CMP_EN"/> 1059 <reg32 offset="0x0094" name="LOCK_CMP_CFG"/> 1060 <reg32 offset="0x0098" name="LOCK_CMP1_MODE0"/> 1061 <reg32 offset="0x009C" name="LOCK_CMP2_MODE0"/> 1062 <reg32 offset="0x00A0" name="LOCK_CMP3_MODE0"/> 1063 <reg32 offset="0x00B0" name="DEC_START_MODE0"/> 1064 <reg32 offset="0x00B4" name="DEC_START_MODE1"/> 1065 <reg32 offset="0x00B8" name="DIV_FRAC_START1_MODE0"/> 1066 <reg32 offset="0x00BC" name="DIV_FRAC_START2_MODE0"/> 1067 <reg32 offset="0x00C0" name="DIV_FRAC_START3_MODE0"/> 1068 <reg32 offset="0x00C4" name="DIV_FRAC_START1_MODE1"/> 1069 <reg32 offset="0x00C8" name="DIV_FRAC_START2_MODE1"/> 1070 <reg32 offset="0x00CC" name="DIV_FRAC_START3_MODE1"/> 1071 <reg32 offset="0x00D0" name="INTEGLOOP_INITVAL"/> 1072 <reg32 offset="0x00D4" name="INTEGLOOP_EN"/> 1073 <reg32 offset="0x00D8" name="INTEGLOOP_GAIN0_MODE0"/> 1074 <reg32 offset="0x00DC" name="INTEGLOOP_GAIN1_MODE0"/> 1075 <reg32 offset="0x00E0" name="INTEGLOOP_GAIN0_MODE1"/> 1076 <reg32 offset="0x00E4" name="INTEGLOOP_GAIN1_MODE1"/> 1077 <reg32 offset="0x00E8" name="VCOCAL_DEADMAN_CTRL"/> 1078 <reg32 offset="0x00EC" name="VCO_TUNE_CTRL"/> 1079 <reg32 offset="0x00F0" name="VCO_TUNE_MAP"/> 1080 <reg32 offset="0x0124" name="CMN_STATUS"/> 1081 <reg32 offset="0x0128" name="RESET_SM_STATUS"/> 1082 <reg32 offset="0x0138" name="CLK_SEL"/> 1083 <reg32 offset="0x013C" name="HSCLK_SEL"/> 1084 <reg32 offset="0x0148" name="CORECLK_DIV_MODE0"/> 1085 <reg32 offset="0x0150" name="SW_RESET"/> 1086 <reg32 offset="0x0154" name="CORE_CLK_EN"/> 1087 <reg32 offset="0x0158" name="C_READY_STATUS"/> 1088 <reg32 offset="0x015C" name="CMN_CONFIG"/> 1089 <reg32 offset="0x0164" name="SVS_MODE_CLK_SEL"/> 1090</domain> 1091 1092<domain name="HDMI_8998_PHY_TXn" width="32"> 1093 <reg32 offset="0x0000" name="EMP_POST1_LVL"/> 1094 <reg32 offset="0x0008" name="INTERFACE_SELECT_TX_BAND"/> 1095 <reg32 offset="0x000C" name="CLKBUF_TERM_ENABLE"/> 1096 <reg32 offset="0x0014" name="DRV_LVL_RES_CODE_OFFSET"/> 1097 <reg32 offset="0x0018" name="DRV_LVL"/> 1098 <reg32 offset="0x001C" name="LANE_CONFIG"/> 1099 <reg32 offset="0x0024" name="PRE_DRIVER_1"/> 1100 <reg32 offset="0x0028" name="PRE_DRIVER_2"/> 1101 <reg32 offset="0x002C" name="LANE_MODE"/> 1102</domain> 1103 1104</database> 1105