xref: /linux/drivers/gpu/drm/msm/registers/adreno/a8xx_perfcntrs.xml (revision 637315cb400eed1dbe721954fea437a61a2d65b2)
1*9f860dbfSRob Clark<?xml version="1.0" encoding="UTF-8"?>
2*9f860dbfSRob Clark<database xmlns="http://nouveau.freedesktop.org/"
3*9f860dbfSRob Clarkxmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4*9f860dbfSRob Clarkxsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd">
5*9f860dbfSRob Clark<import file="freedreno_copyright.xml"/>
6*9f860dbfSRob Clark<import file="adreno/adreno_common.xml"/>
7*9f860dbfSRob Clark<import file="adreno/adreno_pm4.xml"/>
8*9f860dbfSRob Clark
9*9f860dbfSRob Clark<enum name="a8xx_cp_perfcounter_select">
10*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_CP_NEVER_COUNT"/>
11*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_CP_ALWAYS_COUNT"/>
12*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_CP_BUSY_GFX_CORE_IDLE"/>
13*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_CP_BUSY_CYCLES"/>
14*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_CP_NUM_PREEMPTIONS"/>
15*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_CP_PREEMPTION_REACTION_DELAY"/>
16*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
17*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
18*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
19*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_CP_PREDICATED_DRAWS_KILLED"/>
20*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_CP_MODE_SWITCH"/>
21*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_CP_ZPASS_DONE"/>
22*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_CP_CONTEXT_DONE"/>
23*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_CP_CACHE_FLUSH"/>
24*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_CP_LONG_PREEMPTIONS"/>
25*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_CP_SQE_I_CACHE_STARVE"/>
26*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_CP_SQE_IDLE"/>
27*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_CP_SQE_PM4_STARVE_RB"/>
28*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB1"/>
29*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB2"/>
30*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_CP_SQE_PM4_STARVE_IB3"/>
31*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_CP_SQE_PM4_STARVE_FSDT"/>
32*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_CP_SQE_PM4_STARVE_SDS"/>
33*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_CP_SQE_MRB_STARVE"/>
34*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_CP_SQE_RRB_STARVE"/>
35*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_CP_SQE_VSD_STARVE"/>
36*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_CP_VSD_DECODE_STARVE"/>
37*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_CP_SQE_PIPE_OUT_STALL"/>
38*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_CP_SQE_SYNC_STALL"/>
39*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_CP_SQE_PM4_WFI_STALL"/>
40*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_CP_SQE_SYS_WFI_STALL"/>
41*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_CP_WAIT_ON_OTHER_PIPE"/>
42*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_CP_OUTPUT_BLOCKED"/>
43*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_CP_SQE_T4_EXEC"/>
44*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_CP_SQE_LOAD_STATE_EXEC"/>
45*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_CP_SQE_SAVE_SDS_STATE"/>
46*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_CP_SQE_DRAW_EXEC"/>
47*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
48*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_CP_SQE_EXEC_PROFILED"/>
49*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_CP_MEMORY_POOL_EMPTY"/>
50*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_CP_MEMORY_POOL_SYNC_STALL"/>
51*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
52*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_CP_MEMORY_POOL_BELOW_THRESH"/>
53*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
54*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_CP_AHB_STALL_SQE_GMU"/>
55*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
56*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
57*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_CP_CLUSTER_FE_U_EMPTY"/>
58*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_CP_CLUSTER_FE_S_EMPTY"/>
59*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_CP_CLUSTER_SP_VS_EMPTY"/>
60*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_CP_CLUSTER_VPC_US_EMPTY"/>
61*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_CP_CLUSTER_VPC_VS_EMPTY"/>
62*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_CP_CLUSTER_GRAS_EMPTY"/>
63*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_CP_CLUSTER_SP_PS_EMPTY"/>
64*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_CP_CLUSTER_VPC_PS_EMPTY"/>
65*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_CP_CLUSTER_PS_EMPTY"/>
66*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_CP_PM4_DATA"/>
67*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_CP_PM4_HEADERS"/>
68*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_CP_VBIF_READ_BEATS"/>
69*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_CP_VBIF_WRITE_BEATS"/>
70*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_CP_SQE_INSTR_COUNTER"/>
71*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_CP_CLUSTER_FE_US_FULL"/>
72*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_CP_CLUSTER_FE_S_FULL"/>
73*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_CP_CLUSTER_SP_VS_FULL"/>
74*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_CP_CLUSTER_VPC_US_FULL"/>
75*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_CP_CLUSTER_VPC_VS_FULL"/>
76*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_CP_CLUSTER_GRAS_FULL"/>
77*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_CP_CLUSTER_SP_PS_FULL"/>
78*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_CP_CLUSTER_VPC_PS_FULL"/>
79*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_CP_CLUSTER_PS_FULL"/>
80*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_CP_ICACHE_MISSES"/>
81*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_CP_ICACHE_HITS"/>
82*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_CP_ICACHE_STALL"/>
83*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_CP_DCACHE_MISSES"/>
84*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_CP_DCACHE_HITS"/>
85*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_CP_DCACHE_STALLS"/>
86*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_CP_AQE_SQE_STALL"/>
87*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_CP_SQE_AQE_STARVE"/>
88*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_CP_ISR_CYCLES"/>
89*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_CP_SQE_MD8_STALL_CYCLES"/>
90*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_CP_SQE_MESH_EXEC_CYCLES"/>
91*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_CP_AQE_NUM_AS_CHUNKS"/>
92*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_CP_AQE_NUM_MS_CHUNKS"/>
93*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_CP_S_SKEW_BUFFER_FULL"/>
94*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_CP_S_SKEW_BUFFER_ABOVE_THRESH"/>
95*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_CP_ECACHE_HITS"/>
96*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_CP_ECACHE_KILLS"/>
97*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_CP_ECACHE_REQS"/>
98*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_CP_ECACHE_EVEN_REQS"/>
99*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_CP_ECACHE_STALLS_RAP"/>
100*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_CP_ECACHE_BUSY"/>
101*9f860dbfSRob Clark</enum>
102*9f860dbfSRob Clark
103*9f860dbfSRob Clark<enum name="a8xx_rbbm_perfcounter_select">
104*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_RBBM_NEVER_COUNT"/>
105*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_RBBM_US_ALWAYS_COUNT"/>
106*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_RBBM_US_ALWAYS_ON"/>
107*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_RBBM_US_STATUS_MASKED"/>
108*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_RBBM_US_PC_BUSY"/>
109*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_RBBM_US_COM_BUSY"/>
110*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_RBBM_US_DCOM_BUSY"/>
111*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_RBBM_US_VBIF_BUSY"/>
112*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_RBBM_US_VSC_BUSY"/>
113*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_RBBM_US_UCHE_BUSY"/>
114*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_RBBM_US_HLSQ_BUSY"/>
115*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_RBBM_S_HLSQ_BUSY"/>
116*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_RBBM_S_PC_BUSY"/>
117*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_RBBM_S_TESS_BUSY"/>
118*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_RBBM_S_TSEFE_BUSY"/>
119*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_RBBM_S_TSEBE_BUSY"/>
120*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_RBBM_S_RAS_BUSY"/>
121*9f860dbfSRob Clark</enum>
122*9f860dbfSRob Clark
123*9f860dbfSRob Clark<enum name="a8xx_pc_perfcounter_select">
124*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_PC_NEVER_COUNT"/>
125*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_PC_US_BUSY_CYCLES"/>
126*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_PC_US_WORKING_CYCLES"/>
127*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_PC_US_UCHE_OUTSTANDING_TRANS"/>
128*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_PC_US_PASS1_TF_STALL_CYCLES"/>
129*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_PC_US_STARVE_CYCLES_FOR_INDEX"/>
130*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_PC_US_STARVE_CYCLES_FOR_TF"/>
131*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_PC_US_STARVE_CYCLES_FOR_VIZ_STREAM"/>
132*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_PC_US_STARVE_CYCLES_DI"/>
133*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_PC_US_VIS_STREAMS_LOADED"/>
134*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_PC_US_INSTANCES"/>
135*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_PC_US_DEAD_PRIM"/>
136*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_PC_US_SLICE_LIVE_PRIM"/>
137*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_PC_US_3D_DRAWCALLS"/>
138*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_PC_US_2D_DRAWCALLS"/>
139*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_PC_US_NON_DRAWCALL_GLOBAL_EVENTS"/>
140*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_PC_US_MESH_DRAWS"/>
141*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_PC_US_MESH_DEAD_DRAWS"/>
142*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_PC_US_MESH_MVIS_EN_DRAWS"/>
143*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_PC_US_MESH_DEAD_PRIM"/>
144*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_PC_US_MESH_LIVE_PRIM"/>
145*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_PC_US_MESH_PA_EN_PRIM"/>
146*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_PC_US_STARVE_CYCLES_FOR_MVIS_STREAM"/>
147*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_PC_US_STARVE_CYCLES_PREDRAW"/>
148*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_PC_US_STALL_CYCLES_COMPUTE_GFX"/>
149*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_PC_US_STALL_CYCLES_GFX_COMPUTE"/>
150*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_PC_US_PREDRAW_STALLS"/>
151*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_PC_US_DP0_INPUT_STALLS"/>
152*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_PC_US_DP1_INPUT_STALLS"/>
153*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_PC_US_BR_STALLS_BV_WORKLOAD"/>
154*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_PC_US_BV_STALLS_BR_WORKLOAD"/>
155*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_PC_US_PASSPAIR_STALL"/>
156*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_PC_US_STALL_CYCLES_UCHE0"/>
157*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_PC_US_STALL_CYCLES_UCHE1"/>
158*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_PC_US_UCHE_0_TRANS"/>
159*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_PC_US_UCHE_1_TRANS"/>
160*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_PC_US_BV_STALLED_BY_ATTR"/>
161*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_PC_US_BV_STARVED_BY_RARB"/>
162*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BR"/>
163*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_PC_US_VPC_PRIM_COUNT_STALLS_BV"/>
164*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_PC_US_BV_STALLED_BY_UCHE_FEEDBACK"/>
165*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_PC_US_VSD_RARB_DVIZ_FULL"/>
166*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_PC_US_VSD_RARB_PVIZ_FULL"/>
167*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_PC_US_VSD_RARB_TVIZ_FULL"/>
168*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_PC_US_DP0_RARB_FULL"/>
169*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_PC_US_DP1_RARB_FULL"/>
170*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_PC_US_DP0_LIVE_PRIM"/>
171*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_PC_US_DP1_LIVE_PRIM"/>
172*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_PC_US_BV2BR_SWITCH"/>
173*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_PC_US_BR2BV_SWITCH"/>
174*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_PC_US_STALL_CYCLES_PC_S"/>
175*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_PC_RESERVED_51"/>
176*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_PC_RESERVED_52"/>
177*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_PC_RESERVED_53"/>
178*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_PC_RESERVED_54"/>
179*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_PC_RESERVED_55"/>
180*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_PC_RESERVED_56"/>
181*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_PC_RESERVED_57"/>
182*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_PC_RESERVED_58"/>
183*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_PC_RESERVED_59"/>
184*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_PC_S_BUSY_CYCLES"/>
185*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_PC_S_WORKING_CYCLES"/>
186*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_PC_S_STALL_CYCLES_VFD"/>
187*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_PC_S_STALL_CYCLES_VPC_FE"/>
188*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_PC_S_STALL_CYCLES_TESS"/>
189*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_PC_S_STALL_CYCLES_VFD_ONLY"/>
190*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_PC_S_STALL_CYCLES_VPC_ONLY"/>
191*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_PC_S_VPC_PRIMITIVES"/>
192*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_PC_S_VERTEX_HITS"/>
193*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_PC_S_IA_VERTICES"/>
194*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_PC_S_IA_PRIMITIVES"/>
195*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_PC_S_HS_INVOCATIONS"/>
196*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_PC_S_DS_INVOCATIONS"/>
197*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_PC_S_VS_INVOCATIONS"/>
198*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_PC_S_GS_INVOCATIONS"/>
199*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_PC_S_DS_PRIMITIVES"/>
200*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_PC_S_TESS_BUSY_CYCLES"/>
201*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_PC_S_TESS_WORKING_CYCLES"/>
202*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_PC_S_TESS_STALL_CYCLES_PC"/>
203*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_PC_S_TESS_STARVE_CYCLES_PC"/>
204*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_PC_S_TESS_SETUP_ACTIVE"/>
205*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_PC_S_TESS_PID_ACTIVE"/>
206*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_PC_S_TESS_PRIM_GEN_ACTIVE"/>
207*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_PC_S_TESS_FACTOR_TRANS"/>
208*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_PC_S_TESS_PC_UV_TRANS"/>
209*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_PC_S_TESS_PC_UV_PATCHES"/>
210*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_PC_S_MESH_VS_WAVES"/>
211*9f860dbfSRob Clark</enum>
212*9f860dbfSRob Clark
213*9f860dbfSRob Clark<enum name="a8xx_vfd_perfcounter_select">
214*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_VFD_NEVER_COUNT"/>
215*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_VFD_BUSY_CYCLES"/>
216*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_VFD_STALL_CYCLES_UCHE"/>
217*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
218*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_VFD_STALL_CYCLES_SP_INFO"/>
219*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_VFD_STALL_CYCLES_SP_ATTR"/>
220*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_VFD_STARVE_CYCLES_UCHE"/>
221*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_VFD_RBUFFER_FULL"/>
222*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_VFD_ATTR_INFO_FIFO_FULL"/>
223*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
224*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_VFD_NUM_ATTRIBUTES"/>
225*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_VFD_UPPER_SHADER_FIBERS"/>
226*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_VFD_LOWER_SHADER_FIBERS"/>
227*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_VFD_MODE_0_FIBERS"/>
228*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_VFD_MODE_1_FIBERS"/>
229*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_VFD_MODE_2_FIBERS"/>
230*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_VFD_MODE_3_FIBERS"/>
231*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_VFD_MODE_4_FIBERS"/>
232*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_VFD_TOTAL_VERTICES"/>
233*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_VFDP_STALL_CYCLES_VFD"/>
234*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
235*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
236*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_VFDP_STARVE_CYCLES_PC"/>
237*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_VFDP_VS_STAGE_WAVES"/>
238*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_VFD_STALL_CYCLES_PRG_END_FE"/>
239*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_VFD_STALL_CYCLES_CBSYNC"/>
240*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_VFD_BOTTLENECK_CYCLES"/>
241*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_VFD_WORKING_CYCLES"/>
242*9f860dbfSRob Clark</enum>
243*9f860dbfSRob Clark
244*9f860dbfSRob Clark<enum name="a8xx_hlsq_perfcounter_select">
245*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_HLSQ_NEVER_COUNT"/>
246*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_HLSQ_BUSY_CYCLES"/>
247*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
248*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
249*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
250*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_HLSQ_UCHE_LATENCY_COUNT"/>
251*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_HLSQ_STALL_CYCLES_UCHE"/>
252*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_HLSQ_RESERVED_7"/>
253*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_HLSQ_RESERVED_8"/>
254*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_HLSQ_RESERVED_9"/>
255*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_HLSQ_COMPUTE_DRAWCALLS"/>
256*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
257*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
258*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
259*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
260*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
261*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
262*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
263*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_HLSQ_STALL_CYCLES_VPC_BE"/>
264*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_HLSQ_RESERVED_19"/>
265*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_HLSQ_RESERVED_20"/>
266*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_HLSQ_VSBR_STALL_CYCLES"/>
267*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_HLSQ_FS_STALL_CYCLES"/>
268*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_HLSQ_LPAC_STALL_CYCLES"/>
269*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_HLSQ_BV_STALL_CYCLES"/>
270*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_HLSQ_VSBR_DEREF_CYCLES"/>
271*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_HLSQ_FS_DEREF_CYCLES"/>
272*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_HLSQ_LPAC_DEREF_CYCLES"/>
273*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_HLSQ_BV_DEREF_CYCLES"/>
274*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_HLSQ_VSBR_S2W_CYCLES"/>
275*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_HLSQ_FS_S2W_CYCLES"/>
276*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_HLSQ_LPAC_S2W_CYCLES"/>
277*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_HLSQ_BV_S2W_CYCLES"/>
278*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_HLSQ_VSBR_WAIT_FS_S2W"/>
279*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_HLSQ_FS_WAIT_VS_S2W"/>
280*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_HLSQ_LPAC_WAIT_VS_S2W"/>
281*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_HLSQ_BV_WAIT_FS_S2W"/>
282*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_HLSQ_RESERVED_37"/>
283*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_HLSQ_FS_WAIT_SAME_VS_S2W"/>
284*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_HLSQ_FS_STARVING_SP"/>
285*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_HLSQ_VS_DATA_WAIT_PROGRAMMING"/>
286*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_HLSQ_BV_DATA_WAIT_PROGRAMMING"/>
287*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_VS"/>
288*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_VS"/>
289*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_FS"/>
290*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_FS"/>
291*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_BV"/>
292*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_BV"/>
293*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXTS_LPAC"/>
294*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_HLSQ_STPROC_WAVE_CONTEXT_CYCLES_LPAC"/>
295*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_VS"/>
296*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_FS"/>
297*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_BV"/>
298*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_HLSQ_SPTROC_STCHE_WARMUP_INC_LPAC"/>
299*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_VS"/>
300*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_FS"/>
301*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_BV"/>
302*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_HLSQ_SPTROC_STCHE_MISS_INC_LPAC"/>
303*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_HLSQ_VSBR_S2W_CYCLES_SP"/>
304*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_HLSQ_FS_S2W_CYCLES_SP"/>
305*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_HLSQ_LPAC_S2W_CYCLES_SP"/>
306*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_HLSQ_BV_S2W_CYCLES_SP"/>
307*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_HLSQ_L2STC_REQ_HLSQ"/>
308*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_HLSQ_L2STC_REQ_HLSQ_HIT"/>
309*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_HLSQ_L2STC_REQ_SP"/>
310*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_HLSQ_L2STC_REQ_SP_HIT"/>
311*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ"/>
312*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_HLSQ_L2STC_REQ_INS_HLSQ_HIT"/>
313*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_HLSQ_L2STC_REQ_INS_SP"/>
314*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_HLSQ_L2STC_REQ_INS_SP_HIT"/>
315*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_HLSQ_L2STC_REQ_UCHE"/>
316*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_HLSQ_L2STC_LATENCY_CYCLES"/>
317*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_HLSQ_L2STC_LATENCY_COUNT"/>
318*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_HLSQ_L2STC_STALL_SP_MISS_REQ"/>
319*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_HLSQ_L2STC_BANK0_REPLACEMENT"/>
320*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_HLSQ_L2STC_BANK1_REPLACEMENT"/>
321*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_HLSQ_L2STC_BANK2_REPLACEMENT"/>
322*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_HLSQ_L2STC_BANK3_REPLACEMENT"/>
323*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_HLSQ_S2W_STALL_BY_MISS_RETURN"/>
324*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_HLSQ_MISS_RETURN_STALL_BY_S2W"/>
325*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_HLSQ_STPROC_L0_STALL_INS_RD"/>
326*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_HLSQ_STPROC_L0_INS_MISS"/>
327*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_HLSQ_STPROC_L0_INS_HIT"/>
328*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_COUNT"/>
329*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_HLSQ_STPROC_L0_INS_LATENCY_CYCLE"/>
330*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_HLSQ_STPROC_DPS_RUN_COUNT"/>
331*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_HLSQ_STPROC_DPS_RUN_CYCLE"/>
332*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_HLSQ_VSDP_BR_QUERY_REQ"/>
333*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_HLSQ_VSDP_BV_QUERY_REQ"/>
334*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_HLSQ_VSDP_BR_QUERY_REQ_WHEN_BV_PENDING"/>
335*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_HLSQ_VSDP_BR_QUERY_BUSY"/>
336*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_HLSQ_VSDP_BV_QUERY_BUSY"/>
337*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_HLSQ_VSDP_BR_QUERY_FAIL"/>
338*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_HLSQ_VSDP_BV_QUERY_FAIL"/>
339*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_HLSQ_VS_CTXT_BUF_FULL_BLOCK_CPI"/>
340*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_HLSQ_FS_CTXT_BUF_FULL_BLOCK_CPI"/>
341*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_HLSQ_BV_CTXT_BUF_FULL_BLOCK_CPI"/>
342*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_HLSQ_VS_CONST_BUF_FULL_BLOCK_CPI"/>
343*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_HLSQ_FS_CONST_BUF_FULL_BLOCK_CPI"/>
344*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_HLSQ_BV_CONST_BUF_FULL_BLOCK_CPI"/>
345*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_HLSQ_VS_INS_BUF_FULL_BLOCK_CPI"/>
346*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_HLSQ_FS_INS_BUF_FULL_BLOCK_CPI"/>
347*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_HLSQ_BV_INS_BUF_FULL_BLOCK_CPI"/>
348*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_HLSQ_VS_DES_BUF_FULL_BLOCK_CPI"/>
349*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_HLSQ_FS_DES_BUF_FULL_BLOCK_CPI"/>
350*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_HLSQ_BV_DES_BUF_FULL_BLOCK_CPI"/>
351*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_HLSQ_PRIMITIVE_COUNT"/>
352*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_HLSQ_LPAC2BV_SWITCH_CNT"/>
353*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_HLSQ_BV2LPAC_SWITCH_CNT"/>
354*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_HLSQ_LPAC2BV_SWITCH_CYC"/>
355*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_HLSQ_BV2LPAC_SWITCH_CYC"/>
356*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_HLSQ_VSDP_BV2BR_SWITCH_CYC"/>
357*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_HLSQ_VS_SP_HCTX_ACTIVE_CNT"/>
358*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_HLSQ_FS_SP_HCTX_ACTIVE_CNT"/>
359*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_HLSQ_BV_SP_HCTX_ACTIVE_CNT"/>
360*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_HLSQ_VS_SP_HCTX_ACTIVE_CYC"/>
361*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_HLSQ_FS_SP_HCTX_ACTIVE_CYC"/>
362*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_HLSQ_BV_SP_HCTX_ACTIVE_CYC"/>
363*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_HLSQ_VS_SP_CCTX_ACTIVE_CNT"/>
364*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_HLSQ_FS_SP_CCTX_ACTIVE_CNT"/>
365*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_HLSQ_BV_SP_CCTX_ACTIVE_CNT"/>
366*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_HLSQ_VS_SP_SCTX_ACTIVE_CNT"/>
367*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_HLSQ_FS_SP_SCTX_ACTIVE_CNT"/>
368*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_HLSQ_BV_SP_SCTX_ACTIVE_CNT"/>
369*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_HLSQ_VS_SP_CTX_ALIVE_CYCLE"/>
370*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_HLSQ_FS_SP_CTX_ALIVE_CYCLE"/>
371*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_HLSQ_BV_SP_CTX_ALIVE_CYCLE"/>
372*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_HLSQ_STPROC_WAVE_NUM_FS"/>
373*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_HLSQ_STPROC_WAVE_NUM_VS"/>
374*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_HLSQ_STPROC_WAVE_NUM_BV"/>
375*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_HLSQ_STPROC_WAVE_NUM_LPAC"/>
376*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_HLSQ_VS_SP_CCTX_NUM"/>
377*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_HLSQ_FS_SP_CCTX_NUM"/>
378*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_HLSQ_BV_SP_CCTX_NUM"/>
379*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_HLSQ_VS_SP_SCTX_NUM"/>
380*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_HLSQ_FS_SP_SCTX_NUM"/>
381*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_HLSQ_BV_SP_SCTX_NUM"/>
382*9f860dbfSRob Clark</enum>
383*9f860dbfSRob Clark
384*9f860dbfSRob Clark<enum name="a8xx_vpc_perfcounter_select">
385*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_VPC_NEVER_COUNT"/>
386*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_VPC_FE_BUSY_CYCLES"/>
387*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_VPC_FE_WORKING_CYCLES"/>
388*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_VPC_FE_STALL_CYCLES_VFD_WACK"/>
389*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_VPC_FE_STARVE_CYCLES_SP"/>
390*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_VPC_FE_PC_PRIMITIVES"/>
391*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_VPC_FE_SP_COMPONENTS"/>
392*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_VPC_FE_STALL_CYCLES_VPCRAM_POS"/>
393*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_VPC_FE_VS_BUSY_CYCLES"/>
394*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_VPC_FE_VS_WORKING_CYCLES"/>
395*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_VPC_FE_NUM_VPCRAM_READ_POS"/>
396*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_VPC_FE_WIT_FULL_CYCLES"/>
397*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_VPC_FE_VPCRAM_FULL_CYCLES"/>
398*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_VPC_FE_NUM_VPCRAM_WRITE"/>
399*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_VPC_FE_STALL_CYCLES_TSE_FE"/>
400*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_VPC_FE_STALL_CYCLES_VPC_US"/>
401*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_VPC_FE_TSE_FE_PRIMITIVES"/>
402*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_VPC_FE_GS_PRIMITIVES"/>
403*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_VPC_FE_TSE_FE_TRANSACTIONS"/>
404*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_VPC_FE_STALL_CYCLES_CCU"/>
405*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_VPC_FE_NUM_WM_HIT"/>
406*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_VPC_FE_STALL_DQ_WACK"/>
407*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_FE"/>
408*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_VPC_FE_STALL_CYCLES_PRG_END_VPCVS"/>
409*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_VPC_FE_POSRAM_FULL_CYCLES"/>
410*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_VPC_FE_GMEM_NOP_FULL_CYCLES"/>
411*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_VPC_FE_GMEM_POS_FULL_CYCLES"/>
412*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_VPC_FE_BOTTLENECK"/>
413*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_VPC_US_BUSY_CYCLES"/>
414*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_VPC_US_WORKING_CYCLES"/>
415*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_VPC_US_STARVE_CYCLES_TSE_FE"/>
416*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_VPC_US_PTUS_FULL"/>
417*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_VPC_US_COMP_INVIS_PRIM_COUNT"/>
418*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_VPC_US_STALL_CYCLES_VSC"/>
419*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_VPC_US_STALL_CYCLES_VPC_BE"/>
420*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_VPC_US_STALL_CYCLES_UCHE"/>
421*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_VPC_US_STREAMOUT_TRANSACTION"/>
422*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_VPC_US_NUM_GMEM_READ_SO"/>
423*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_VPC_US_STARVE_CYCLES_UCHE_RD"/>
424*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_VPC_US_STALL_CYCLES_PRG_END_VPCUS"/>
425*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_VPC_US_STARVE_CYCLES_REORDER"/>
426*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_VPC_US_BOTTLENECK"/>
427*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_VPC_RESERVED_42"/>
428*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_VPC_RESERVED_43"/>
429*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_VPC_RESERVED_44"/>
430*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_VPC_BE_BUSY_CYCLES"/>
431*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_VPC_BE_WORKING_CYCLES"/>
432*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_VPC_BE_STALL_CYCLES_TSE_BE"/>
433*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_VPC_BE_TSE_BE_PRIMITIVES"/>
434*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_VPC_BE_TSE_BE_TRANSACTIONS"/>
435*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_VPC_BE_STARVE_CYCLES_LRZ"/>
436*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_VPC_BE_LRZ_ASSIGN_PRIMITIVES"/>
437*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_VPC_BE_RB_VISIBLE_PRIMITIVES"/>
438*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_VPC_BE_STARVE_CYCLES_RB"/>
439*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_VPC_BE_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
440*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_VPC_BE_STALL_CYCLES_SP_LM"/>
441*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_VPC_BE_NUM_PA_REQ"/>
442*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_VPC_BE_NUM_LM_REQ_HIT"/>
443*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_VPC_BE_NUM_ATTR_REQ_LM"/>
444*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_VPC_BE_LM_TRANSACTION"/>
445*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_VPC_BE_PS_BUSY_CYCLES"/>
446*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_VPC_BE_PS_WORKING_CYCLES"/>
447*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_VPC_BE_STALL_CYCLES_CCHE"/>
448*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_VPC_BE_STARVE_CYCLES_CCHE"/>
449*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_VPC_BE_LM_FULL_WAIT_FOR_INTP_END"/>
450*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_VPC_BE_CCHE_REQBUF_FULL"/>
451*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_VPC_BE_CCHE_NUM_POS_REQ"/>
452*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_VPC_BE_STALL_CYCLES_LM_ACK"/>
453*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_VPC_BE_STALL_CYCLES_PRG_END_VPCPS"/>
454*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_VPC_BE_POS_OVERFETCH_ATTR"/>
455*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_VPC_BE_BOTTLENECK"/>
456*9f860dbfSRob Clark</enum>
457*9f860dbfSRob Clark
458*9f860dbfSRob Clark<enum name="a8xx_tse_perfcounter_select">
459*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_TSE_NEVER_COUNT"/>
460*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_TSE_BE_BUSY_CYCLES"/>
461*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_TSE_BE_CLIPPING_CYCLES"/>
462*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_TSE_BE_STALL_CYCLES_RAS"/>
463*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_TSE_BE_STALL_CYCLES_LRZ_BARYPLANE"/>
464*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_TSE_BE_STALL_CYCLES_LRZ_ZPLANE"/>
465*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_TSE_BE_STARVE_CYCLES_PC"/>
466*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_TSE_BE_INPUT_PRIM"/>
467*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_TSE_BE_INPUT_NULL_PRIM"/>
468*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_TSE_BE_TRIVAL_REJ_PRIM"/>
469*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_TSE_BE_CLIPPED_PRIM"/>
470*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_TSE_BE_ZERO_AREA_PRIM"/>
471*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_TSE_BE_FACENESS_CULLED_PRIM"/>
472*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_TSE_BE_ZERO_PIXEL_PRIM"/>
473*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_TSE_BE_OUTPUT_NULL_PRIM"/>
474*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_TSE_BE_OUTPUT_VISIBLE_PRIM"/>
475*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_TSE_BE_CINVOCATION"/>
476*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_TSE_BE_CPRIMITIVES"/>
477*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_TSE_BE_2D_INPUT_PRIM"/>
478*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_TSE_BE_2D_ALIVE_CYCLES"/>
479*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_TSE_BE_CLIP_PLANES"/>
480*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_TSE_BE_EMPTY_BBOX_KILLED_PRIM"/>
481*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_TSE_BE_ST1_VP_PARAMS_CACHE_MISS"/>
482*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_TSE_BE_ST2_VPORT_VP_PARAMS_CACHE_MISS"/>
483*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_TSE_BE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS"/>
484*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_TSE_BE_ILLEGAL_BOUNDING_BOX_PRIM"/>
485*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_TSE_BE_VP_OUT_IS_NAN"/>
486*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_TSE_BE_EXCLUDED_PRIM"/>
487*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_TSE_BE_EARLY_CULL_CLIPPED_PRIM"/>
488*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_CLIP"/>
489*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_TSE_BE_BR_STALLS_DUETO_BV_POLY"/>
490*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_CLIP"/>
491*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_TSE_BE_BV_STALLS_DUETO_BR_POLY"/>
492*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_TSE_BE_BV_STALLS_DUETO_BR"/>
493*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_TSE_FE_BUSY_CYCLES"/>
494*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_TSE_FE_STALL_CYCLES_VPC_US"/>
495*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_TSE_FE_STARVE_CYCLES_PC"/>
496*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_TSE_FE_INPUT_PRIM"/>
497*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_TSE_FE_INPUT_NULL_PRIM"/>
498*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_TSE_FE_TRIVAL_REJ_PRIM"/>
499*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_TSE_FE_ZERO_AREA_PRIM"/>
500*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_TSE_FE_FACENESS_CULLED_PRIM"/>
501*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_TSE_FE_ZERO_PIXEL_PRIM"/>
502*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_TSE_FE_OUTPUT_NULL_PRIM"/>
503*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_TSE_FE_OUTPUT_VISIBLE_PRIM"/>
504*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_TSE_FE_CINVOCATION"/>
505*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_TSE_FE_CPRIMITIVES"/>
506*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_TSE_FE_CLIP_PLANES"/>
507*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_TSE_FE_EMPTY_BBOX_KILLED_PRIM"/>
508*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_TSE_FE_ST1_VP_PARAMS_CACHE_MISS"/>
509*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_TSE_FE_ST2_VPORT_VP_PARAMS_CACHE_MISS"/>
510*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_TSE_FE_ST2_SCISSOR_VP_PARAMS_CACHE_MISS"/>
511*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_TSE_FE_ILLEGAL_BOUNDING_BOX_PRIM"/>
512*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_TSE_FE_VP_OUT_IS_NAN"/>
513*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_TSE_FE_EXCLUDED_PRIM"/>
514*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_TSE_FE_EARLY_CULL_CLIPPED_PRIM"/>
515*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_CLIP"/>
516*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_TSE_FE_BR_STALLS_DUETO_BV_POLY"/>
517*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_CLIP"/>
518*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_TSE_FE_BV_STALLS_DUETO_BR_POLY"/>
519*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_TSE_FE_BV_STALLS_DUETO_BR"/>
520*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_TSE_BE_STALL_CYCLES_LRZ_PRIM"/>
521*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_TSE_FE_EARLY_BFCULL_GBCLIPPED_PRIM"/>
522*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_TSE_REG_PROGRAMMING_WORKING_CYCLE_L1"/>
523*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_TSE_REG_PROGRAMMING_ONLY_CYCLE_L0"/>
524*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_TSE_COMMON_RAM_WORKING_CYCLE_L2"/>
525*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_TSE_COMMON_RAM_RD_WORKING_CYCLE_L3"/>
526*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_TSE_COMMON_RAM_WR_WORKING_CYCLE_L3"/>
527*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_TSE_CLIP_CODE_WORKING_CYCLE_L1"/>
528*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_TSE_CLIP_WORKING_CYCLE_L1"/>
529*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_TSE_CLIP_CTRL_WORKING_CYCLE_L2"/>
530*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_TSE_CLIP_VP_FMUL_WORKING_CYCLE_L2"/>
531*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_TSE_CLIP_VP_FMUL_0_WORKING_CYCLE_L3"/>
532*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_TSE_CLIP_VP_FMUL_1_WORKING_CYCLE_L3"/>
533*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_TSE_CLIP_VP_FMUL_2_WORKING_CYCLE_L3"/>
534*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_TSE_CLIP_VP_FMUL_3_WORKING_CYCLE_L3"/>
535*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_TSE_CLIP_VP_FMUL_4_WORKING_CYCLE_L3"/>
536*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_TSE_CLIP_VP_FMUL_5_WORKING_CYCLE_L3"/>
537*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_TSE_CLIP_VP_FADD_WORKING_CYCLE_L2"/>
538*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_TSE_CLIP_VP_FADD_0_WORKING_CYCLE_L3"/>
539*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_TSE_CLIP_VP_FADD_1_WORKING_CYCLE_L3"/>
540*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_TSE_CLIP_VP_FADD_2_WORKING_CYCLE_L3"/>
541*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_TSE_CLIP_VP_RCP_WORKING_CYCLE_L2"/>
542*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_TSE_VP_TRANSFORM_WORKING_CYCLE_L1"/>
543*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_TSE_VP0_TRANSFORM_WORKING_CYCLE_L2"/>
544*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_TSE_VP1_TRANSFORM_WORKING_CYCLE_L2"/>
545*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_TSE_VP2_TRANSFORM_WORKING_CYCLE_L2"/>
546*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_TSE_VERTEX_GEN_WORKING_CYCLE_L1"/>
547*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_TSE_DET_WORKING_CYCLE_L1"/>
548*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_TSE_BBOX_WORKING_CYCLE_L1"/>
549*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_TSE_CULLING_WORKING_CYCLE_L1"/>
550*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_TSE_SETUP_WORKING_CYCLE_L1"/>
551*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_TSE_SETUP_CTRL_WORKING_CYCLE_L2"/>
552*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_TSE_SETUP_FDP3_WORKING_CYCLE_L2"/>
553*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_TSE_SETUP_FDP3_0_WORKING_CYCLE_L3"/>
554*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_TSE_SETUP_FDP3_1_WORKING_CYCLE_L3"/>
555*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_TSE_SETUP_FDP3_2_WORKING_CYCLE_L3"/>
556*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_TSE_SETUP_FDP3_3_WORKING_CYCLE_L3"/>
557*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_TSE_SETUP_FDP3_4_WORKING_CYCLE_L3"/>
558*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_TSE_SETUP_FDP3_5_WORKING_CYCLE_L3"/>
559*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_TSE_SETUP_FMUL_WORKING_CYCLE_L2"/>
560*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_TSE_SETUP_FMUL_0_WORKING_CYCLE_L3"/>
561*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_TSE_SETUP_FMUL_1_WORKING_CYCLE_L3"/>
562*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_TSE_SETUP_FMUL_2_WORKING_CYCLE_L3"/>
563*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_TSE_SETUP_FMUL_3_WORKING_CYCLE_L3"/>
564*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_TSE_SETUP_FMUL_4_WORKING_CYCLE_L3"/>
565*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_TSE_SETUP_FMUL_5_WORKING_CYCLE_L3"/>
566*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_TSE_EDGE_SETUP_WORKING_CYCLE_L1"/>
567*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_TSE_EDGE_SETUP_IMUL_WORKING_CYCLE_L2"/>
568*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_TSE_RAS_INTF_WORKING_CYCLE_L1"/>
569*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_TSE_LRZ_Z_INTF_WORKING_CYCLE_L1"/>
570*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_TSE_LRZ_BARY_INTF_WORKING_CYCLE_L1"/>
571*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_TSE_NON_CLIP_WORKING_CYCLES"/>
572*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_TSE_NULL_WORKING_CYCLES"/>
573*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_TSE_OUT_PRIM_WORKING_CYCLES"/>
574*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_TSE_INPUT_VERTEX_WORKING_CYCLES"/>
575*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_TSE_MVC_STALL_VPC"/>
576*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_TSE_VPC_STARVE_TSE"/>
577*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_TSE_WORKING_CYCLE_L0"/>
578*9f860dbfSRob Clark</enum>
579*9f860dbfSRob Clark
580*9f860dbfSRob Clark<enum name="a8xx_ras_perfcounter_select">
581*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_RAS_NEVER_COUNT"/>
582*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_RAS_BUSY_CYCLES"/>
583*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
584*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_RAS_STALL_CYCLES_LRZ"/>
585*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_RAS_STARVE_CYCLES_TSE"/>
586*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_RAS_SUPER_TILES"/>
587*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_RAS_8X4_TILES"/>
588*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_RAS_MASKGEN_ACTIVE"/>
589*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
590*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_RAS_FULLY_COVERED_8X4_TILES"/>
591*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_RAS_PRIM_KILLED_INVISILBE"/>
592*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
593*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
594*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_RAS_BLOCKS"/>
595*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_RAS_FALSE_PARTIAL_STILE"/>
596*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_RAS_SLICE_BLOCK_NONEMTPY"/>
597*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_RAS_SLICE_BLOCK_EMPTY"/>
598*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_0_WORKING_CC_L2"/>
599*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_1_WORKING_CC_L2"/>
600*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_2_WORKING_CC_L2"/>
601*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_3_WORKING_CC_L2"/>
602*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_4_WORKING_CC_L2"/>
603*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_5_WORKING_CC_L2"/>
604*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_6_WORKING_CC_L2"/>
605*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_7_WORKING_CC_L2"/>
606*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_8_WORKING_CC_L2"/>
607*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_9_WORKING_CC_L2"/>
608*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_10_WORKING_CC_L2"/>
609*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_11_WORKING_CC_L2"/>
610*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_12_WORKING_CC_L2"/>
611*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_13_WORKING_CC_L2"/>
612*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_14_WORKING_CC_L2"/>
613*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_RAS_SAMPLE_MASK_GEN_LANE_15_WORKING_CC_L2"/>
614*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_RAS_EMPTY_SBLOCK_SCAN_CYCLE_PERFCOUNTER"/>
615*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_RAS_STEGN_STALL_BY_LATENCY_FIFO"/>
616*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_RAS_STALL_CYCLES_LRZ_PREFETCH"/>
617*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_RAS_STGEN_BOTTLENECK_CYCLES"/>
618*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_RAS_MTGEN_BOTTLENECK_CYCLES"/>
619*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_RAS_TGEN_BOTTLENECK_CYCLES"/>
620*9f860dbfSRob Clark</enum>
621*9f860dbfSRob Clark
622*9f860dbfSRob Clark<enum name="a8xx_uche_perfcounter_select">
623*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_UCHE_NEVER_COUNT"/>
624*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_UCHE_BUSY_CYCLES"/>
625*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_UCHE_STALL_CYCLES_ARBITER"/>
626*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
627*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_UCHE_STARVED_CYCLES_VBIF_DECMP"/>
628*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_UCHE_STALL_CYCLES_DECMP"/>
629*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_UCHE_ARBITER_STALL_CYCLES_VBIF"/>
630*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_UCHE_VBIF_LATENCY_CYCLES"/>
631*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
632*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
633*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_UCHE_DCMP_LATENCY_CYCLES"/>
634*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_UCHE_READ_REQUESTS_SP"/>
635*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_UCHE_READ_REQUESTS_TP"/>
636*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_UCHE_READ_REQUESTS_TP_UBWC"/>
637*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_UCHE_READ_REQUESTS_TP_GBIF"/>
638*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_UCHE_READ_REQUESTS_TP_GMEM"/>
639*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_UCHE_READ_REQUESTS_VFD"/>
640*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_UCHE_READ_REQUESTS_VPC"/>
641*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_UCHE_READ_REQUESTS_HLSQ"/>
642*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_UCHE_READ_REQUESTS_LRZ"/>
643*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_UCHE_READ_REQUESTS_PC"/>
644*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_UCHE_WRITE_REQUESTS_SP"/>
645*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_UCHE_WRITE_REQUESTS_LRZ"/>
646*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_UCHE_WRITE_REQUESTS_VPC"/>
647*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_UCHE_WRITE_REQUESTS_VSC"/>
648*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_SP"/>
649*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_TP"/>
650*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_VFD"/>
651*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_VPC"/>
652*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
653*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
654*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_PC"/>
655*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_CH0"/>
656*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_UCHE_VBIF_READ_BEATS_CH1"/>
657*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_UCHE_VBIF_WRITE_BEATS_CH0"/>
658*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_UCHE_VBIF_WRITE_BEATS_CH1"/>
659*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_UCHE_GMEM_READ_BEATS"/>
660*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_UCHE_GMEM_WRITE_BEATS"/>
661*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_UCHE_UBWC_READ_BEATS"/>
662*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_UCHE_UBWC_WRITE_BEATS"/>
663*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_UCHE_EVICTS"/>
664*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_UCHE_BANK_REQ0"/>
665*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_UCHE_BANK_REQ1"/>
666*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_UCHE_BANK_REQ2"/>
667*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_UCHE_BANK_REQ3"/>
668*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_UCHE_BANK_REQ4"/>
669*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_UCHE_BANK_REQ5"/>
670*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_UCHE_BANK_REQ6"/>
671*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_UCHE_BANK_REQ7"/>
672*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_UCHE_TPH_REF_FULL"/>
673*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_UCHE_TPH_VICTIM_FULL"/>
674*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_UCHE_TPH_EXT_FULL"/>
675*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_UCHE_RAM_READ_REQ"/>
676*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_UCHE_RAM_WRITE_REQ"/>
677*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_UCHE_LONG_LINE_ALL_EVICTS"/>
678*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_UCHE_LONG_LINE_PARTIAL_EVICTS"/>
679*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_UCHE_TPH_CONFLICT_CL_CCHE"/>
680*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_UCHE_TPH_CONFLICT_CL_OTHER"/>
681*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_UCHE_DBANK_CONFLICT_CL_CCHE"/>
682*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_UCHE_DBANK_CONFLICT_CL_OTHER_CLIENTS"/>
683*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_UCHE_CCHE_TPH_QUEUE_FULL"/>
684*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_UCHE_CCHE_DPH_IO_QUEUE_FULL"/>
685*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_UCHE_CCHE_DPH_CMDPOOL_FULL"/>
686*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_UCHE_EVICTS_SP"/>
687*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_UCHE_EVICTS_LRZ"/>
688*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_UCHE_READ_REQUESTS_VPCUS"/>
689*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BV"/>
690*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_UCHE_READ_REQUESTS_VFD_BYPASS_BR"/>
691*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_BYPC_FULL"/>
692*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_BYPC_FULL_CCHE_STALL"/>
693*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_BYPC_VHUB_STALL"/>
694*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_BYPD_FULL"/>
695*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_BYPD_FULL_GBIF_STALL"/>
696*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_VHUB_PTABLE_FULL"/>
697*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_DHUB_PTABLE_FULL"/>
698*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_UCHE_RESERVED_75"/>
699*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_UCHE_RESERVED_76"/>
700*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_UCHE_RESERVED_77"/>
701*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_UCHE_RESERVED_78"/>
702*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_UCHE_RESERVED_79"/>
703*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_UCHE_RESERVED_80"/>
704*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_UCHE_RESERVED_81"/>
705*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_UCHE_RESERVED_82"/>
706*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_UCHE_RESERVED_83"/>
707*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_UCHE_RESERVED_84"/>
708*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_UCHE_RESERVED_85"/>
709*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_UCHE_RESERVED_86"/>
710*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_UCHE_RESERVED_87"/>
711*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_UCHE_RESERVED_88"/>
712*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_UCHE_RESERVED_89"/>
713*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_UCHE_RESERVED_90"/>
714*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_UCHE_RESERVED_91"/>
715*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_UCHE_RESERVED_92"/>
716*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_UCHE_RESERVED_93"/>
717*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_UCHE_RESERVED_94"/>
718*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_UCHE_RESERVED_95"/>
719*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_UCHE_RESERVED_96"/>
720*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_UCHE_RESERVED_97"/>
721*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_UCHE_RESERVED_98"/>
722*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_UCHE_RESERVED_99"/>
723*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_UCHE_RESERVED_100"/>
724*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_UCHE_RESERVED_101"/>
725*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_UCHE_RESERVED_102"/>
726*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_UCHE_RESERVED_103"/>
727*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_UCHE_RESERVED_104"/>
728*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_UCHE_RESERVED_105"/>
729*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_UCHE_RESERVED_106"/>
730*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_UCHE_RESERVED_107"/>
731*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_UCHE_RESERVED_108"/>
732*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_UCHE_RESERVED_109"/>
733*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_UCHE_RESERVED_110"/>
734*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_UCHE_RESERVED_111"/>
735*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_UCHE_RESERVED_112"/>
736*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_UCHE_RESERVED_113"/>
737*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_UCHE_RESERVED_114"/>
738*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_UCHE_RESERVED_115"/>
739*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_UCHE_RESERVED_116"/>
740*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_UCHE_RESERVED_117"/>
741*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_UCHE_RESERVED_118"/>
742*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_UCHE_RESERVED_119"/>
743*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_UCHE_RESERVED_120"/>
744*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_UCHE_RESERVED_121"/>
745*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_UCHE_RESERVED_122"/>
746*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_UCHE_RESERVED_123"/>
747*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_UCHE_RESERVED_124"/>
748*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_UCHE_RESERVED_125"/>
749*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_UCHE_RESERVED_126"/>
750*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_UCHE_RESERVED_127"/>
751*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_CCHE_BUSY_CYCLES"/>
752*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_CCHE_STALL_CYCLES_UCHE"/>
753*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_CCHE_UCHE_STALL_WRITE_DATA"/>
754*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_CCHE_UCHE_LATENCY_CYCLES"/>
755*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_CCHE_UCHE_LATENCY_SAMPLES"/>
756*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_CCHE_READ_REQUESTS_SP_TOTAL"/>
757*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_CCHE_READ_REQUESTS_SP_UBWC"/>
758*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_CCHE_READ_REQUESTS_SP_GBIF"/>
759*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_CCHE_READ_REQUESTS_SP_GMEM"/>
760*9f860dbfSRob Clark	<value value="137" name="A8XX_PERF_CCHE_READ_REQUESTS_TP_TOTAL"/>
761*9f860dbfSRob Clark	<value value="138" name="A8XX_PERF_CCHE_READ_REQUESTS_TP_UBWC"/>
762*9f860dbfSRob Clark	<value value="139" name="A8XX_PERF_CCHE_READ_REQUESTS_TP_GBIF"/>
763*9f860dbfSRob Clark	<value value="140" name="A8XX_PERF_CCHE_READ_REQUESTS_TP_GMEM"/>
764*9f860dbfSRob Clark	<value value="141" name="A8XX_PERF_CCHE_READ_REQUESTS_VFD_TOTAL"/>
765*9f860dbfSRob Clark	<value value="142" name="A8XX_PERF_CCHE_READ_REQUEST_VFD_GMEM"/>
766*9f860dbfSRob Clark	<value value="143" name="A8XX_PERF_CCHE_READ_REQUEST_VFD_GBIF"/>
767*9f860dbfSRob Clark	<value value="144" name="A8XX_PERF_CCHE_READ_REQUESTS_LRZ"/>
768*9f860dbfSRob Clark	<value value="145" name="A8XX_PERF_CCHE_READ_REQUESTS_VPC"/>
769*9f860dbfSRob Clark	<value value="146" name="A8XX_PERF_CCHE_WRITE_REQUESTS_SP"/>
770*9f860dbfSRob Clark	<value value="147" name="A8XX_PERF_CCHE_WRITE_REQUESTS_LRZ"/>
771*9f860dbfSRob Clark	<value value="148" name="A8XX_PERF_CCHE_READ_REQUESTS_GMEM"/>
772*9f860dbfSRob Clark	<value value="149" name="A8XX_PERF_CCHE_WRITE_REQUESTS_GMEM"/>
773*9f860dbfSRob Clark	<value value="150" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_TP"/>
774*9f860dbfSRob Clark	<value value="151" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_VFD"/>
775*9f860dbfSRob Clark	<value value="152" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_SP"/>
776*9f860dbfSRob Clark	<value value="153" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_VPC"/>
777*9f860dbfSRob Clark	<value value="154" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_LRZ"/>
778*9f860dbfSRob Clark	<value value="155" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_CH0"/>
779*9f860dbfSRob Clark	<value value="156" name="A8XX_PERF_CCHE_UCHE_READ_BEATS_CH1"/>
780*9f860dbfSRob Clark	<value value="157" name="A8XX_PERF_CCHE_GMEM_READ_BEATS_VPC"/>
781*9f860dbfSRob Clark	<value value="158" name="A8XX_PERF_CCHE_GMEM_READ_BEATS_TP"/>
782*9f860dbfSRob Clark	<value value="159" name="A8XX_PERF_CCHE_GMEM_READ_BEATS_SP"/>
783*9f860dbfSRob Clark	<value value="160" name="A8XX_PERF_CCHE_GMEM_READ_BEATS_VFD"/>
784*9f860dbfSRob Clark	<value value="161" name="A8XX_PERF_CCHE_BANK_REQ0"/>
785*9f860dbfSRob Clark	<value value="162" name="A8XX_PERF_CCHE_BANK_REQ1"/>
786*9f860dbfSRob Clark	<value value="163" name="A8XX_PERF_CCHE_BANK_REQ2"/>
787*9f860dbfSRob Clark	<value value="164" name="A8XX_PERF_CCHE_BANK_REQ3"/>
788*9f860dbfSRob Clark	<value value="165" name="A8XX_PERF_CCHE_BANK_REQ4"/>
789*9f860dbfSRob Clark	<value value="166" name="A8XX_PERF_CCHE_BANK_REQ5"/>
790*9f860dbfSRob Clark	<value value="167" name="A8XX_PERF_CCHE_BANK_REQ6"/>
791*9f860dbfSRob Clark	<value value="168" name="A8XX_PERF_CCHE_BANK_REQ7"/>
792*9f860dbfSRob Clark	<value value="169" name="A8XX_PERF_CCHE_BANK_REQ8"/>
793*9f860dbfSRob Clark	<value value="170" name="A8XX_PERF_CCHE_BANK_REQ9"/>
794*9f860dbfSRob Clark	<value value="171" name="A8XX_PERF_CCHE_BANK_REQ10"/>
795*9f860dbfSRob Clark	<value value="172" name="A8XX_PERF_CCHE_BANK_REQ11"/>
796*9f860dbfSRob Clark	<value value="173" name="A8XX_PERF_CCHE_BANK_REQ12"/>
797*9f860dbfSRob Clark	<value value="174" name="A8XX_PERF_CCHE_BANK_REQ13"/>
798*9f860dbfSRob Clark	<value value="175" name="A8XX_PERF_CCHE_BANK_REQ14"/>
799*9f860dbfSRob Clark	<value value="176" name="A8XX_PERF_CCHE_BANK_REQ15"/>
800*9f860dbfSRob Clark	<value value="177" name="A8XX_PERF_CCHE_GBANK_REQ0"/>
801*9f860dbfSRob Clark	<value value="178" name="A8XX_PERF_CCHE_GBANK_REQ1"/>
802*9f860dbfSRob Clark	<value value="179" name="A8XX_PERF_CCHE_GBANK_REQ2"/>
803*9f860dbfSRob Clark	<value value="180" name="A8XX_PERF_CCHE_GBANK_REQ3"/>
804*9f860dbfSRob Clark	<value value="181" name="A8XX_PERF_CCHE_TPH_REF_FULL"/>
805*9f860dbfSRob Clark	<value value="182" name="A8XX_PERF_CCHE_TPH_VICTIM_FULL"/>
806*9f860dbfSRob Clark	<value value="183" name="A8XX_PERF_CCHE_TPH_EXT_FULL"/>
807*9f860dbfSRob Clark	<value value="184" name="A8XX_PERF_CCHE_RAM_READ_REQ"/>
808*9f860dbfSRob Clark	<value value="185" name="A8XX_PERF_CCHE_RAM_WRITE_REQ"/>
809*9f860dbfSRob Clark	<value value="186" name="A8XX_PERF_CCHE_TPH_CONFLICT_CL"/>
810*9f860dbfSRob Clark	<value value="187" name="A8XX_PERF_CCHE_DBANK_CONFLICT"/>
811*9f860dbfSRob Clark	<value value="188" name="A8XX_PERF_CCHE_TPH_QUEUE_FULL"/>
812*9f860dbfSRob Clark	<value value="189" name="A8XX_PERF_CCHE_DPH_QUEUE_FULL"/>
813*9f860dbfSRob Clark	<value value="190" name="A8XX_PERF_CCHE_OPH_QUEUE_FULL"/>
814*9f860dbfSRob Clark	<value value="191" name="A8XX_PERF_CCHE_WACK_QUEUE_FULL"/>
815*9f860dbfSRob Clark	<value value="192" name="A8XX_PERF_CCHE_GMEM0_LOCAL_RD_REQUEST"/>
816*9f860dbfSRob Clark	<value value="193" name="A8XX_PERF_CCHE_GMEM0_LOCAL_WR_REQUEST"/>
817*9f860dbfSRob Clark	<value value="194" name="A8XX_PERF_CCHE_GMEM1_LOCAL_RD_REQUEST"/>
818*9f860dbfSRob Clark	<value value="195" name="A8XX_PERF_CCHE_GMEM1_LOCAL_WR_REQUEST"/>
819*9f860dbfSRob Clark	<value value="196" name="A8XX_PERF_CCHE_GMEM0_REMOTE_RD_REQUEST"/>
820*9f860dbfSRob Clark	<value value="197" name="A8XX_PERF_CCHE_GMEM0_REMOTE_WR_REQUEST"/>
821*9f860dbfSRob Clark	<value value="198" name="A8XX_PERF_CCHE_GMEM1_REMOTE_RD_REQUEST"/>
822*9f860dbfSRob Clark	<value value="199" name="A8XX_PERF_CCHE_GMEM1_REMOTE_WR_REQUEST"/>
823*9f860dbfSRob Clark	<value value="200" name="A8XX_PERF_CCHE_STALL_CYCLES_TP"/>
824*9f860dbfSRob Clark	<value value="201" name="A8XX_PERF_CCHE_ATOMIC_REQUESTS_SP_TOTAL"/>
825*9f860dbfSRob Clark	<value value="202" name="A8XX_PERF_CCHE_ATOMIC_PACKING_BEAT_SP_TOTAL"/>
826*9f860dbfSRob Clark</enum>
827*9f860dbfSRob Clark
828*9f860dbfSRob Clark<enum name="a8xx_tp_perfcounter_select">
829*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_TP_NEVER_COUNT"/>
830*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_TP_BUSY_CYCLES"/>
831*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_TP_STALL_CYCLES_UCHE"/>
832*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_TP_LATENCY_CYCLES"/>
833*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_TP_LATENCY_TRANS"/>
834*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_TP_FLAG_FIFO_DELAY_SAMPLES"/>
835*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_TP_FLAG_FIFO_DELAY_CYCLES"/>
836*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_TP_L1_CACHELINE_REQUESTS"/>
837*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_TP_L1_CACHELINE_MISSES"/>
838*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_TP_SP_TP_TRANS"/>
839*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_TP_TP_SP_TRANS"/>
840*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_TP_OUTPUT_PIXELS"/>
841*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_TP_FILTER_WORKLOAD_16BIT"/>
842*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_TP_FILTER_WORKLOAD_32BIT"/>
843*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_TP_QUADS_RECEIVED"/>
844*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_TP_QUADS_OFFSET"/>
845*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_TP_QUADS_SHADOW"/>
846*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_TP_QUADS_ARRAY"/>
847*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_TP_QUADS_GRADIENT"/>
848*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_TP_QUADS_1D"/>
849*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_TP_QUADS_2D"/>
850*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_TP_QUADS_BUFFER"/>
851*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_TP_QUADS_3D"/>
852*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_TP_QUADS_CUBE"/>
853*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
854*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
855*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_TP_OUTPUT_PIXELS_POINT"/>
856*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
857*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_TP_OUTPUT_PIXELS_MIP"/>
858*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_TP_OUTPUT_PIXELS_ANISO"/>
859*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
860*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_TP_FLAG_CACHE_REQUESTS"/>
861*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_TP_FLAG_CACHE_MISSES"/>
862*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_TP_L1_5_L2_REQUESTS"/>
863*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_TP_2D_OUTPUT_PIXELS"/>
864*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
865*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
866*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
867*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
868*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_TP_TPA2TPC_TRANS"/>
869*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_TP_L1_MISSES_ASTC_1TILE"/>
870*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_TP_L1_MISSES_ASTC_2TILE"/>
871*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_TP_L1_MISSES_ASTC_4TILE"/>
872*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_TP_L1_5_COMPRESS_REQS"/>
873*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_TP_L1_5_L2_COMPRESS_MISS"/>
874*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_TP_L1_BANK_CONFLICT"/>
875*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
876*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
877*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
878*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_TP_FRONTEND_WORKING_CYCLES"/>
879*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_TP_L1_TAG_WORKING_CYCLES"/>
880*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
881*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
882*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_TP_BACKEND_WORKING_CYCLES"/>
883*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
884*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_TP_STARVE_CYCLES_SP"/>
885*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_TP_STARVE_CYCLES_UCHE"/>
886*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_TP_STALL_CYCLES_UFC"/>
887*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_TP_FORMAT_DECOMP_POINT"/>
888*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_TP_FILTER_POINT_FP16"/>
889*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_TP_FILTER_POINT_FP32"/>
890*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_TP_LATENCY_FIFO_FULL"/>
891*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_TP_RESERVED_62"/>
892*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_TP_RESERVED_63"/>
893*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_TP_RESERVED_64"/>
894*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_TP_RESERVED_65"/>
895*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_TP_RESERVED_66"/>
896*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_TP_RESERVED_67"/>
897*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_TP_RESERVED_68"/>
898*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_TP_RESERVED_69"/>
899*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_TP_RESERVED_70"/>
900*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_TP_RESERVED_71"/>
901*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_TP_RESERVED_72"/>
902*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_TP_RESERVED_73"/>
903*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_TP_RESERVED_74"/>
904*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_TP_RESERVED_75"/>
905*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_TP_RESERVED_76"/>
906*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_TP_RESERVED_77"/>
907*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_TP_RESERVED_78"/>
908*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_TP_RESERVED_79"/>
909*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_TP_RESERVED_80"/>
910*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_TP_RESERVED_81"/>
911*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_TP_RESERVED_82"/>
912*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_TP_RESERVED_83"/>
913*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_TP_RESERVED_84"/>
914*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_TP_RESERVED_85"/>
915*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_TP_RESERVED_86"/>
916*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_TP_RESERVED_87"/>
917*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_TP_RESERVED_88"/>
918*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_TP_RESERVED_89"/>
919*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_TP_RESERVED_90"/>
920*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_TP_RESERVED_91"/>
921*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_TP_RESERVED_92"/>
922*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_TP_RESERVED_93"/>
923*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_TP_RESERVED_94"/>
924*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_TP_RESERVED_95"/>
925*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_TP_RESERVED_96"/>
926*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_TP_RESERVED_97"/>
927*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_TP_RESERVED_98"/>
928*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_TP_RESERVED_99"/>
929*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_TP_RESERVED_100"/>
930*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_TP_RESERVED_101"/>
931*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_TP_RESERVED_102"/>
932*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_TP_RESERVED_103"/>
933*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_TP_RESERVED_104"/>
934*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_TP_RESERVED_105"/>
935*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_TP_RESERVED_106"/>
936*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_TP_RESERVED_107"/>
937*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_TP_RESERVED_108"/>
938*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_TP_RESERVED_109"/>
939*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_TP_RESERVED_110"/>
940*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_TP_RESERVED_111"/>
941*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_TP_RESERVED_112"/>
942*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_TP_RESERVED_113"/>
943*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_TP_RESERVED_114"/>
944*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_TP_RESERVED_115"/>
945*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_TP_RESERVED_116"/>
946*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_TP_RESERVED_117"/>
947*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_TP_RESERVED_118"/>
948*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_TP_RESERVED_119"/>
949*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_TP_RESERVED_120"/>
950*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_TP_RESERVED_121"/>
951*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_TP_RESERVED_122"/>
952*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_TP_RESERVED_123"/>
953*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_TP_RESERVED_124"/>
954*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_TP_RESERVED_125"/>
955*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_TP_RESERVED_126"/>
956*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_TP_RESERVED_127"/>
957*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_TP_FORMAT_DECOMP_BILINEAR"/>
958*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP16"/>
959*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP16"/>
960*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_TP_PACKED_POINT_BOTH_VALID_FP32"/>
961*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_TP_PACKED_POINT_SINGLE_VALID_FP32"/>
962*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_TP_TOTAL_DECOMP_L1_RESP_CH0"/>
963*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_TP_TOTAL_DECOMP_L1_RESP_CH1"/>
964*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_TP_L1POINT5_PRE_L1_DECOMP_0_WORKLOAD_R"/>
965*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_TP_L1POINT5_PRE_L1_DECOMP_1_WORKLOAD_R"/>
966*9f860dbfSRob Clark	<value value="137" name="A8XX_PERF_TP_L1POINT5_ASTC_DECODER_0_WORKLOAD_R"/>
967*9f860dbfSRob Clark	<value value="138" name="A8XX_PERF_TP_L1POINT5_ASTC_DECODER_1_WORKLOAD_R"/>
968*9f860dbfSRob Clark	<value value="139" name="A8XX_PERF_TP_PARTIAL_SURFACE_PGMEM_PIXELS"/>
969*9f860dbfSRob Clark	<value value="140" name="A8XX_PERF_TP_PARTIAL_SURFACE_SYSMEM_PIXELS"/>
970*9f860dbfSRob Clark	<value value="141" name="A8XX_PERF_TP_PARTIAL_SURFACE_PGMEM_MISS_REQ"/>
971*9f860dbfSRob Clark	<value value="142" name="A8XX_PERF_TP_PARTIAL_SURFACE_SYSMEM_MISS_REQ"/>
972*9f860dbfSRob Clark</enum>
973*9f860dbfSRob Clark
974*9f860dbfSRob Clark<enum name="a8xx_sp_perfcounter_select">
975*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_SP_NEVER_COUNT"/>
976*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_SP_BUSY_CYCLES"/>
977*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_SP_ALU_WORKING_CYCLES"/>
978*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_SP_STALL_CYCLES_VPC_BE"/>
979*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_SP_STALL_CYCLES_TP"/>
980*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_SP_STALL_CYCLES_UCHE"/>
981*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_SP_STALL_CYCLES_RB"/>
982*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_SP_NON_EXECUTION_CYCLES"/>
983*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_SP_WAVE_CONTEXTS"/>
984*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_SP_WAVE_CONTEXT_CYCLES"/>
985*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_SP_FS_STAGE_WAVE_CYCLES"/>
986*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
987*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_SP_VS_STAGE_WAVE_CYCLES"/>
988*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
989*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_SP_FS_STAGE_DURATION_CYCLES"/>
990*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_SP_VS_STAGE_DURATION_CYCLES"/>
991*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_SP_WAVE_CTRL_CYCLES"/>
992*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_SP_WAVE_LOAD_CYCLES"/>
993*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_SP_WAVE_EMIT_CYCLES"/>
994*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_SP_WAVE_NOP_CYCLES"/>
995*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_SP_WAVE_WAIT_CYCLES"/>
996*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_SP_WAVE_FETCH_CYCLES"/>
997*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_SP_WAVE_IDLE_CYCLES"/>
998*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_SP_WAVE_END_CYCLES"/>
999*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
1000*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
1001*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_SP_WAVE_JOIN_CYCLES"/>
1002*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_SP_LM_LOAD_INSTRUCTIONS"/>
1003*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_SP_LM_STORE_INSTRUCTIONS"/>
1004*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_SP_LM_ATOMICS"/>
1005*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_SP_GM_LOAD_INSTRUCTIONS"/>
1006*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_SP_GM_STORE_INSTRUCTIONS"/>
1007*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_SP_GM_ATOMICS"/>
1008*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
1009*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
1010*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
1011*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
1012*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
1013*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
1014*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
1015*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
1016*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
1017*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
1018*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_SP_VS_INSTRUCTIONS"/>
1019*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_SP_FS_INSTRUCTIONS"/>
1020*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_SP_ADDR_LOCK_COUNT"/>
1021*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_SP_UCHE_READ_TRANS"/>
1022*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_SP_UCHE_WRITE_TRANS"/>
1023*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_SP_EXPORT_VPC_TRANS"/>
1024*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_SP_EXPORT_RB_TRANS"/>
1025*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_SP_PIXELS_KILLED"/>
1026*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_SP_ICL1_REQUESTS"/>
1027*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_SP_ICL1_MISSES"/>
1028*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_SP_HS_INSTRUCTIONS"/>
1029*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_SP_DS_INSTRUCTIONS"/>
1030*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_SP_GS_INSTRUCTIONS"/>
1031*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_SP_CS_INSTRUCTIONS"/>
1032*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_SP_GPR_READ"/>
1033*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_SP_GPR_WRITE"/>
1034*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
1035*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
1036*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_SP_LM_BANK_CONFLICTS"/>
1037*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
1038*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
1039*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
1040*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_SP_LM_WORKING_CYCLES"/>
1041*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_SP_DISPATCHER_WORKING_CYCLES"/>
1042*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_SP_SEQUENCER_WORKING_CYCLES"/>
1043*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
1044*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_SP_STARVE_CYCLES_HLSQ"/>
1045*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_SP_NON_EXECUTION_LS_CYCLES"/>
1046*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_SP_WORKING_EU"/>
1047*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_SP_ANY_EU_WORKING"/>
1048*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_SP_WORKING_EU_FS_STAGE"/>
1049*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
1050*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_SP_WORKING_EU_VS_STAGE"/>
1051*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
1052*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_SP_WORKING_EU_CS_STAGE"/>
1053*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
1054*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_SP_GPR_READ_PREFETCH"/>
1055*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_SP_GPR_READ_CONFLICT"/>
1056*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_SP_GPR_WRITE_CONFLICT"/>
1057*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
1058*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
1059*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_SP_EXECUTABLE_WAVES"/>
1060*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_SP_ICL1_MISS_FETCH_CYCLES"/>
1061*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_SP_RESERVED_86"/>
1062*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_SP_BYPASS_BUSY_CYCLES"/>
1063*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_SP_ANY_EU_WORKING_LPAC"/>
1064*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_SP_WAVE_ALU_CYCLES"/>
1065*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_SP_WAVE_EFU_CYCLES"/>
1066*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_SP_WAVE_INT_CYCLES"/>
1067*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_SP_WAVE_CSP_CYCLES"/>
1068*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_SP_EWAVE_CONTEXTS"/>
1069*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_SP_EWAVE_CONTEXT_CYCLES"/>
1070*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_SP_LPAC_BUSY_CYCLES"/>
1071*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_SP_LPAC_INSTRUCTIONS"/>
1072*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_SP_FS_STAGE_1X_WAVES"/>
1073*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_SP_FS_STAGE_2X_WAVES"/>
1074*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_SP_QUADS"/>
1075*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_SP_CS_INVOCATIONS"/>
1076*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_SP_PIXELS"/>
1077*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_SP_LPAC_DRAWCALLS"/>
1078*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_SP_PI_WORKING_CYCLES"/>
1079*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_SP_WAVE_INPUT_CYCLES"/>
1080*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_SP_WAVE_OUTPUT_CYCLES"/>
1081*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_SP_WAVE_HWAVE_WAIT_CYCLES"/>
1082*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_SP_WAVE_HWAVE_SYNC"/>
1083*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_SP_OUTPUT_3D_PIXELS"/>
1084*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_SP_FULL_ALU_MAD_INSTRUCTIONS"/>
1085*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_SP_HALF_ALU_MAD_INSTRUCTIONS"/>
1086*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_SP_FULL_ALU_MUL_INSTRUCTIONS"/>
1087*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_SP_HALF_ALU_MUL_INSTRUCTIONS"/>
1088*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_SP_FULL_ALU_ADD_INSTRUCTIONS"/>
1089*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_SP_HALF_ALU_ADD_INSTRUCTIONS"/>
1090*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_SP_BARY_FP32_INSTRUCTIONS"/>
1091*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_SP_ALU_GPR_READ_CYCLES"/>
1092*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_SP_ALU_DATA_FORWARDING_CYCLES"/>
1093*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_SP_LM_FULL_CYCLES"/>
1094*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_SP_TEXTURE_FETCH_LATENCY_CYCLES"/>
1095*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_SP_TEXTURE_FETCH_LATENCY_SAMPLES"/>
1096*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_SP_FS_STAGE_PI_TEX_INSTRUCTION"/>
1097*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_SP_RAY_QUERY_INSTRUCTIONS"/>
1098*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_SP_RBRT_KICKOFF_FIBERS"/>
1099*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_SP_RBRT_KICKOFF_DQUADS"/>
1100*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_SP_RTU_BUSY_CYCLES"/>
1101*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_SP_RTU_L0_HITS"/>
1102*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_SP_RTU_L0_MISSES"/>
1103*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_SP_RTU_L0_HIT_ON_MISS"/>
1104*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_SP_RTU_STALL_CYCLES_WAVE_QUEUE"/>
1105*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_SP_RTU_STALL_CYCLES_L0_HIT_QUEUE"/>
1106*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_SP_RTU_STALL_CYCLES_L0_MISS_QUEUE"/>
1107*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_SP_RTU_STALL_CYCLES_L0D_IDX_QUEUE"/>
1108*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_SP_RTU_STALL_CYCLES_L0DATA"/>
1109*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_SP_RTU_STALL_CYCLES_REPLACE_CNT"/>
1110*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_SP_RTU_STALL_CYCLES_MRG_CNT"/>
1111*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_SP_RTU_STALL_CYCLES_UCHE"/>
1112*9f860dbfSRob Clark	<value value="137" name="A8XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_L0"/>
1113*9f860dbfSRob Clark	<value value="138" name="A8XX_PERF_SP_RTU_OPERAND_FETCH_STALL_CYCLES_INS_FIFO"/>
1114*9f860dbfSRob Clark	<value value="139" name="A8XX_PERF_SP_RTU_BVH_FETCH_LATENCY_CYCLES"/>
1115*9f860dbfSRob Clark	<value value="140" name="A8XX_PERF_SP_RTU_BVH_FETCH_LATENCY_SAMPLES"/>
1116*9f860dbfSRob Clark	<value value="141" name="A8XX_PERF_SP_STCHE_MISS_INC_VS"/>
1117*9f860dbfSRob Clark	<value value="142" name="A8XX_PERF_SP_STCHE_MISS_INC_FS"/>
1118*9f860dbfSRob Clark	<value value="143" name="A8XX_PERF_SP_STCHE_MISS_INC_BV"/>
1119*9f860dbfSRob Clark	<value value="144" name="A8XX_PERF_SP_STCHE_MISS_INC_LPAC"/>
1120*9f860dbfSRob Clark	<value value="145" name="A8XX_PERF_SP_VGPR_ACTIVE_CONTEXTS"/>
1121*9f860dbfSRob Clark	<value value="146" name="A8XX_PERF_SP_PGPR_ALLOC_CONTEXTS"/>
1122*9f860dbfSRob Clark	<value value="147" name="A8XX_PERF_SP_VGPR_ALLOC_CONTEXTS"/>
1123*9f860dbfSRob Clark	<value value="148" name="A8XX_PERF_SP_RTU_RAY_BOX_INTERSECTIONS"/>
1124*9f860dbfSRob Clark	<value value="149" name="A8XX_PERF_SP_RTU_RAY_TRIANGLE_INTERSECTIONS"/>
1125*9f860dbfSRob Clark	<value value="150" name="A8XX_PERF_SP_SCH_STALL_CYCLES_RTU"/>
1126*9f860dbfSRob Clark	<value value="151" name="A8XX_PERF_SP_EFU_WORKING_CYCLES"/>
1127*9f860dbfSRob Clark	<value value="152" name="A8XX_PERF_SP_BRANCH_TAKEN"/>
1128*9f860dbfSRob Clark	<value value="153" name="A8XX_PERF_SP_BRANCH_NOT_TAKEN"/>
1129*9f860dbfSRob Clark	<value value="154" name="A8XX_PERF_SP_BRANCH_INS_DIVERGENCY_COUNT"/>
1130*9f860dbfSRob Clark	<value value="155" name="A8XX_PERF_SP_BRANCH_INS_COUNT"/>
1131*9f860dbfSRob Clark	<value value="156" name="A8XX_PERF_SP_PREDICT_TAKEN"/>
1132*9f860dbfSRob Clark	<value value="157" name="A8XX_PERF_SP_PREDICT_NOT_TAKEN"/>
1133*9f860dbfSRob Clark	<value value="158" name="A8XX_PERF_SP_PREDICT_INS_DIVERGENCY_COUNT"/>
1134*9f860dbfSRob Clark	<value value="159" name="A8XX_PERF_SP_PREDICT_INS_COUNT"/>
1135*9f860dbfSRob Clark	<value value="160" name="A8XX_PERF_SP_CCHE_UAV_TOTAL_REQ"/>
1136*9f860dbfSRob Clark	<value value="161" name="A8XX_PERF_SP_CCHE_UAV_TOTAL_DUALQUAD"/>
1137*9f860dbfSRob Clark	<value value="162" name="A8XX_PERF_SP_CCHE_NONUAV_TOTAL_REQ"/>
1138*9f860dbfSRob Clark	<value value="163" name="A8XX_PERF_SP_CCHE_NONUAV_TOTAL_DUALQUAD"/>
1139*9f860dbfSRob Clark	<value value="164" name="A8XX_PERF_SP_LB_NONUAV_TOTAL_REQ"/>
1140*9f860dbfSRob Clark	<value value="165" name="A8XX_PERF_SP_LB_NONUAV_TOTAL_DUALQUAD"/>
1141*9f860dbfSRob Clark	<value value="166" name="A8XX_PERF_SP_LB_READ_XFER_ALU"/>
1142*9f860dbfSRob Clark	<value value="167" name="A8XX_PERF_SP_LB_ALU_READ_CONS"/>
1143*9f860dbfSRob Clark	<value value="168" name="A8XX_PERF_SP_LB_READ_ALU_BLOCK_OTHER"/>
1144*9f860dbfSRob Clark	<value value="169" name="A8XX_PERF_SP_LB_WRITE_XFER_VPC"/>
1145*9f860dbfSRob Clark	<value value="170" name="A8XX_PERF_SP_LB_WRITE_VPC_BLOCK_OTHER"/>
1146*9f860dbfSRob Clark	<value value="171" name="A8XX_PERF_SP_LB_LDST_RW_LM"/>
1147*9f860dbfSRob Clark	<value value="172" name="A8XX_PERF_SP_LB_LDST_RW_LM_BLOCKED"/>
1148*9f860dbfSRob Clark	<value value="173" name="A8XX_PERF_SP_LB_LDST_WRITE_CONS"/>
1149*9f860dbfSRob Clark	<value value="174" name="A8XX_PERF_SP_LB_LDST_WRITE_CONS_BLOCKED"/>
1150*9f860dbfSRob Clark	<value value="175" name="A8XX_PERF_SP_GPR_READ_BANK"/>
1151*9f860dbfSRob Clark	<value value="176" name="A8XX_PERF_SP_GPR_WRITE_BANK"/>
1152*9f860dbfSRob Clark	<value value="177" name="A8XX_PERF_SP_VS_WAVE_REQ_PENDING"/>
1153*9f860dbfSRob Clark	<value value="178" name="A8XX_PERF_SP_FS_WAVE_REQ_PENDING"/>
1154*9f860dbfSRob Clark	<value value="179" name="A8XX_PERF_SP_LPAC_WAVE_REQ_PENDING"/>
1155*9f860dbfSRob Clark	<value value="180" name="A8XX_PERF_SP_WAVE_SPLIT_CNT"/>
1156*9f860dbfSRob Clark	<value value="181" name="A8XX_PERF_SP_FS_OOO_WAVE_ACC"/>
1157*9f860dbfSRob Clark	<value value="182" name="A8XX_PERF_SP_SCH_MEM_CTRL_WORKING_CYCLES"/>
1158*9f860dbfSRob Clark	<value value="183" name="A8XX_PERF_SP_LDST_EXECUTION_CYCLES"/>
1159*9f860dbfSRob Clark	<value value="184" name="A8XX_PERF_SP_CCHE_UAV_TOTAL_ATOM_REQ"/>
1160*9f860dbfSRob Clark	<value value="185" name="A8XX_PERF_SP_CCHE_NONUAV_TOTAL_AOM_REQ"/>
1161*9f860dbfSRob Clark	<value value="186" name="A8XX_PERF_SP_TTU_INSTRUCTIONS"/>
1162*9f860dbfSRob Clark	<value value="187" name="A8XX_PERF_SP_TTU_ACTIVE_FIBERS"/>
1163*9f860dbfSRob Clark	<value value="188" name="A8XX_PERF_SP_TTU_BUSY_CYCLES"/>
1164*9f860dbfSRob Clark	<value value="189" name="A8XX_PERF_SP_TTU_GPR_RD_CYCLES"/>
1165*9f860dbfSRob Clark	<value value="190" name="A8XX_PERF_SP_TTU_GPR_RD_REQ"/>
1166*9f860dbfSRob Clark	<value value="191" name="A8XX_PERF_SP_TTU_GPR_WR_CYCLES"/>
1167*9f860dbfSRob Clark	<value value="192" name="A8XX_PERF_SP_TTU_GPR_WR_REQ"/>
1168*9f860dbfSRob Clark	<value value="193" name="A8XX_PERF_SP_GPR_CACHE_SRC0_GPR_RDCNT"/>
1169*9f860dbfSRob Clark	<value value="194" name="A8XX_PERF_SP_GPR_CACHE_SRC0_GPR_CACHE_HIT_RDCNT"/>
1170*9f860dbfSRob Clark	<value value="195" name="A8XX_PERF_SP_GPR_CACHE_SRC0_GPR_CACHE_HINT_RDCNT"/>
1171*9f860dbfSRob Clark	<value value="196" name="A8XX_PERF_SP_GPR_CACHE_SRC1_RDCNT"/>
1172*9f860dbfSRob Clark	<value value="197" name="A8XX_PERF_SP_GPR_CACHE_SRC1_GPR_CACHE_HIT_RDCNT"/>
1173*9f860dbfSRob Clark	<value value="198" name="A8XX_PERF_SP_GPR_CACHE_SRC1_GPR_CACHE_HINT_RDCNT"/>
1174*9f860dbfSRob Clark	<value value="199" name="A8XX_PERF_SP_GPR_CACHE_SRC2_RDCNT"/>
1175*9f860dbfSRob Clark	<value value="200" name="A8XX_PERF_SP_GPR_CACHE_SRC2_GPR_CACHE_HIT_RDCNT"/>
1176*9f860dbfSRob Clark	<value value="201" name="A8XX_PERF_SP_GPR_CACHE_SRC2_GPR_CACHE_HINT_RDCNT"/>
1177*9f860dbfSRob Clark	<value value="202" name="A8XX_PERF_SP_UCHE_READ_BURST"/>
1178*9f860dbfSRob Clark	<value value="203" name="A8XX_PERF_SP_UCHE_WRITE_BURST"/>
1179*9f860dbfSRob Clark	<value value="204" name="A8XX_PERF_SP_LDST_GMEM_REQ_NUM"/>
1180*9f860dbfSRob Clark</enum>
1181*9f860dbfSRob Clark
1182*9f860dbfSRob Clark<enum name="a8xx_rb_perfcounter_select">
1183*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_RB_NEVER_COUNT"/>
1184*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_RB_BUSY_CYCLES"/>
1185*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_RB_STALL_CYCLES_HLSQ"/>
1186*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
1187*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
1188*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
1189*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_RB_STARVE_CYCLES_SP"/>
1190*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
1191*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_RB_STARVE_CYCLES_CCU"/>
1192*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_RB_STARVE_CYCLES_Z_PLANE"/>
1193*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
1194*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_RB_Z_WORKLOAD"/>
1195*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_RB_HLSQ_ACTIVE"/>
1196*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_RB_Z_READ"/>
1197*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_RB_Z_WRITE"/>
1198*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_RB_C_READ"/>
1199*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_RB_C_WRITE"/>
1200*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_RB_TOTAL_PASS"/>
1201*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_RB_Z_PASS"/>
1202*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_RB_Z_FAIL"/>
1203*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_RB_S_FAIL"/>
1204*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_RB_BLENDED_FXP_COMPONENTS"/>
1205*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_RB_BLENDED_FP16_COMPONENTS"/>
1206*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_RB_PS_INVOCATIONS"/>
1207*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_RB_2D_ALIVE_CYCLES"/>
1208*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_RB_2D_STARVE_CYCLES_SP"/>
1209*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_RB_2D_VALID_PIXELS"/>
1210*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_RB_3D_PIXELS"/>
1211*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_RB_BLENDER_WORKING_CYCLES"/>
1212*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_RB_ZPROC_WORKING_CYCLES"/>
1213*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_RB_CPROC_WORKING_CYCLES"/>
1214*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_RB_SAMPLER_WORKING_CYCLES"/>
1215*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
1216*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
1217*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
1218*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
1219*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_RB_STALL_CYCLES_VPC_BE"/>
1220*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_RB_BLENDED_FP32_COMPONENTS"/>
1221*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_RB_COLOR_PIX_TILES"/>
1222*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_RB_STALL_CYCLES_CCU"/>
1223*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_RB_EARLY_Z_ARB3_GRANT"/>
1224*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_RB_LATE_Z_ARB3_GRANT"/>
1225*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_RB_EARLY_Z_SKIP_GRANT"/>
1226*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_RB_VRS_1X1_QUADS"/>
1227*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_RB_VRS_2X1_QUADS"/>
1228*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_RB_VRS_1X2_QUADS"/>
1229*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_RB_VRS_2X2_QUADS"/>
1230*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_RB_VRS_2X4_QUADS"/>
1231*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_RB_VRS_4X2_QUADS"/>
1232*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_RB_VRS_4X4_QUADS"/>
1233*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_RB_STALL_CYCLES_HLSQ_INFO"/>
1234*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_RB_HLSQ_ACTIVE_INFO"/>
1235*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_RB_STALL_CYCLES_HLSQ_ATTR"/>
1236*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_RB_HLSQ_ACTIVE_ATTR"/>
1237*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_RB_STALL_CYCLES_ZMODE_SWITCH"/>
1238*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_RB_TOTAL_PASS_PIXELS"/>
1239*9f860dbfSRob Clark</enum>
1240*9f860dbfSRob Clark
1241*9f860dbfSRob Clark<enum name="a8xx_vsc_perfcounter_select">
1242*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_VSC_NEVER_COUNT"/>
1243*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_VSC_BUSY_CYCLES"/>
1244*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_VSC_WORKING_CYCLES"/>
1245*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_VSC_STALL_CYCLES_UCHE"/>
1246*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_VSC_EOT_NUM"/>
1247*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_VSC_INPUT_TILES"/>
1248*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_VSC_TILE_COMP_TRAN"/>
1249*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_VSC_TILE_BYPASS_TRAN"/>
1250*9f860dbfSRob Clark</enum>
1251*9f860dbfSRob Clark
1252*9f860dbfSRob Clark<enum name="a8xx_ccu_perfcounter_select">
1253*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_CCU_NEVER_COUNT"/>
1254*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_CCU_BUSY_CYCLES"/>
1255*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
1256*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
1257*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_CCU_DEPTH_BLOCKS"/>
1258*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_CCU_COLOR_BLOCKS"/>
1259*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_CCU_DEPTH_BLOCK_HIT"/>
1260*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_CCU_COLOR_BLOCK_HIT"/>
1261*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_CCU_PARTIAL_BLOCK_READ"/>
1262*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_CCU_GMEM_READ"/>
1263*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_CCU_GMEM_WRITE"/>
1264*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_CCU_2D_RD_REQ"/>
1265*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_CCU_2D_WR_REQ"/>
1266*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_CCU_UBWC_COLOR_BLOCKS_CONCURRENT"/>
1267*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_CCU_UBWC_DEPTH_BLOCKS_CONCURRENT"/>
1268*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_CCU_COLOR_RESOLVE_DROPPED"/>
1269*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_CCU_DEPTH_RESOLVE_DROPPED"/>
1270*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_CCU_COLOR_RENDER_CONCURRENT"/>
1271*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_CCU_DEPTH_RENDER_CONCURRENT"/>
1272*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_CCU_COLOR_RESOLVE_AFTER_RENDER"/>
1273*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_CCU_DEPTH_RESOLVE_AFTER_RENDER"/>
1274*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_CCU_GMEM_EXTRA_DEPTH_READ"/>
1275*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_CCU_GMEM_COLOR_READ_4AA"/>
1276*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_CCU_GMEM_COLOR_READ_4AA_FULL"/>
1277*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_CCU_COLOR_EVB_STALL"/>
1278*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_CCU_RENDER_OVERLAP_CRE_C"/>
1279*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_CCU_RENDER_OVERLAP_CRE_Z"/>
1280*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_CCU_RENDER_STALL_BY_CRE_C"/>
1281*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_CCU_RENDER_STALL_BY_CRE_Z"/>
1282*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_CCU_FULL_SURFACE_RESOLVE_CYCLES"/>
1283*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_CCU_RENDER_OVERLAP_FULL_SURFACE_RESOLVE"/>
1284*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_CCU_STALL_BY_FULL_SURFACE_RESOLVE"/>
1285*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_CCU_CONCURRENT_RESOLVE_CYCLES"/>
1286*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_CCU_GMEM_BK2BK_STALL"/>
1287*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_CCU_RESERVED_34"/>
1288*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_CCU_RESERVED_35"/>
1289*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_CCU_RESERVED_36"/>
1290*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_CCU_RESERVED_37"/>
1291*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_CCU_RESERVED_38"/>
1292*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_CCU_RESERVED_39"/>
1293*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_CCU_RESERVED_40"/>
1294*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_CCU_RESERVED_41"/>
1295*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_CCU_RESERVED_42"/>
1296*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_CCU_RESERVED_43"/>
1297*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_CCU_RESERVED_44"/>
1298*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_CCU_RESERVED_45"/>
1299*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_CCU_RESERVED_46"/>
1300*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_CCU_RESERVED_47"/>
1301*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_CCU_RESERVED_48"/>
1302*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_CCU_RESERVED_49"/>
1303*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_CCU_RESERVED_50"/>
1304*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_CCU_RESERVED_51"/>
1305*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_CCU_RESERVED_52"/>
1306*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_CCU_RESERVED_53"/>
1307*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_CCU_RESERVED_54"/>
1308*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_CCU_RESERVED_55"/>
1309*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_CCU_RESERVED_56"/>
1310*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_CCU_RESERVED_57"/>
1311*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_CCU_RESERVED_58"/>
1312*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_CCU_RESERVED_59"/>
1313*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_CCU_RESERVED_60"/>
1314*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_CCU_RESERVED_61"/>
1315*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_CCU_RESERVED_62"/>
1316*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_CCU_RESERVED_63"/>
1317*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_UFC_L0_TP_HINT_REQUESTS"/>
1318*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_UFC_L0_TP_HINT_TAG_MISS"/>
1319*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_UFC_L0_TP_HINT_TAG_HIT_RDY"/>
1320*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_UFC_L0_TP_HINT_TAG_HIT_NRDY"/>
1321*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_UFC_L0_TP_HINT_IS_FCLEAR"/>
1322*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_UFC_L0_TP_HINT_IS_ALPHA0"/>
1323*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_UFC_L0_TP_HINT_IS_ALPHA1"/>
1324*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_UFC_L0_TP_HINT_IS_UNCOMP"/>
1325*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_UFC_L0_SP_REQUESTS"/>
1326*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_UFC_L0_SP_FILTER_HIT"/>
1327*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_UFC_L0_SP_FILTER_MISS"/>
1328*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_UFC_L0_SP_REQ_STALLED_CYCLES"/>
1329*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_UFC_L0_TP_REQ_STALLED_CYCLES"/>
1330*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_UFC_L0_TP_RTN_STALLED_CYCLES"/>
1331*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_CCU_RESERVED_78"/>
1332*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_CCU_RESERVED_79"/>
1333*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_CCU_RESERVED_80"/>
1334*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_CCU_RESERVED_81"/>
1335*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_CCU_RESERVED_82"/>
1336*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_CCU_RESERVED_83"/>
1337*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_CCU_RESERVED_84"/>
1338*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_CCU_RESERVED_85"/>
1339*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_CCU_RESERVED_86"/>
1340*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_CCU_RESERVED_87"/>
1341*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_CCU_RESERVED_88"/>
1342*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_CCU_RESERVED_89"/>
1343*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_CCU_RESERVED_90"/>
1344*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_CCU_RESERVED_91"/>
1345*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_CCU_RESERVED_92"/>
1346*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_CCU_RESERVED_93"/>
1347*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_CCU_RESERVED_94"/>
1348*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_CCU_RESERVED_95"/>
1349*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_CCU_RESERVED_96"/>
1350*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_CCU_RESERVED_97"/>
1351*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_CCU_RESERVED_98"/>
1352*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_CCU_RESERVED_99"/>
1353*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_CCU_RESERVED_100"/>
1354*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_CCU_RESERVED_101"/>
1355*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_CCU_RESERVED_102"/>
1356*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_CCU_RESERVED_103"/>
1357*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_CCU_RESERVED_104"/>
1358*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_CCU_RESERVED_105"/>
1359*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_CCU_RESERVED_106"/>
1360*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_CCU_RESERVED_107"/>
1361*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_CCU_RESERVED_108"/>
1362*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_CCU_RESERVED_109"/>
1363*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_CCU_RESERVED_110"/>
1364*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_CCU_RESERVED_111"/>
1365*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_CCU_RESERVED_112"/>
1366*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_CCU_RESERVED_113"/>
1367*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_CCU_RESERVED_114"/>
1368*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_CCU_RESERVED_115"/>
1369*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_CCU_RESERVED_116"/>
1370*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_CCU_RESERVED_117"/>
1371*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_CCU_RESERVED_118"/>
1372*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_CCU_RESERVED_119"/>
1373*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_CCU_RESERVED_120"/>
1374*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_CCU_RESERVED_121"/>
1375*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_CCU_RESERVED_122"/>
1376*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_CCU_RESERVED_123"/>
1377*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_CCU_RESERVED_124"/>
1378*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_CCU_RESERVED_125"/>
1379*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_CCU_RESERVED_126"/>
1380*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_CCU_RESERVED_127"/>
1381*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_CRE_RESOLVE_EVENTS"/>
1382*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_CRE_CONCURRENT_RESOLVE_EVENTS"/>
1383*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_CRE_DROPPED_CLEAR_EVENTS"/>
1384*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_CRE_ST_BLOCKS_CONCURRENT"/>
1385*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_CRE_LRZ_ST_BLOCKS_CONCURRENT"/>
1386*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_CRE_SP_UFC_PREFETCH_REQUESTS"/>
1387*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_CRE_RESOLVE_CDP_PREFETCH_REQUESTS"/>
1388*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_CRE_RESOLVE_UFC_PREFETCH_REQUESTS"/>
1389*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_CRE_DR_UFC_PREFTCH_REQUESTS"/>
1390*9f860dbfSRob Clark</enum>
1391*9f860dbfSRob Clark
1392*9f860dbfSRob Clark<enum name="a8xx_lrz_perfcounter_select">
1393*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_LRZ_NEVER_COUNT"/>
1394*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_LRZ_BUSY_CYCLES"/>
1395*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_LRZ_STARVE_CYCLES_RAS"/>
1396*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_LRZ_STALL_CYCLES_RB"/>
1397*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_LRZ_STALL_CYCLES_VSC"/>
1398*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_LRZ_STALL_CYCLES_VPC_BE"/>
1399*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_LRZ_STALL_CYCLES_FLAG_ACR"/>
1400*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_LRZ_STALL_CYCLES_UCHE"/>
1401*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_LRZ_LRZ_READ"/>
1402*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_LRZ_LRZ_WRITE"/>
1403*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_LRZ_READ_LATENCY"/>
1404*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_LRZ_MERGE_CACHE_UPDATING"/>
1405*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
1406*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
1407*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
1408*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_LRZ_FULL_8X8_TILES"/>
1409*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_LRZ_PARTIAL_8X8_TILES"/>
1410*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_LRZ_TILE_KILLED"/>
1411*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_LRZ_TOTAL_PIXEL"/>
1412*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
1413*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_LRZ_FEEDBACK_ACCEPT"/>
1414*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_LRZ_FEEDBACK_DISCARD"/>
1415*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_LRZ_FEEDBACK_STALL"/>
1416*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
1417*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
1418*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_LRZ_RAS_MASK_TRANS"/>
1419*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_LRZ_STALL_CYCLES_MVC"/>
1420*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_LRZ_TILE_KILLED_BY_IMAGE_VRS"/>
1421*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_LRZ_TILE_KILLED_BY_Z"/>
1422*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_LRZ_STALL_CYCLES_HLSQ_BATCH"/>
1423*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_LRZ_NUM_FLOCK"/>
1424*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_LRZ_DRAWS_TOTAL"/>
1425*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_LRZ_DRAWS_LRZ_DIS"/>
1426*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_LRZ_DRAWS_LRZ_WRITE_DIS"/>
1427*9f860dbfSRob Clark</enum>
1428*9f860dbfSRob Clark
1429*9f860dbfSRob Clark<enum name="a8xx_cmp_perfcounter_select">
1430*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_CMPDECMP_NEVER_COUNT"/>
1431*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_CMPDECMP_STALL_CYCLES_ARB"/>
1432*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
1433*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
1434*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
1435*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
1436*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_CMPDECMP_VBIF_READ_REQUEST"/>
1437*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
1438*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_CMPDECMP_VBIF_READ_DATA"/>
1439*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_CMPDECMP_VBIF_WRITE_DATA"/>
1440*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
1441*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
1442*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
1443*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
1444*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
1445*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
1446*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
1447*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
1448*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
1449*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
1450*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
1451*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
1452*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
1453*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
1454*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
1455*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
1456*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
1457*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
1458*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
1459*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
1460*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_CMPDECMP_CDP_FILTER_HIT"/>
1461*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_CMPDECMP_CDP_FILTER_MISS"/>
1462*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG0_COUNT"/>
1463*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG1_COUNT"/>
1464*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG2_COUNT"/>
1465*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG3_COUNT"/>
1466*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG4_COUNT"/>
1467*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG5_COUNT"/>
1468*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG6_COUNT"/>
1469*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG8_COUNT"/>
1470*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG0_COUNT"/>
1471*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG1_COUNT"/>
1472*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG2_COUNT"/>
1473*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG3_COUNT"/>
1474*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG4_COUNT"/>
1475*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG5_COUNT"/>
1476*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG6_COUNT"/>
1477*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG8_COUNT"/>
1478*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_CMPDECMP_UFC_REQ_CCU"/>
1479*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_CMPDECMP_UFC_REQ_UCHE"/>
1480*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_CMPDECMP_INPUT_STALL_CYCLES_ENC"/>
1481*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_CMPDECMP_ENC_STALL_CYCLES_UFC"/>
1482*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_CMPDECMP_ENC_STALL_CYCLES_GBIF_DATA"/>
1483*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_CMPDECMP_ENC_STALL_CYCLES_GBIF_CMD"/>
1484*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_CMPDECMP_INPUT_STALL_CYCLES_DEC"/>
1485*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_CMPDECMP_DEC_STALL_CYCLES_OUTPUT"/>
1486*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_CMPDECMP_REQ_SSEC_FLAG_COMP"/>
1487*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_CMPDECMP_CCU_EVENT_SKEW_STALL"/>
1488*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_CMPDECMP_CCU_BV_EVENT_SKEW_STALL"/>
1489*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_CMPDECMP_DEPTH_WRITE_FLAG7_COUNT"/>
1490*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_CMPDECMP_COLOR_WRITE_FLAG7_COUNT"/>
1491*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_CMPDECMP_DEPTH_READ_FLAG7_COUNT"/>
1492*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_CMPDECMP_COLOR_READ_FLAG7_COUNT"/>
1493*9f860dbfSRob Clark</enum>
1494*9f860dbfSRob Clark
1495*9f860dbfSRob Clark<enum name="a8xx_gbif_perfcounter_select">
1496*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_GBIF_NEVER_COUNT"/>
1497*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_GBIF_RESERVED_1"/>
1498*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_GBIF_RESERVED_2"/>
1499*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_GBIF_RESERVED_3"/>
1500*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_GBIF_RESERVED_4"/>
1501*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_GBIF_RESERVED_5"/>
1502*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_GBIF_RESERVED_6"/>
1503*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_GBIF_RESERVED_7"/>
1504*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_GBIF_RESERVED_8"/>
1505*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_GBIF_RESERVED_9"/>
1506*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_GBIF_AXI0_READ_REQUESTS_TOTAL"/>
1507*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_GBIF_AXI1_READ_REQUESTS_TOTAL"/>
1508*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_GBIF_RESERVED_12"/>
1509*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_GBIF_RESERVED_13"/>
1510*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_GBIF_RESERVED_14"/>
1511*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_GBIF_RESERVED_15"/>
1512*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_GBIF_RESERVED_16"/>
1513*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_GBIF_RESERVED_17"/>
1514*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_GBIF_RESERVED_18"/>
1515*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_GBIF_RESERVED_19"/>
1516*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_GBIF_RESERVED_20"/>
1517*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_GBIF_RESERVED_21"/>
1518*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_GBIF_AXI0_WRITE_REQUESTS_TOTAL"/>
1519*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_GBIF_AXI1_WRITE_REQUESTS_TOTAL"/>
1520*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_GBIF_RESERVED_24"/>
1521*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_GBIF_RESERVED_25"/>
1522*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_GBIF_RESERVED_26"/>
1523*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_GBIF_RESERVED_27"/>
1524*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_GBIF_RESERVED_28"/>
1525*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_GBIF_RESERVED_29"/>
1526*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_GBIF_RESERVED_30"/>
1527*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_GBIF_RESERVED_31"/>
1528*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_GBIF_RESERVED_32"/>
1529*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_GBIF_RESERVED_33"/>
1530*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_GBIF_AXI0_READ_DATA_BEATS_TOTAL"/>
1531*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_GBIF_AXI1_READ_DATA_BEATS_TOTAL"/>
1532*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_GBIF_RESERVED_36"/>
1533*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_GBIF_RESERVED_37"/>
1534*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_GBIF_RESERVED_38"/>
1535*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_GBIF_RESERVED_39"/>
1536*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_GBIF_RESERVED_40"/>
1537*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_GBIF_RESERVED_41"/>
1538*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_GBIF_RESERVED_42"/>
1539*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_GBIF_RESERVED_43"/>
1540*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_GBIF_RESERVED_44"/>
1541*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_GBIF_RESERVED_45"/>
1542*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_GBIF_AXI0_WRITE_DATA_BEATS_TOTAL"/>
1543*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_GBIF_AXI1_WRITE_DATA_BEATS_TOTAL"/>
1544*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_GBIF_RESERVED_48"/>
1545*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_GBIF_RESERVED_49"/>
1546*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_GBIF_RESERVED_50"/>
1547*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_GBIF_RESERVED_51"/>
1548*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_GBIF_RESERVED_52"/>
1549*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_GBIF_RESERVED_53"/>
1550*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_GBIF_RESERVED_54"/>
1551*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_GBIF_RESERVED_55"/>
1552*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_GBIF_RESERVED_56"/>
1553*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_GBIF_RESERVED_57"/>
1554*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_GBIF_RESERVED_58"/>
1555*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_GBIF_RESERVED_59"/>
1556*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_GBIF_RESERVED_60"/>
1557*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_GBIF_RESERVED_61"/>
1558*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_GBIF_RESERVED_62"/>
1559*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_GBIF_RESERVED_63"/>
1560*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_GBIF_RESERVED_64"/>
1561*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_GBIF_RESERVED_65"/>
1562*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_GBIF_RESERVED_66"/>
1563*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_GBIF_RESERVED_67"/>
1564*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_RD_ALL"/>
1565*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_RD_ALL"/>
1566*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_GBIF_CYCLES_CH0_HELD_OFF_WR_ALL"/>
1567*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_GBIF_CYCLES_CH1_HELD_OFF_WR_ALL"/>
1568*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_GBIF_AXI_CH0_REQUEST_HELD_OFF"/>
1569*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_GBIF_AXI_CH1_REQUEST_HELD_OFF"/>
1570*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_GBIF_AXI_REQUEST_HELD_OFF"/>
1571*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_GBIF_AXI_CH0_WRITE_DATA_HELD_OFF"/>
1572*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_GBIF_AXI_CH1_WRITE_DATA_HELD_OFF"/>
1573*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_GBIF_AXI_ALL_WRITE_DATA_HELD_OFF"/>
1574*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_GBIF_RESERVED_78"/>
1575*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_GBIF_RESERVED_79"/>
1576*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_GBIF_RESERVED_80"/>
1577*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_GBIF_RESERVED_81"/>
1578*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_GBIF_RESERVED_82"/>
1579*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_GBIF_RESERVED_83"/>
1580*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_GBIF_RESERVED_84"/>
1581*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_GBIF_RESERVED_85"/>
1582*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_GBIF_RESERVED_86"/>
1583*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_GBIF_RESERVED_87"/>
1584*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_GBIF_AXI2_READ_REQUESTS_TOTAL"/>
1585*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_GBIF_AXI3_READ_REQUESTS_TOTAL"/>
1586*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_GBIF_RESERVED_90"/>
1587*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_GBIF_RESERVED_91"/>
1588*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_GBIF_RESERVED_92"/>
1589*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_GBIF_RESERVED_93"/>
1590*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_GBIF_RESERVED_94"/>
1591*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_GBIF_RESERVED_95"/>
1592*9f860dbfSRob Clark	<value value="96" name="A8XX_PERF_GBIF_RESERVED_96"/>
1593*9f860dbfSRob Clark	<value value="97" name="A8XX_PERF_GBIF_RESERVED_97"/>
1594*9f860dbfSRob Clark	<value value="98" name="A8XX_PERF_GBIF_RESERVED_98"/>
1595*9f860dbfSRob Clark	<value value="99" name="A8XX_PERF_GBIF_RESERVED_99"/>
1596*9f860dbfSRob Clark	<value value="100" name="A8XX_PERF_GBIF_AXI2_WRITE_REQUESTS_TOTAL"/>
1597*9f860dbfSRob Clark	<value value="101" name="A8XX_PERF_GBIF_AXI3_WRITE_REQUESTS_TOTAL"/>
1598*9f860dbfSRob Clark	<value value="102" name="A8XX_PERF_GBIF_RESERVED_102"/>
1599*9f860dbfSRob Clark	<value value="103" name="A8XX_PERF_GBIF_RESERVED_103"/>
1600*9f860dbfSRob Clark	<value value="104" name="A8XX_PERF_GBIF_RESERVED_104"/>
1601*9f860dbfSRob Clark	<value value="105" name="A8XX_PERF_GBIF_RESERVED_105"/>
1602*9f860dbfSRob Clark	<value value="106" name="A8XX_PERF_GBIF_RESERVED_106"/>
1603*9f860dbfSRob Clark	<value value="107" name="A8XX_PERF_GBIF_RESERVED_107"/>
1604*9f860dbfSRob Clark	<value value="108" name="A8XX_PERF_GBIF_RESERVED_108"/>
1605*9f860dbfSRob Clark	<value value="109" name="A8XX_PERF_GBIF_RESERVED_109"/>
1606*9f860dbfSRob Clark	<value value="110" name="A8XX_PERF_GBIF_RESERVED_110"/>
1607*9f860dbfSRob Clark	<value value="111" name="A8XX_PERF_GBIF_RESERVED_111"/>
1608*9f860dbfSRob Clark	<value value="112" name="A8XX_PERF_GBIF_AXI2_READ_DATA_BEATS_TOTAL"/>
1609*9f860dbfSRob Clark	<value value="113" name="A8XX_PERF_GBIF_AXI3_READ_DATA_BEATS_TOTAL"/>
1610*9f860dbfSRob Clark	<value value="114" name="A8XX_PERF_GBIF_RESERVED_114"/>
1611*9f860dbfSRob Clark	<value value="115" name="A8XX_PERF_GBIF_RESERVED_115"/>
1612*9f860dbfSRob Clark	<value value="116" name="A8XX_PERF_GBIF_RESERVED_116"/>
1613*9f860dbfSRob Clark	<value value="117" name="A8XX_PERF_GBIF_RESERVED_117"/>
1614*9f860dbfSRob Clark	<value value="118" name="A8XX_PERF_GBIF_RESERVED_118"/>
1615*9f860dbfSRob Clark	<value value="119" name="A8XX_PERF_GBIF_RESERVED_119"/>
1616*9f860dbfSRob Clark	<value value="120" name="A8XX_PERF_GBIF_RESERVED_120"/>
1617*9f860dbfSRob Clark	<value value="121" name="A8XX_PERF_GBIF_RESERVED_121"/>
1618*9f860dbfSRob Clark	<value value="122" name="A8XX_PERF_GBIF_RESERVED_122"/>
1619*9f860dbfSRob Clark	<value value="123" name="A8XX_PERF_GBIF_RESERVED_123"/>
1620*9f860dbfSRob Clark	<value value="124" name="A8XX_PERF_GBIF_AXI2_WRITE_DATA_BEATS_TOTAL"/>
1621*9f860dbfSRob Clark	<value value="125" name="A8XX_PERF_GBIF_AXI3_WRITE_DATA_BEATS_TOTAL"/>
1622*9f860dbfSRob Clark	<value value="126" name="A8XX_PERF_GBIF_RESERVED_126"/>
1623*9f860dbfSRob Clark	<value value="127" name="A8XX_PERF_GBIF_RESERVED_127"/>
1624*9f860dbfSRob Clark	<value value="128" name="A8XX_PERF_GBIF_RESERVED_128"/>
1625*9f860dbfSRob Clark	<value value="129" name="A8XX_PERF_GBIF_RESERVED_129"/>
1626*9f860dbfSRob Clark	<value value="130" name="A8XX_PERF_GBIF_RESERVED_130"/>
1627*9f860dbfSRob Clark	<value value="131" name="A8XX_PERF_GBIF_RESERVED_131"/>
1628*9f860dbfSRob Clark	<value value="132" name="A8XX_PERF_GBIF_RESERVED_132"/>
1629*9f860dbfSRob Clark	<value value="133" name="A8XX_PERF_GBIF_RESERVED_133"/>
1630*9f860dbfSRob Clark	<value value="134" name="A8XX_PERF_GBIF_RESERVED_134"/>
1631*9f860dbfSRob Clark	<value value="135" name="A8XX_PERF_GBIF_RESERVED_135"/>
1632*9f860dbfSRob Clark	<value value="136" name="A8XX_PERF_GBIF_RESERVED_136"/>
1633*9f860dbfSRob Clark	<value value="137" name="A8XX_PERF_GBIF_RESERVED_137"/>
1634*9f860dbfSRob Clark	<value value="138" name="A8XX_PERF_GBIF_RESERVED_138"/>
1635*9f860dbfSRob Clark	<value value="139" name="A8XX_PERF_GBIF_RESERVED_139"/>
1636*9f860dbfSRob Clark	<value value="140" name="A8XX_PERF_GBIF_RESERVED_140"/>
1637*9f860dbfSRob Clark	<value value="141" name="A8XX_PERF_GBIF_RESERVED_141"/>
1638*9f860dbfSRob Clark	<value value="142" name="A8XX_PERF_GBIF_RESERVED_142"/>
1639*9f860dbfSRob Clark	<value value="143" name="A8XX_PERF_GBIF_RESERVED_143"/>
1640*9f860dbfSRob Clark	<value value="144" name="A8XX_PERF_GBIF_RESERVED_144"/>
1641*9f860dbfSRob Clark	<value value="145" name="A8XX_PERF_GBIF_RESERVED_145"/>
1642*9f860dbfSRob Clark	<value value="146" name="A8XX_PERF_GBIF_RESERVED_146"/>
1643*9f860dbfSRob Clark	<value value="147" name="A8XX_PERF_GBIF_RESERVED_147"/>
1644*9f860dbfSRob Clark	<value value="148" name="A8XX_PERF_GBIF_RESERVED_148"/>
1645*9f860dbfSRob Clark	<value value="149" name="A8XX_PERF_GBIF_RESERVED_149"/>
1646*9f860dbfSRob Clark	<value value="150" name="A8XX_PERF_GBIF_READ_BEAT_ALL_CHANNELS"/>
1647*9f860dbfSRob Clark	<value value="151" name="A8XX_PERF_GBIF_WRITE_BEAT_ALL_CHANNELS"/>
1648*9f860dbfSRob Clark	<value value="152" name="A8XX_PERF_GBIF_READ_AND_WRITE_BEAT_ALL_CHANNELS"/>
1649*9f860dbfSRob Clark	<value value="153" name="A8XX_PERF_GBIF_RESERVED_153"/>
1650*9f860dbfSRob Clark	<value value="154" name="A8XX_PERF_GBIF_RESERVED_154"/>
1651*9f860dbfSRob Clark	<value value="155" name="A8XX_PERF_GBIF_RESERVED_155"/>
1652*9f860dbfSRob Clark	<value value="156" name="A8XX_PERF_GBIF_CYCLES_CH2_HELD_OFF_RD_ALL"/>
1653*9f860dbfSRob Clark	<value value="157" name="A8XX_PERF_GBIF_CYCLES_CH3_HELD_OFF_RD_ALL"/>
1654*9f860dbfSRob Clark	<value value="158" name="A8XX_PERF_GBIF_CYCLES_CH2_HELD_OFF_WR_ALL"/>
1655*9f860dbfSRob Clark	<value value="159" name="A8XX_PERF_GBIF_CYCLES_CH3_HELD_OFF_WR_ALL"/>
1656*9f860dbfSRob Clark	<value value="160" name="A8XX_PERF_GBIF_AXI_CH2_REQUEST_HELD_OFF"/>
1657*9f860dbfSRob Clark	<value value="161" name="A8XX_PERF_GBIF_AXI_CH3_REQUEST_HELD_OFF"/>
1658*9f860dbfSRob Clark	<value value="162" name="A8XX_PERF_GBIF_AXI_CH2_WRITE_DATA_HELD_OFF"/>
1659*9f860dbfSRob Clark	<value value="163" name="A8XX_PERF_GBIF_AXI_CH3_WRITE_DATA_HELD_OFF"/>
1660*9f860dbfSRob Clark	<value value="164" name="A8XX_PERF_GBIF_AXI_CH0_READ_PENDING_SUM"/>
1661*9f860dbfSRob Clark	<value value="165" name="A8XX_PERF_GBIF_AXI_CH1_READ_PENDING_SUM"/>
1662*9f860dbfSRob Clark	<value value="166" name="A8XX_PERF_GBIF_AXI_CH2_READ_PENDING_SUM"/>
1663*9f860dbfSRob Clark	<value value="167" name="A8XX_PERF_GBIF_AXI_CH3_READ_PENDING_SUM"/>
1664*9f860dbfSRob Clark	<value value="168" name="A8XX_PERF_GBIF_AXI_CH0_WRITE_PENDING_SUM"/>
1665*9f860dbfSRob Clark	<value value="169" name="A8XX_PERF_GBIF_AXI_CH1_WRITE_PENDING_SUM"/>
1666*9f860dbfSRob Clark	<value value="170" name="A8XX_PERF_GBIF_AXI_CH2_WRITE_PENDING_SUM"/>
1667*9f860dbfSRob Clark	<value value="171" name="A8XX_PERF_GBIF_AXI_CH3_WRITE_PENDING_SUM"/>
1668*9f860dbfSRob Clark	<value value="172" name="A8XX_PERF_GBIF_SMMU_RD_REQ_SAMPLES_CH0"/>
1669*9f860dbfSRob Clark	<value value="173" name="A8XX_PERF_GBIF_SMMU_RD_REQ_CYCLES_CH0"/>
1670*9f860dbfSRob Clark	<value value="174" name="A8XX_PERF_GBIF_RBUF_RD_REQ_SAMPLES_CH0"/>
1671*9f860dbfSRob Clark	<value value="175" name="A8XX_PERF_GBIF_RBUF_RD_REQ_CYCLES_CH0"/>
1672*9f860dbfSRob Clark	<value value="176" name="A8XX_PERF_GBIF_RBUF_UTIL_SAMPLES_CH0"/>
1673*9f860dbfSRob Clark	<value value="177" name="A8XX_PERF_GBIF_RBUF_BUSY_CYCLES_CH0"/>
1674*9f860dbfSRob Clark	<value value="178" name="A8XX_PERF_GBIF_RTABLE_OT_UTIL_SAMPLES_CH0"/>
1675*9f860dbfSRob Clark	<value value="179" name="A8XX_PERF_GBIF_SMMU_RD_REQ_SAMPLES_CH1"/>
1676*9f860dbfSRob Clark	<value value="180" name="A8XX_PERF_GBIF_SMMU_RD_REQ_CYCLES_CH1"/>
1677*9f860dbfSRob Clark	<value value="181" name="A8XX_PERF_GBIF_RBUF_RD_REQ_SAMPLES_CH1"/>
1678*9f860dbfSRob Clark	<value value="182" name="A8XX_PERF_GBIF_RBUF_RD_REQ_CYCLES_CH1"/>
1679*9f860dbfSRob Clark	<value value="183" name="A8XX_PERF_GBIF_RBUF_UTIL_SAMPLES_CH1"/>
1680*9f860dbfSRob Clark	<value value="184" name="A8XX_PERF_GBIF_RBUF_BUSY_CYCLES_CH1"/>
1681*9f860dbfSRob Clark	<value value="185" name="A8XX_PERF_GBIF_RTABLE_OT_UTIL_SAMPLES_CH1"/>
1682*9f860dbfSRob Clark	<value value="186" name="A8XX_PERF_GBIF_SMMU_RD_REQ_SAMPLES_CH2"/>
1683*9f860dbfSRob Clark	<value value="187" name="A8XX_PERF_GBIF_SMMU_RD_REQ_CYCLES_CH2"/>
1684*9f860dbfSRob Clark	<value value="188" name="A8XX_PERF_GBIF_RBUF_RD_REQ_SAMPLES_CH2"/>
1685*9f860dbfSRob Clark	<value value="189" name="A8XX_PERF_GBIF_RBUF_RD_REQ_CYCLES_CH2"/>
1686*9f860dbfSRob Clark	<value value="190" name="A8XX_PERF_GBIF_RBUF_UTIL_SAMPLES_CH2"/>
1687*9f860dbfSRob Clark	<value value="191" name="A8XX_PERF_GBIF_RBUF_BUSY_CYCLES_CH2"/>
1688*9f860dbfSRob Clark	<value value="192" name="A8XX_PERF_GBIF_RTABLE_OT_UTIL_SAMPLES_CH2"/>
1689*9f860dbfSRob Clark	<value value="193" name="A8XX_PERF_GBIF_SMMU_RD_REQ_SAMPLES_CH3"/>
1690*9f860dbfSRob Clark	<value value="194" name="A8XX_PERF_GBIF_SMMU_RD_REQ_CYCLES_CH3"/>
1691*9f860dbfSRob Clark	<value value="195" name="A8XX_PERF_GBIF_RBUF_RD_REQ_SAMPLES_CH3"/>
1692*9f860dbfSRob Clark	<value value="196" name="A8XX_PERF_GBIF_RBUF_RD_REQ_CYCLES_CH3"/>
1693*9f860dbfSRob Clark	<value value="197" name="A8XX_PERF_GBIF_RBUF_UTIL_SAMPLES_CH3"/>
1694*9f860dbfSRob Clark	<value value="198" name="A8XX_PERF_GBIF_RBUF_BUSY_CYCLES_CH3"/>
1695*9f860dbfSRob Clark	<value value="199" name="A8XX_PERF_GBIF_RTABLE_OT_UTIL_SAMPLES_CH3"/>
1696*9f860dbfSRob Clark</enum>
1697*9f860dbfSRob Clark
1698*9f860dbfSRob Clark<enum name="a8xx_gbif_pwr_perfcounter_select">
1699*9f860dbfSRob Clark	<value value="0" name="A8XX_M0_STALL"/>
1700*9f860dbfSRob Clark	<value value="1" name="A8XX_M1_STALL"/>
1701*9f860dbfSRob Clark	<value value="2" name="A8XX_M0_NO_CLIENT_REQ"/>
1702*9f860dbfSRob Clark	<value value="3" name="A8XX_M1_NO_CLIENT_REQ"/>
1703*9f860dbfSRob Clark</enum>
1704*9f860dbfSRob Clark
1705*9f860dbfSRob Clark<enum name="a8xx_alwayson_perfcounter_select">
1706*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_ALWAYSON"/>
1707*9f860dbfSRob Clark</enum>
1708*9f860dbfSRob Clark
1709*9f860dbfSRob Clark<enum name="a8xx_gmu_xoclk_perfcounter_select">
1710*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_GMU_XOCLK_NO_COUNT"/>
1711*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_GMU_PWC_GPU_TOP_POWER_ON_CYCLES"/>
1712*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_GMU_PWC_GPU_TOP_POWER_OFF_SWITCHING_CYCLES"/>
1713*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_GMU_PWC_GPU_TOP_POWER_OFF_CYCLES"/>
1714*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_GMU_PWC_GPU_TOP_POWER_ON_SWITCHING_CYCLES"/>
1715*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_GMU_PWC_GPU_TOP_POWER_COLLAPSED"/>
1716*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_GMU_PWC_SPTPRAC_POWER_ON_CYCLES"/>
1717*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_GMU_PWC_SPTPRAC_POWER_OFF_SWITCHING_CYCLES"/>
1718*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_GMU_PWC_SPTPRAC_POWER_OFF_CYCLES"/>
1719*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_GMU_PWC_SPTPRAC_POWER_ON_SWITCHING_CYCLES"/>
1720*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_GMU_PWC_SPTPRAC_POWER_COLLAPSED"/>
1721*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_GMU_PWC_GPU_TOP_IDLE_PHASE1_IN_LATENCY"/>
1722*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_GMU_PWC_GPU_TOP_IDLE_PHASE2_IN_LATENCY"/>
1723*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_GMU_PWC_GPU_TOP_IDLE_PHASE1_OUT_LATENCY"/>
1724*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_GMU_PWC_GPU_TOP_IDLE_PHASE2_OUT_LATENCY"/>
1725*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_GMU_PWC_TOTAL_THROTTLED_CYCLES"/>
1726*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_0"/>
1727*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_1"/>
1728*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_2"/>
1729*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_3"/>
1730*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_4"/>
1731*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_5"/>
1732*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_6"/>
1733*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_7"/>
1734*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_8"/>
1735*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_9"/>
1736*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_GMU_PWC_NUM_GDPM_EPOCH_TOO_SHORT_INTR"/>
1737*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_GMU_PWC_NUM_GDPM_INVALID_OPCODE_INTR"/>
1738*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_GMU_PWC_NUM_MAX_THRESHOLD_BREACH"/>
1739*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_GMU_PWC_NUM_MIN_THRESHOLD_BREACH"/>
1740*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_GMU_PWC_CYCLE_MAX_THRESHOLD_BREACH"/>
1741*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_GMU_PWC_CYCLE_MIN_THRESHOLD_BREACH"/>
1742*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_GMU_PWC_GPU_BUSY_CYCLES"/>
1743*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_GMU_PWC_CYCLE_ALM_LOW_THROTTLE_CYCLES"/>
1744*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_GMU_PWC_CYCLE_ALM_HIGH_THROTTLE_CYCLES"/>
1745*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_10"/>
1746*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_GMU_PWC_SID_N_TOTAL_THROTTLED_CYCLES_11"/>
1747*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_GMU_PWC_CLX_TOTAL_THROTTLE_CYCLES"/>
1748*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_GMU_PWC_BCL_TOTAL_THROTTLE_CYCLES"/>
1749*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_GMU_PWC_MSG2_CLX_TOTAL_THROTTLE_CYCLES"/>
1750*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_GMU_XOCLK_RESERVED_40"/>
1751*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_GMU_XOCLK_RESERVED_41"/>
1752*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_GMU_XOCLK_RESERVED_42"/>
1753*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_GMU_XOCLK_RESERVED_43"/>
1754*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_GMU_XOCLK_RESERVED_44"/>
1755*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_GMU_XOCLK_RESERVED_45"/>
1756*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_GMU_XOCLK_RESERVED_46"/>
1757*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_GMU_XOCLK_RESERVED_47"/>
1758*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_GMU_PWC_LPAC_BUSY_CYCLES"/>
1759*9f860dbfSRob Clark	<value value="49" name="A8XX_PERF_GMU_PWC_GPU_OR_LPAC_BUSY_CYCLES"/>
1760*9f860dbfSRob Clark	<value value="50" name="A8XX_PERF_GMU_PWC_GX_THROTTLE_VIOLATION_CNT"/>
1761*9f860dbfSRob Clark	<value value="51" name="A8XX_PERF_GMU_PWC_MX_THROTTLE_VIOLATION_CNT"/>
1762*9f860dbfSRob Clark	<value value="52" name="A8XX_PERF_GMU_PWC_PWRLIMITS_PREBUCK_THROTTLE_CYCLES"/>
1763*9f860dbfSRob Clark	<value value="53" name="A8XX_PERF_GMU_PWC_GX_IFF_THROTTLE_CYCLES"/>
1764*9f860dbfSRob Clark	<value value="54" name="A8XX_PERF_GMU_PWC_GFX_PCLX_THROTTLE_CYCLES"/>
1765*9f860dbfSRob Clark	<value value="55" name="A8XX_PERF_GMU_PWC_MX_IFF_THROTTLE_CYCLES"/>
1766*9f860dbfSRob Clark	<value value="56" name="A8XX_PERF_GMU_PWC_MX_PCLX_THROTTLE_CYCLES"/>
1767*9f860dbfSRob Clark	<value value="57" name="A8XX_PERF_GMU_XOCLK_RESERVED_57"/>
1768*9f860dbfSRob Clark	<value value="58" name="A8XX_PERF_GMU_XOCLK_RESERVED_58"/>
1769*9f860dbfSRob Clark	<value value="59" name="A8XX_PERF_GMU_XOCLK_RESERVED_59"/>
1770*9f860dbfSRob Clark	<value value="60" name="A8XX_PERF_GMU_XOCLK_RESERVED_60"/>
1771*9f860dbfSRob Clark	<value value="61" name="A8XX_PERF_GMU_XOCLK_RESERVED_61"/>
1772*9f860dbfSRob Clark	<value value="62" name="A8XX_PERF_GMU_XOCLK_RESERVED_62"/>
1773*9f860dbfSRob Clark	<value value="63" name="A8XX_PERF_GMU_XOCLK_RESERVED_63"/>
1774*9f860dbfSRob Clark	<value value="64" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_0_CNT"/>
1775*9f860dbfSRob Clark	<value value="65" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_1_CNT"/>
1776*9f860dbfSRob Clark	<value value="66" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_2_CNT"/>
1777*9f860dbfSRob Clark	<value value="67" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_3_CNT"/>
1778*9f860dbfSRob Clark	<value value="68" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_4_CNT"/>
1779*9f860dbfSRob Clark	<value value="69" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_5_CNT"/>
1780*9f860dbfSRob Clark	<value value="70" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_6_CNT"/>
1781*9f860dbfSRob Clark	<value value="71" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_7_CNT"/>
1782*9f860dbfSRob Clark	<value value="72" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_8_CNT"/>
1783*9f860dbfSRob Clark	<value value="73" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_9_CNT"/>
1784*9f860dbfSRob Clark	<value value="74" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_10_CNT"/>
1785*9f860dbfSRob Clark	<value value="75" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_11_CNT"/>
1786*9f860dbfSRob Clark	<value value="76" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_12_CNT"/>
1787*9f860dbfSRob Clark	<value value="77" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_13_CNT"/>
1788*9f860dbfSRob Clark	<value value="78" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_14_CNT"/>
1789*9f860dbfSRob Clark	<value value="79" name="A8XX_PERF_GMU_PWC_GXDCE_HIST_BIN_15_CNT"/>
1790*9f860dbfSRob Clark	<value value="80" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_0_CNT"/>
1791*9f860dbfSRob Clark	<value value="81" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_1_CNT"/>
1792*9f860dbfSRob Clark	<value value="82" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_2_CNT"/>
1793*9f860dbfSRob Clark	<value value="83" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_3_CNT"/>
1794*9f860dbfSRob Clark	<value value="84" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_4_CNT"/>
1795*9f860dbfSRob Clark	<value value="85" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_5_CNT"/>
1796*9f860dbfSRob Clark	<value value="86" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_6_CNT"/>
1797*9f860dbfSRob Clark	<value value="87" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_7_CNT"/>
1798*9f860dbfSRob Clark	<value value="88" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_8_CNT"/>
1799*9f860dbfSRob Clark	<value value="89" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_9_CNT"/>
1800*9f860dbfSRob Clark	<value value="90" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_10_CNT"/>
1801*9f860dbfSRob Clark	<value value="91" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_11_CNT"/>
1802*9f860dbfSRob Clark	<value value="92" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_12_CNT"/>
1803*9f860dbfSRob Clark	<value value="93" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_13_CNT"/>
1804*9f860dbfSRob Clark	<value value="94" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_14_CNT"/>
1805*9f860dbfSRob Clark	<value value="95" name="A8XX_PERF_GMU_PWC_GXCDYN_HIST_BIN_15_CNT"/>
1806*9f860dbfSRob Clark</enum>
1807*9f860dbfSRob Clark
1808*9f860dbfSRob Clark<enum name="a8xx_gmu_gmuclk_perfcounter_select">
1809*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_GMUCLK_NO_COUNT"/>
1810*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_0"/>
1811*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_1"/>
1812*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_2"/>
1813*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_3"/>
1814*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_4"/>
1815*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_5"/>
1816*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_6"/>
1817*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_GMU_PWC_FW_INCREMENT_7"/>
1818*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_GMU_PWC_SOC_MIN_IDLE_VOTE"/>
1819*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_GMU_PWC_TSENSE_CBCAST_MSG"/>
1820*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_GMU_PWC_MXA_CBCAST_MSG"/>
1821*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_GMU_PWC_CX_CBCAST_MSG"/>
1822*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_GMU_PWC_GX_CBCAST_MSG"/>
1823*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_GMU_PWC_BCL_CBCAST_MSG"/>
1824*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_GMU_PWC_MXC_CBCAST_MSG"/>
1825*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_GMU_PWC_GENERIC_CBCAST_MSG"/>
1826*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_GMU_PWC_PMIC_CBCAST_MSG"/>
1827*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_GMU_PWC_CLX_CBCAST_MSG"/>
1828*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_GMU_PWC_PMICARB_CLX_IRQ"/>
1829*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_GMU_PWC_CLX_EXPIRE_CBCAST_MSG"/>
1830*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_GMU_PWC_PMICARB_CLX_EXPIRE_IRQ"/>
1831*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_GMU_PWC_MXC_CLX_CBCAST_MSG"/>
1832*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_GMU_PWC_BCL_TYPE_0_CBCAST_MSG"/>
1833*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_GMU_PWC_BCL_TYPE_1_CBCAST_MSG"/>
1834*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_GMU_PWC_BCL_TYPE_2_CBCAST_MSG"/>
1835*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_GMU_PWC_PMIC_MSG2_CBCAST_MSG"/>
1836*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_GMU_PWC_MSG2_CLX_START_CBCAST_MSG"/>
1837*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_GMU_PWC_MSG2_CLX_EXPIRE_CBCAST_MSG"/>
1838*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_GMU_PWC_GX_VRM_1_CBCAST_MSG"/>
1839*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_GMU_GMUCLK_RESERVED_30"/>
1840*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_GMU_GMUCLK_RESERVED_31"/>
1841*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_GMU_PWC_CTXT_DONE_BR"/>
1842*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_GMU_PWC_CTXT_DONE_BV"/>
1843*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_GMU_PWC_CTXT_DONE_LPAC"/>
1844*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_GMU_PWC_GFX_IFF_MSG"/>
1845*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_GMU_PWC_GFX_PCLX_MSG"/>
1846*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_GMU_PWC_MX_IFF_MSG"/>
1847*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_GMU_PWC_MX_PCLX_MSG"/>
1848*9f860dbfSRob Clark</enum>
1849*9f860dbfSRob Clark
1850*9f860dbfSRob Clark<enum name="a8xx_gmu_perf_perfcounter_select">
1851*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_GMU_NO_COUNT"/>
1852*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_GMU_CM3_BUSY_CYCLES"/>
1853*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_GMU_DATA_CACHE_READ"/>
1854*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_GMU_DATA_CACHE_READ_MISS"/>
1855*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_GMU_DATA_CACHE_WRITE"/>
1856*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_GMU_DATA_CACHE_WRITE_MISS"/>
1857*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_GMU_DATA_CACHE_EVICTIONS"/>
1858*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_GMU_L0_INSTRUCTION_CACHE_READ"/>
1859*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_GMU_L0_INSTRUCTION_CACHE_READ_MISS"/>
1860*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_GMU_L1_INSTRUCTION_CACHE_READ"/>
1861*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_GMU_L1_INSTRUCTION_CACHE_READ_MISS"/>
1862*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_GMU_SYS_AHB_WRITE"/>
1863*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_GMU_SYS_AHB_WRITE_BUFFER_MISS"/>
1864*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_GMU_SYS_AHB_READ"/>
1865*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_GMU_SYS_AHB_READ_BUFFER_MISS"/>
1866*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_GMU_DATA_CACHE_AHB_TOTAL_WAIT_CYCLES"/>
1867*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_GMU_DATA_CACHE_VBIF_TOTAL_WAIT_CYCLES"/>
1868*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_GMU_INSTRUCTION_CACHE_AHB_TOTAL_WAIT_CYCLES"/>
1869*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_GMU_INSTRUCTION_CACHE_VBIF_TOTAL_WAIT_CYCLES"/>
1870*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_GMU_SYS_VBIF_AHB_TOTAL_WAIT_CYCLES"/>
1871*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_GMU_SYS__AHB_TOTAL_WAIT_CYCLES"/>
1872*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_GMU_TOTAL_INTR_LATENCY_CYCLES"/>
1873*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_GMU_WORST_INTR_LATENCY_CYCLES"/>
1874*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_GMU_TOTAL_OUTSTANDING_INTERRUPTS"/>
1875*9f860dbfSRob Clark</enum>
1876*9f860dbfSRob Clark
1877*9f860dbfSRob Clark<enum name="a8xx_ufc_perfcounter_select">
1878*9f860dbfSRob Clark	<value value="0" name="A8XX_PERF_UFC_NEVER_COUNT"/>
1879*9f860dbfSRob Clark	<value value="1" name="A8XX_PERF_UFC_BUSY_CYCLES"/>
1880*9f860dbfSRob Clark	<value value="2" name="A8XX_PERF_UFC_READ_DATA_VBIF"/>
1881*9f860dbfSRob Clark	<value value="3" name="A8XX_PERF_UFC_WRITE_DATA_VBIF"/>
1882*9f860dbfSRob Clark	<value value="4" name="A8XX_PERF_UFC_READ_REQUEST_VBIF"/>
1883*9f860dbfSRob Clark	<value value="5" name="A8XX_PERF_UFC_WRITE_REQUEST_VBIF"/>
1884*9f860dbfSRob Clark	<value value="6" name="A8XX_PERF_UFC_MAIN_HIT_CRE_PREFETCH"/>
1885*9f860dbfSRob Clark	<value value="7" name="A8XX_PERF_UFC_MAIN_HIT_SP_PREFETCH"/>
1886*9f860dbfSRob Clark	<value value="8" name="A8XX_PERF_UFC_MAIN_HIT_TP_PREFETCH"/>
1887*9f860dbfSRob Clark	<value value="9" name="A8XX_PERF_UFC_MAIN_HIT_UBWC_READ"/>
1888*9f860dbfSRob Clark	<value value="10" name="A8XX_PERF_UFC_MAIN_HIT_UBWC_WRITE"/>
1889*9f860dbfSRob Clark	<value value="11" name="A8XX_PERF_UFC_MAIN_MISS_CRE_PREFETCH"/>
1890*9f860dbfSRob Clark	<value value="12" name="A8XX_PERF_UFC_MAIN_MISS_SP_PREFETCH"/>
1891*9f860dbfSRob Clark	<value value="13" name="A8XX_PERF_UFC_MAIN_MISS_TP_PREFETCH"/>
1892*9f860dbfSRob Clark	<value value="14" name="A8XX_PERF_UFC_MAIN_MISS_UBWC_READ"/>
1893*9f860dbfSRob Clark	<value value="15" name="A8XX_PERF_UFC_MAIN_MISS_UBWC_WRITE"/>
1894*9f860dbfSRob Clark	<value value="16" name="A8XX_PERF_UFC_MAIN_UBWC_RD_NRDY"/>
1895*9f860dbfSRob Clark	<value value="17" name="A8XX_PERF_UFC_MAIN_UBWC_RD_RDY"/>
1896*9f860dbfSRob Clark	<value value="18" name="A8XX_PERF_UFC_MAIN_TP_RD_NRDY"/>
1897*9f860dbfSRob Clark	<value value="19" name="A8XX_PERF_UFC_MAIN_TP_RD_RDY"/>
1898*9f860dbfSRob Clark	<value value="20" name="A8XX_PERF_UFC_STALL_CYCLES_GBIF_CMD"/>
1899*9f860dbfSRob Clark	<value value="21" name="A8XX_PERF_UFC_STALL_CYCLES_GBIF_RDATA"/>
1900*9f860dbfSRob Clark	<value value="22" name="A8XX_PERF_UFC_STALL_CYCLES_GBIF_WDATA"/>
1901*9f860dbfSRob Clark	<value value="23" name="A8XX_PERF_UFC_STALL_CYCLES_UBWC_WR_FLAG"/>
1902*9f860dbfSRob Clark	<value value="24" name="A8XX_PERF_UFC_STALL_CYCLES_UBWC_FLAG_RTN"/>
1903*9f860dbfSRob Clark	<value value="25" name="A8XX_PERF_UFC_STALL_CYCLES_UBWC_EVENT"/>
1904*9f860dbfSRob Clark	<value value="26" name="A8XX_PERF_UFC_UBWC_REQ_STALLED_CYCLES"/>
1905*9f860dbfSRob Clark	<value value="27" name="A8XX_PERF_UFC_UBWC_RD_STALLED_CYCLES"/>
1906*9f860dbfSRob Clark	<value value="28" name="A8XX_PERF_UFC_UBWC_WR_STALLED_CYCLES"/>
1907*9f860dbfSRob Clark	<value value="29" name="A8XX_PERF_UFC_PREFETCH_STALLED_CYCLES"/>
1908*9f860dbfSRob Clark	<value value="30" name="A8XX_PERF_UFC_EVICTION_STALLED_CYCLES"/>
1909*9f860dbfSRob Clark	<value value="31" name="A8XX_PERF_UFC_LOCK_STALLED_CYCLES"/>
1910*9f860dbfSRob Clark	<value value="32" name="A8XX_PERF_UFC_MISS_LATENCY_CYCLES"/>
1911*9f860dbfSRob Clark	<value value="33" name="A8XX_PERF_UFC_MISS_LATENCY_SAMPLES"/>
1912*9f860dbfSRob Clark	<value value="34" name="A8XX_PERF_UFC_L1_CRE_REQUESTS"/>
1913*9f860dbfSRob Clark	<value value="35" name="A8XX_PERF_UFC_L1_CRE_STALLED_CYCLES"/>
1914*9f860dbfSRob Clark	<value value="36" name="A8XX_PERF_UFC_L1_CRE_FILTER_HIT"/>
1915*9f860dbfSRob Clark	<value value="37" name="A8XX_PERF_UFC_L1_CRE_FILTER_MISS"/>
1916*9f860dbfSRob Clark	<value value="38" name="A8XX_PERF_UFC_L1_SP_REQUESTS"/>
1917*9f860dbfSRob Clark	<value value="39" name="A8XX_PERF_UFC_L1_SP_STALLED_CYCLES"/>
1918*9f860dbfSRob Clark	<value value="40" name="A8XX_PERF_UFC_L1_SP_FILTER_HIT"/>
1919*9f860dbfSRob Clark	<value value="41" name="A8XX_PERF_UFC_L1_SP_FILTER_MISS"/>
1920*9f860dbfSRob Clark	<value value="42" name="A8XX_PERF_UFC_L1_TP_HINT_REQUESTS"/>
1921*9f860dbfSRob Clark	<value value="43" name="A8XX_PERF_UFC_L1_TP_STALLED_CYCLES"/>
1922*9f860dbfSRob Clark	<value value="44" name="A8XX_PERF_UFC_L1_TP_HINT_TAG_MISS"/>
1923*9f860dbfSRob Clark	<value value="45" name="A8XX_PERF_UFC_L1_TP_HINT_TAG_HIT_RDY"/>
1924*9f860dbfSRob Clark	<value value="46" name="A8XX_PERF_UFC_L1_TP_HINT_TAG_HIT_NRDY"/>
1925*9f860dbfSRob Clark	<value value="47" name="A8XX_PERF_UFC_AUTO_EVICTIONS"/>
1926*9f860dbfSRob Clark	<value value="48" name="A8XX_PERF_UFC_PARTIAL_EVICTIONS"/>
1927*9f860dbfSRob Clark</enum>
1928*9f860dbfSRob Clark
1929*9f860dbfSRob Clark</database>
1930