1<?xml version="1.0" encoding="UTF-8"?> 2<database xmlns="http://nouveau.freedesktop.org/" 3xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" 4xsi:schemaLocation="https://gitlab.freedesktop.org/freedreno/ rules-fd.xsd"> 5<import file="freedreno_copyright.xml"/> 6<import file="adreno/adreno_common.xml"/> 7<import file="adreno/adreno_pm4.xml"/> 8 9<enum name="a6xx_cp_perfcounter_select"> 10 <value value="0" name="PERF_CP_ALWAYS_COUNT"/> 11 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/> 12 <value value="2" name="PERF_CP_BUSY_CYCLES"/> 13 <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/> 14 <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/> 15 <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/> 16 <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/> 17 <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/> 18 <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/> 19 <value value="9" name="PERF_CP_MODE_SWITCH"/> 20 <value value="10" name="PERF_CP_ZPASS_DONE"/> 21 <value value="11" name="PERF_CP_CONTEXT_DONE"/> 22 <value value="12" name="PERF_CP_CACHE_FLUSH"/> 23 <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/> 24 <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/> 25 <value value="15" name="PERF_CP_SQE_IDLE"/> 26 <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/> 27 <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/> 28 <value value="18" name="PERF_CP_SQE_MRB_STARVE"/> 29 <value value="19" name="PERF_CP_SQE_RRB_STARVE"/> 30 <value value="20" name="PERF_CP_SQE_VSD_STARVE"/> 31 <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/> 32 <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/> 33 <value value="23" name="PERF_CP_SQE_SYNC_STALL"/> 34 <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/> 35 <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/> 36 <value value="26" name="PERF_CP_SQE_T4_EXEC"/> 37 <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/> 38 <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/> 39 <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/> 40 <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/> 41 <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/> 42 <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/> 43 <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/> 44 <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/> 45 <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/> 46 <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/> 47 <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/> 48 <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/> 49 <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/> 50 <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/> 51 <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/> 52 <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/> 53 <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/> 54 <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/> 55 <value value="45" name="PERF_CP_PM4_DATA"/> 56 <value value="46" name="PERF_CP_PM4_HEADERS"/> 57 <value value="47" name="PERF_CP_VBIF_READ_BEATS"/> 58 <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/> 59 <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/> 60</enum> 61 62<enum name="a6xx_rbbm_perfcounter_select"> 63 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/> 64 <value value="1" name="PERF_RBBM_ALWAYS_ON"/> 65 <value value="2" name="PERF_RBBM_TSE_BUSY"/> 66 <value value="3" name="PERF_RBBM_RAS_BUSY"/> 67 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/> 68 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/> 69 <value value="6" name="PERF_RBBM_STATUS_MASKED"/> 70 <value value="7" name="PERF_RBBM_COM_BUSY"/> 71 <value value="8" name="PERF_RBBM_DCOM_BUSY"/> 72 <value value="9" name="PERF_RBBM_VBIF_BUSY"/> 73 <value value="10" name="PERF_RBBM_VSC_BUSY"/> 74 <value value="11" name="PERF_RBBM_TESS_BUSY"/> 75 <value value="12" name="PERF_RBBM_UCHE_BUSY"/> 76 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/> 77</enum> 78 79<enum name="a6xx_pc_perfcounter_select"> 80 <value value="0" name="PERF_PC_BUSY_CYCLES"/> 81 <value value="1" name="PERF_PC_WORKING_CYCLES"/> 82 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/> 83 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/> 84 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/> 85 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/> 86 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/> 87 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/> 88 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/> 89 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/> 90 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/> 91 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/> 92 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/> 93 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/> 94 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/> 95 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/> 96 <value value="16" name="PERF_PC_INSTANCES"/> 97 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/> 98 <value value="18" name="PERF_PC_DEAD_PRIM"/> 99 <value value="19" name="PERF_PC_LIVE_PRIM"/> 100 <value value="20" name="PERF_PC_VERTEX_HITS"/> 101 <value value="21" name="PERF_PC_IA_VERTICES"/> 102 <value value="22" name="PERF_PC_IA_PRIMITIVES"/> 103 <value value="23" name="PERF_PC_GS_PRIMITIVES"/> 104 <value value="24" name="PERF_PC_HS_INVOCATIONS"/> 105 <value value="25" name="PERF_PC_DS_INVOCATIONS"/> 106 <value value="26" name="PERF_PC_VS_INVOCATIONS"/> 107 <value value="27" name="PERF_PC_GS_INVOCATIONS"/> 108 <value value="28" name="PERF_PC_DS_PRIMITIVES"/> 109 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/> 110 <value value="30" name="PERF_PC_3D_DRAWCALLS"/> 111 <value value="31" name="PERF_PC_2D_DRAWCALLS"/> 112 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/> 113 <value value="33" name="PERF_TESS_BUSY_CYCLES"/> 114 <value value="34" name="PERF_TESS_WORKING_CYCLES"/> 115 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/> 116 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/> 117 <value value="37" name="PERF_PC_TSE_TRANSACTION"/> 118 <value value="38" name="PERF_PC_TSE_VERTEX"/> 119 <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/> 120 <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/> 121 <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/> 122</enum> 123 124<enum name="a6xx_vfd_perfcounter_select"> 125 <value value="0" name="PERF_VFD_BUSY_CYCLES"/> 126 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/> 127 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/> 128 <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/> 129 <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/> 130 <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/> 131 <value value="6" name="PERF_VFD_RBUFFER_FULL"/> 132 <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/> 133 <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/> 134 <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/> 135 <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/> 136 <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/> 137 <value value="12" name="PERF_VFD_MODE_0_FIBERS"/> 138 <value value="13" name="PERF_VFD_MODE_1_FIBERS"/> 139 <value value="14" name="PERF_VFD_MODE_2_FIBERS"/> 140 <value value="15" name="PERF_VFD_MODE_3_FIBERS"/> 141 <value value="16" name="PERF_VFD_MODE_4_FIBERS"/> 142 <value value="17" name="PERF_VFD_TOTAL_VERTICES"/> 143 <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/> 144 <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/> 145 <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/> 146 <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/> 147 <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/> 148</enum> 149 150<enum name="a6xx_hlsq_perfcounter_select"> 151 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/> 152 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/> 153 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/> 154 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/> 155 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/> 156 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/> 157 <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/> 158 <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/> 159 <value value="8" name="PERF_HLSQ_QUADS"/> 160 <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/> 161 <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/> 162 <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/> 163 <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/> 164 <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/> 165 <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/> 166 <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/> 167 <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/> 168 <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/> 169 <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/> 170 <value value="19" name="PERF_HLSQ_PIXELS"/> 171 <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/> 172</enum> 173 174<enum name="a6xx_vpc_perfcounter_select"> 175 <value value="0" name="PERF_VPC_BUSY_CYCLES"/> 176 <value value="1" name="PERF_VPC_WORKING_CYCLES"/> 177 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/> 178 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/> 179 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/> 180 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/> 181 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/> 182 <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/> 183 <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/> 184 <value value="9" name="PERF_VPC_PC_PRIMITIVES"/> 185 <value value="10" name="PERF_VPC_SP_COMPONENTS"/> 186 <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/> 187 <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/> 188 <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/> 189 <value value="14" name="PERF_VPC_LM_TRANSACTION"/> 190 <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/> 191 <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/> 192 <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/> 193 <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/> 194 <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/> 195 <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/> 196 <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/> 197 <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/> 198 <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/> 199 <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/> 200 <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/> 201 <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/> 202 <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/> 203</enum> 204 205<enum name="a6xx_tse_perfcounter_select"> 206 <value value="0" name="PERF_TSE_BUSY_CYCLES"/> 207 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/> 208 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/> 209 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/> 210 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/> 211 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/> 212 <value value="6" name="PERF_TSE_INPUT_PRIM"/> 213 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/> 214 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/> 215 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/> 216 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/> 217 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/> 218 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/> 219 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/> 220 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/> 221 <value value="15" name="PERF_TSE_CINVOCATION"/> 222 <value value="16" name="PERF_TSE_CPRIMITIVES"/> 223 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/> 224 <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/> 225 <value value="19" name="PERF_TSE_CLIP_PLANES"/> 226</enum> 227 228<enum name="a6xx_ras_perfcounter_select"> 229 <value value="0" name="PERF_RAS_BUSY_CYCLES"/> 230 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/> 231 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/> 232 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/> 233 <value value="4" name="PERF_RAS_SUPER_TILES"/> 234 <value value="5" name="PERF_RAS_8X4_TILES"/> 235 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/> 236 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/> 237 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/> 238 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/> 239 <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/> 240 <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/> 241 <value value="12" name="PERF_RAS_BLOCKS"/> 242</enum> 243 244<enum name="a6xx_uche_perfcounter_select"> 245 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/> 246 <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/> 247 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/> 248 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/> 249 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/> 250 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/> 251 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/> 252 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/> 253 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/> 254 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/> 255 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/> 256 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/> 257 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/> 258 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/> 259 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/> 260 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/> 261 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/> 262 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/> 263 <value value="18" name="PERF_UCHE_EVICTS"/> 264 <value value="19" name="PERF_UCHE_BANK_REQ0"/> 265 <value value="20" name="PERF_UCHE_BANK_REQ1"/> 266 <value value="21" name="PERF_UCHE_BANK_REQ2"/> 267 <value value="22" name="PERF_UCHE_BANK_REQ3"/> 268 <value value="23" name="PERF_UCHE_BANK_REQ4"/> 269 <value value="24" name="PERF_UCHE_BANK_REQ5"/> 270 <value value="25" name="PERF_UCHE_BANK_REQ6"/> 271 <value value="26" name="PERF_UCHE_BANK_REQ7"/> 272 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/> 273 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/> 274 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/> 275 <value value="30" name="PERF_UCHE_TPH_REF_FULL"/> 276 <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/> 277 <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/> 278 <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/> 279 <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/> 280 <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/> 281 <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/> 282 <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/> 283 <value value="38" name="PERF_UCHE_RAM_READ_REQ"/> 284 <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/> 285</enum> 286 287<enum name="a6xx_tp_perfcounter_select"> 288 <value value="0" name="PERF_TP_BUSY_CYCLES"/> 289 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/> 290 <value value="2" name="PERF_TP_LATENCY_CYCLES"/> 291 <value value="3" name="PERF_TP_LATENCY_TRANS"/> 292 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/> 293 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/> 294 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/> 295 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/> 296 <value value="8" name="PERF_TP_SP_TP_TRANS"/> 297 <value value="9" name="PERF_TP_TP_SP_TRANS"/> 298 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/> 299 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/> 300 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/> 301 <value value="13" name="PERF_TP_QUADS_RECEIVED"/> 302 <value value="14" name="PERF_TP_QUADS_OFFSET"/> 303 <value value="15" name="PERF_TP_QUADS_SHADOW"/> 304 <value value="16" name="PERF_TP_QUADS_ARRAY"/> 305 <value value="17" name="PERF_TP_QUADS_GRADIENT"/> 306 <value value="18" name="PERF_TP_QUADS_1D"/> 307 <value value="19" name="PERF_TP_QUADS_2D"/> 308 <value value="20" name="PERF_TP_QUADS_BUFFER"/> 309 <value value="21" name="PERF_TP_QUADS_3D"/> 310 <value value="22" name="PERF_TP_QUADS_CUBE"/> 311 <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/> 312 <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/> 313 <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/> 314 <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/> 315 <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/> 316 <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/> 317 <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/> 318 <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/> 319 <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/> 320 <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/> 321 <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/> 322 <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/> 323 <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/> 324 <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/> 325 <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/> 326 <value value="38" name="PERF_TP_TPA2TPC_TRANS"/> 327 <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/> 328 <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/> 329 <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/> 330 <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/> 331 <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/> 332 <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/> 333 <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/> 334 <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/> 335 <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/> 336 <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/> 337 <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/> 338 <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/> 339 <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/> 340 <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/> 341 <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/> 342 <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/> 343 <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/> 344 <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/> 345</enum> 346 347<enum name="a6xx_sp_perfcounter_select"> 348 <value value="0" name="PERF_SP_BUSY_CYCLES"/> 349 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/> 350 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/> 351 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/> 352 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/> 353 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/> 354 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/> 355 <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/> 356 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/> 357 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/> 358 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/> 359 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/> 360 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/> 361 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/> 362 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/> 363 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/> 364 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/> 365 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/> 366 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/> 367 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/> 368 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/> 369 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/> 370 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/> 371 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/> 372 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/> 373 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/> 374 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/> 375 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/> 376 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/> 377 <value value="29" name="PERF_SP_LM_ATOMICS"/> 378 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/> 379 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/> 380 <value value="32" name="PERF_SP_GM_ATOMICS"/> 381 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/> 382 <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/> 383 <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/> 384 <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/> 385 <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/> 386 <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/> 387 <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/> 388 <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/> 389 <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/> 390 <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/> 391 <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/> 392 <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/> 393 <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/> 394 <value value="46" name="PERF_SP_UCHE_READ_TRANS"/> 395 <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/> 396 <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/> 397 <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/> 398 <value value="50" name="PERF_SP_PIXELS_KILLED"/> 399 <value value="51" name="PERF_SP_ICL1_REQUESTS"/> 400 <value value="52" name="PERF_SP_ICL1_MISSES"/> 401 <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/> 402 <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/> 403 <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/> 404 <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/> 405 <value value="57" name="PERF_SP_GPR_READ"/> 406 <value value="58" name="PERF_SP_GPR_WRITE"/> 407 <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/> 408 <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/> 409 <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/> 410 <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/> 411 <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/> 412 <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/> 413 <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/> 414 <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/> 415 <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/> 416 <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/> 417 <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/> 418 <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/> 419 <value value="71" name="PERF_SP_WORKING_EU"/> 420 <value value="72" name="PERF_SP_ANY_EU_WORKING"/> 421 <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/> 422 <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/> 423 <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/> 424 <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/> 425 <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/> 426 <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/> 427 <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/> 428 <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/> 429 <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/> 430 <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/> 431 <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/> 432 <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/> 433</enum> 434 435<enum name="a6xx_rb_perfcounter_select"> 436 <value value="0" name="PERF_RB_BUSY_CYCLES"/> 437 <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/> 438 <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/> 439 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/> 440 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/> 441 <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/> 442 <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/> 443 <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/> 444 <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/> 445 <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/> 446 <value value="10" name="PERF_RB_Z_WORKLOAD"/> 447 <value value="11" name="PERF_RB_HLSQ_ACTIVE"/> 448 <value value="12" name="PERF_RB_Z_READ"/> 449 <value value="13" name="PERF_RB_Z_WRITE"/> 450 <value value="14" name="PERF_RB_C_READ"/> 451 <value value="15" name="PERF_RB_C_WRITE"/> 452 <value value="16" name="PERF_RB_TOTAL_PASS"/> 453 <value value="17" name="PERF_RB_Z_PASS"/> 454 <value value="18" name="PERF_RB_Z_FAIL"/> 455 <value value="19" name="PERF_RB_S_FAIL"/> 456 <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/> 457 <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/> 458 <value value="22" name="PERF_RB_PS_INVOCATIONS"/> 459 <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/> 460 <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/> 461 <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/> 462 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/> 463 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/> 464 <value value="28" name="PERF_RB_2D_VALID_PIXELS"/> 465 <value value="29" name="PERF_RB_3D_PIXELS"/> 466 <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/> 467 <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/> 468 <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/> 469 <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/> 470 <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/> 471 <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/> 472 <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/> 473 <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/> 474 <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/> 475 <value value="39" name="PERF_RB_2D_INPUT_TRANS"/> 476 <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/> 477 <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/> 478 <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/> 479 <value value="43" name="PERF_RB_COLOR_PIX_TILES"/> 480 <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/> 481 <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/> 482 <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/> 483 <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/> 484</enum> 485 486<enum name="a6xx_vsc_perfcounter_select"> 487 <value value="0" name="PERF_VSC_BUSY_CYCLES"/> 488 <value value="1" name="PERF_VSC_WORKING_CYCLES"/> 489 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/> 490 <value value="3" name="PERF_VSC_EOT_NUM"/> 491 <value value="4" name="PERF_VSC_INPUT_TILES"/> 492</enum> 493 494<enum name="a6xx_ccu_perfcounter_select"> 495 <value value="0" name="PERF_CCU_BUSY_CYCLES"/> 496 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/> 497 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/> 498 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/> 499 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/> 500 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/> 501 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/> 502 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/> 503 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/> 504 <value value="9" name="PERF_CCU_GMEM_READ"/> 505 <value value="10" name="PERF_CCU_GMEM_WRITE"/> 506 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/> 507 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/> 508 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/> 509 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/> 510 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/> 511 <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/> 512 <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/> 513 <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/> 514 <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/> 515 <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/> 516 <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/> 517 <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/> 518 <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/> 519 <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/> 520 <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/> 521 <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/> 522 <value value="27" name="PERF_CCU_2D_RD_REQ"/> 523 <value value="28" name="PERF_CCU_2D_WR_REQ"/> 524</enum> 525 526<enum name="a6xx_lrz_perfcounter_select"> 527 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/> 528 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/> 529 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/> 530 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/> 531 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/> 532 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/> 533 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/> 534 <value value="7" name="PERF_LRZ_LRZ_READ"/> 535 <value value="8" name="PERF_LRZ_LRZ_WRITE"/> 536 <value value="9" name="PERF_LRZ_READ_LATENCY"/> 537 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/> 538 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/> 539 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/> 540 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/> 541 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/> 542 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/> 543 <value value="16" name="PERF_LRZ_TILE_KILLED"/> 544 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/> 545 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/> 546 <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/> 547 <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/> 548 <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/> 549 <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/> 550 <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/> 551 <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/> 552 <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/> 553 <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/> 554 <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/> 555</enum> 556 557<enum name="a6xx_cmp_perfcounter_select"> 558 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/> 559 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/> 560 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/> 561 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/> 562 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/> 563 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/> 564 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/> 565 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/> 566 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/> 567 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/> 568 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/> 569 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/> 570 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/> 571 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/> 572 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/> 573 <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/> 574 <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/> 575 <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/> 576 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/> 577 <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/> 578 <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/> 579 <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/> 580 <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/> 581 <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/> 582 <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/> 583 <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/> 584 <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/> 585 <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/> 586 <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/> 587 <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/> 588 <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/> 589 <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/> 590 <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/> 591 <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/> 592 <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/> 593 <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/> 594 <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/> 595 <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/> 596 <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/> 597 <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/> 598</enum> 599 600</database> 601