1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 9 #include <drm/drm_vblank.h> 10 11 #include "msm_drv.h" 12 #include "msm_gem.h" 13 #include "msm_mmu.h" 14 #include "mdp4_kms.h" 15 16 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev); 17 18 static int mdp4_hw_init(struct msm_kms *kms) 19 { 20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 21 struct drm_device *dev = mdp4_kms->dev; 22 u32 dmap_cfg, vg_cfg; 23 unsigned long clk; 24 25 pm_runtime_get_sync(dev->dev); 26 27 if (mdp4_kms->rev > 1) { 28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 30 } 31 32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 33 34 /* max read pending cmd config, 3 pending requests: */ 35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 36 37 clk = clk_get_rate(mdp4_kms->clk); 38 39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 42 } else { 43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 45 } 46 47 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 48 49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 51 52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 56 57 if (mdp4_kms->rev >= 2) 58 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 60 61 /* disable CSC matrix / YUV by default: */ 62 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 64 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 65 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 66 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 68 69 if (mdp4_kms->rev > 1) 70 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 71 72 pm_runtime_put_sync(dev->dev); 73 74 return 0; 75 } 76 77 static void mdp4_enable_commit(struct msm_kms *kms) 78 { 79 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 80 mdp4_enable(mdp4_kms); 81 } 82 83 static void mdp4_disable_commit(struct msm_kms *kms) 84 { 85 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 86 mdp4_disable(mdp4_kms); 87 } 88 89 static void mdp4_prepare_commit(struct msm_kms *kms, struct drm_atomic_state *state) 90 { 91 } 92 93 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 94 { 95 /* TODO */ 96 } 97 98 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 99 { 100 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 101 struct drm_crtc *crtc; 102 103 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask) 104 mdp4_crtc_wait_for_commit_done(crtc); 105 } 106 107 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 108 { 109 } 110 111 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 112 struct drm_encoder *encoder) 113 { 114 /* if we had >1 encoder, we'd need something more clever: */ 115 switch (encoder->encoder_type) { 116 case DRM_MODE_ENCODER_TMDS: 117 return mdp4_dtv_round_pixclk(encoder, rate); 118 case DRM_MODE_ENCODER_LVDS: 119 case DRM_MODE_ENCODER_DSI: 120 default: 121 return rate; 122 } 123 } 124 125 static void mdp4_destroy(struct msm_kms *kms) 126 { 127 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 128 struct device *dev = mdp4_kms->dev->dev; 129 struct msm_gem_address_space *aspace = kms->aspace; 130 131 if (mdp4_kms->blank_cursor_iova) 132 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace); 133 drm_gem_object_put(mdp4_kms->blank_cursor_bo); 134 135 if (aspace) { 136 aspace->mmu->funcs->detach(aspace->mmu); 137 msm_gem_address_space_put(aspace); 138 } 139 140 if (mdp4_kms->rpm_enabled) 141 pm_runtime_disable(dev); 142 143 mdp_kms_destroy(&mdp4_kms->base); 144 145 kfree(mdp4_kms); 146 } 147 148 static const struct mdp_kms_funcs kms_funcs = { 149 .base = { 150 .hw_init = mdp4_hw_init, 151 .irq_preinstall = mdp4_irq_preinstall, 152 .irq_postinstall = mdp4_irq_postinstall, 153 .irq_uninstall = mdp4_irq_uninstall, 154 .irq = mdp4_irq, 155 .enable_vblank = mdp4_enable_vblank, 156 .disable_vblank = mdp4_disable_vblank, 157 .enable_commit = mdp4_enable_commit, 158 .disable_commit = mdp4_disable_commit, 159 .prepare_commit = mdp4_prepare_commit, 160 .flush_commit = mdp4_flush_commit, 161 .wait_flush = mdp4_wait_flush, 162 .complete_commit = mdp4_complete_commit, 163 .get_format = mdp_get_format, 164 .round_pixclk = mdp4_round_pixclk, 165 .destroy = mdp4_destroy, 166 }, 167 .set_irqmask = mdp4_set_irqmask, 168 }; 169 170 int mdp4_disable(struct mdp4_kms *mdp4_kms) 171 { 172 DBG(""); 173 174 clk_disable_unprepare(mdp4_kms->clk); 175 clk_disable_unprepare(mdp4_kms->pclk); 176 clk_disable_unprepare(mdp4_kms->lut_clk); 177 clk_disable_unprepare(mdp4_kms->axi_clk); 178 179 return 0; 180 } 181 182 int mdp4_enable(struct mdp4_kms *mdp4_kms) 183 { 184 DBG(""); 185 186 clk_prepare_enable(mdp4_kms->clk); 187 clk_prepare_enable(mdp4_kms->pclk); 188 clk_prepare_enable(mdp4_kms->lut_clk); 189 clk_prepare_enable(mdp4_kms->axi_clk); 190 191 return 0; 192 } 193 194 195 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 196 int intf_type) 197 { 198 struct drm_device *dev = mdp4_kms->dev; 199 struct msm_drm_private *priv = dev->dev_private; 200 struct drm_encoder *encoder; 201 struct drm_connector *connector; 202 struct device_node *panel_node; 203 int dsi_id; 204 int ret; 205 206 switch (intf_type) { 207 case DRM_MODE_ENCODER_LVDS: 208 /* 209 * bail out early if there is no panel node (no need to 210 * initialize LCDC encoder and LVDS connector) 211 */ 212 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0); 213 if (!panel_node) 214 return 0; 215 216 encoder = mdp4_lcdc_encoder_init(dev, panel_node); 217 if (IS_ERR(encoder)) { 218 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); 219 return PTR_ERR(encoder); 220 } 221 222 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */ 223 encoder->possible_crtcs = 1 << DMA_P; 224 225 connector = mdp4_lvds_connector_init(dev, panel_node, encoder); 226 if (IS_ERR(connector)) { 227 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); 228 return PTR_ERR(connector); 229 } 230 231 break; 232 case DRM_MODE_ENCODER_TMDS: 233 encoder = mdp4_dtv_encoder_init(dev); 234 if (IS_ERR(encoder)) { 235 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); 236 return PTR_ERR(encoder); 237 } 238 239 /* DTV can be hooked to DMA_E: */ 240 encoder->possible_crtcs = 1 << 1; 241 242 if (priv->hdmi) { 243 /* Construct bridge/connector for HDMI: */ 244 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder); 245 if (ret) { 246 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); 247 return ret; 248 } 249 } 250 251 break; 252 case DRM_MODE_ENCODER_DSI: 253 /* only DSI1 supported for now */ 254 dsi_id = 0; 255 256 if (!priv->dsi[dsi_id]) 257 break; 258 259 encoder = mdp4_dsi_encoder_init(dev); 260 if (IS_ERR(encoder)) { 261 ret = PTR_ERR(encoder); 262 DRM_DEV_ERROR(dev->dev, 263 "failed to construct DSI encoder: %d\n", ret); 264 return ret; 265 } 266 267 /* TODO: Add DMA_S later? */ 268 encoder->possible_crtcs = 1 << DMA_P; 269 270 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder); 271 if (ret) { 272 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", 273 ret); 274 return ret; 275 } 276 277 break; 278 default: 279 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); 280 return -EINVAL; 281 } 282 283 return 0; 284 } 285 286 static int modeset_init(struct mdp4_kms *mdp4_kms) 287 { 288 struct drm_device *dev = mdp4_kms->dev; 289 struct msm_drm_private *priv = dev->dev_private; 290 struct drm_plane *plane; 291 struct drm_crtc *crtc; 292 int i, ret; 293 static const enum mdp4_pipe rgb_planes[] = { 294 RGB1, RGB2, 295 }; 296 static const enum mdp4_pipe vg_planes[] = { 297 VG1, VG2, 298 }; 299 static const enum mdp4_dma mdp4_crtcs[] = { 300 DMA_P, DMA_E, 301 }; 302 static const char * const mdp4_crtc_names[] = { 303 "DMA_P", "DMA_E", 304 }; 305 static const int mdp4_intfs[] = { 306 DRM_MODE_ENCODER_LVDS, 307 DRM_MODE_ENCODER_DSI, 308 DRM_MODE_ENCODER_TMDS, 309 }; 310 311 /* construct non-private planes: */ 312 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { 313 plane = mdp4_plane_init(dev, vg_planes[i], false); 314 if (IS_ERR(plane)) { 315 DRM_DEV_ERROR(dev->dev, 316 "failed to construct plane for VG%d\n", i + 1); 317 ret = PTR_ERR(plane); 318 goto fail; 319 } 320 } 321 322 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { 323 plane = mdp4_plane_init(dev, rgb_planes[i], true); 324 if (IS_ERR(plane)) { 325 DRM_DEV_ERROR(dev->dev, 326 "failed to construct plane for RGB%d\n", i + 1); 327 ret = PTR_ERR(plane); 328 goto fail; 329 } 330 331 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i, 332 mdp4_crtcs[i]); 333 if (IS_ERR(crtc)) { 334 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", 335 mdp4_crtc_names[i]); 336 ret = PTR_ERR(crtc); 337 goto fail; 338 } 339 340 priv->crtcs[priv->num_crtcs++] = crtc; 341 } 342 343 /* 344 * we currently set up two relatively fixed paths: 345 * 346 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS 347 * or 348 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel 349 * 350 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI 351 */ 352 353 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { 354 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); 355 if (ret) { 356 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", 357 i, ret); 358 goto fail; 359 } 360 } 361 362 return 0; 363 364 fail: 365 return ret; 366 } 367 368 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms, 369 u32 *major, u32 *minor) 370 { 371 struct drm_device *dev = mdp4_kms->dev; 372 u32 version; 373 374 mdp4_enable(mdp4_kms); 375 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 376 mdp4_disable(mdp4_kms); 377 378 *major = FIELD(version, MDP4_VERSION_MAJOR); 379 *minor = FIELD(version, MDP4_VERSION_MINOR); 380 381 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor); 382 } 383 384 static int mdp4_kms_init(struct drm_device *dev) 385 { 386 struct platform_device *pdev = to_platform_device(dev->dev); 387 struct mdp4_platform_config *config = mdp4_get_config(pdev); 388 struct msm_drm_private *priv = dev->dev_private; 389 struct mdp4_kms *mdp4_kms; 390 struct msm_kms *kms = NULL; 391 struct msm_gem_address_space *aspace; 392 int irq, ret; 393 u32 major, minor; 394 395 mdp4_kms = kzalloc(sizeof(*mdp4_kms), GFP_KERNEL); 396 if (!mdp4_kms) { 397 DRM_DEV_ERROR(dev->dev, "failed to allocate kms\n"); 398 return -ENOMEM; 399 } 400 401 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs); 402 if (ret) { 403 DRM_DEV_ERROR(dev->dev, "failed to init kms\n"); 404 goto fail; 405 } 406 407 priv->kms = &mdp4_kms->base.base; 408 kms = priv->kms; 409 410 mdp4_kms->dev = dev; 411 412 mdp4_kms->mmio = msm_ioremap(pdev, NULL); 413 if (IS_ERR(mdp4_kms->mmio)) { 414 ret = PTR_ERR(mdp4_kms->mmio); 415 goto fail; 416 } 417 418 irq = platform_get_irq(pdev, 0); 419 if (irq < 0) { 420 ret = irq; 421 DRM_DEV_ERROR(dev->dev, "failed to get irq: %d\n", ret); 422 goto fail; 423 } 424 425 kms->irq = irq; 426 427 /* NOTE: driver for this regulator still missing upstream.. use 428 * _get_exclusive() and ignore the error if it does not exist 429 * (and hope that the bootloader left it on for us) 430 */ 431 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 432 if (IS_ERR(mdp4_kms->vdd)) 433 mdp4_kms->vdd = NULL; 434 435 if (mdp4_kms->vdd) { 436 ret = regulator_enable(mdp4_kms->vdd); 437 if (ret) { 438 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); 439 goto fail; 440 } 441 } 442 443 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 444 if (IS_ERR(mdp4_kms->clk)) { 445 DRM_DEV_ERROR(dev->dev, "failed to get core_clk\n"); 446 ret = PTR_ERR(mdp4_kms->clk); 447 goto fail; 448 } 449 450 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 451 if (IS_ERR(mdp4_kms->pclk)) 452 mdp4_kms->pclk = NULL; 453 454 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); 455 if (IS_ERR(mdp4_kms->axi_clk)) { 456 DRM_DEV_ERROR(dev->dev, "failed to get axi_clk\n"); 457 ret = PTR_ERR(mdp4_kms->axi_clk); 458 goto fail; 459 } 460 461 clk_set_rate(mdp4_kms->clk, config->max_clk); 462 463 read_mdp_hw_revision(mdp4_kms, &major, &minor); 464 465 if (major != 4) { 466 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", 467 major, minor); 468 ret = -ENXIO; 469 goto fail; 470 } 471 472 mdp4_kms->rev = minor; 473 474 if (mdp4_kms->rev >= 2) { 475 mdp4_kms->lut_clk = devm_clk_get(&pdev->dev, "lut_clk"); 476 if (IS_ERR(mdp4_kms->lut_clk)) { 477 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); 478 ret = PTR_ERR(mdp4_kms->lut_clk); 479 goto fail; 480 } 481 clk_set_rate(mdp4_kms->lut_clk, config->max_clk); 482 } 483 484 pm_runtime_enable(dev->dev); 485 mdp4_kms->rpm_enabled = true; 486 487 /* make sure things are off before attaching iommu (bootloader could 488 * have left things on, in which case we'll start getting faults if 489 * we don't disable): 490 */ 491 mdp4_enable(mdp4_kms); 492 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 493 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 494 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 495 mdp4_disable(mdp4_kms); 496 mdelay(16); 497 498 if (config->iommu) { 499 struct msm_mmu *mmu = msm_iommu_new(&pdev->dev, 500 config->iommu); 501 502 aspace = msm_gem_address_space_create(mmu, 503 "mdp4", 0x1000, 0x100000000 - 0x1000); 504 505 if (IS_ERR(aspace)) { 506 if (!IS_ERR(mmu)) 507 mmu->funcs->destroy(mmu); 508 ret = PTR_ERR(aspace); 509 goto fail; 510 } 511 512 kms->aspace = aspace; 513 } else { 514 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 515 "contig buffers for scanout\n"); 516 aspace = NULL; 517 } 518 519 ret = modeset_init(mdp4_kms); 520 if (ret) { 521 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); 522 goto fail; 523 } 524 525 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); 526 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 527 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 528 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 529 mdp4_kms->blank_cursor_bo = NULL; 530 goto fail; 531 } 532 533 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace, 534 &mdp4_kms->blank_cursor_iova); 535 if (ret) { 536 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 537 goto fail; 538 } 539 540 dev->mode_config.min_width = 0; 541 dev->mode_config.min_height = 0; 542 dev->mode_config.max_width = 2048; 543 dev->mode_config.max_height = 2048; 544 545 return 0; 546 547 fail: 548 if (kms) 549 mdp4_destroy(kms); 550 551 return ret; 552 } 553 554 static struct mdp4_platform_config *mdp4_get_config(struct platform_device *dev) 555 { 556 static struct mdp4_platform_config config = {}; 557 558 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ 559 config.max_clk = 266667000; 560 config.iommu = iommu_domain_alloc(&platform_bus_type); 561 562 return &config; 563 } 564 565 static const struct dev_pm_ops mdp4_pm_ops = { 566 .prepare = msm_pm_prepare, 567 .complete = msm_pm_complete, 568 }; 569 570 static int mdp4_probe(struct platform_device *pdev) 571 { 572 return msm_drv_probe(&pdev->dev, mdp4_kms_init); 573 } 574 575 static int mdp4_remove(struct platform_device *pdev) 576 { 577 component_master_del(&pdev->dev, &msm_drm_ops); 578 579 return 0; 580 } 581 582 static const struct of_device_id mdp4_dt_match[] = { 583 { .compatible = "qcom,mdp4" }, 584 { /* sentinel */ } 585 }; 586 MODULE_DEVICE_TABLE(of, mdp4_dt_match); 587 588 static struct platform_driver mdp4_platform_driver = { 589 .probe = mdp4_probe, 590 .remove = mdp4_remove, 591 .shutdown = msm_drv_shutdown, 592 .driver = { 593 .name = "mdp4", 594 .of_match_table = mdp4_dt_match, 595 .pm = &mdp4_pm_ops, 596 }, 597 }; 598 599 void __init msm_mdp4_register(void) 600 { 601 platform_driver_register(&mdp4_platform_driver); 602 } 603 604 void __exit msm_mdp4_unregister(void) 605 { 606 platform_driver_unregister(&mdp4_platform_driver); 607 } 608