1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2013 Red Hat
4 * Author: Rob Clark <robdclark@gmail.com>
5 */
6
7 #include <linux/delay.h>
8
9 #include <drm/drm_vblank.h>
10
11 #include "msm_drv.h"
12 #include "msm_gem.h"
13 #include "msm_mmu.h"
14 #include "mdp4_kms.h"
15
mdp4_hw_init(struct msm_kms * kms)16 static int mdp4_hw_init(struct msm_kms *kms)
17 {
18 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
19 struct drm_device *dev = mdp4_kms->dev;
20 u32 dmap_cfg, vg_cfg;
21 unsigned long clk;
22
23 pm_runtime_get_sync(dev->dev);
24
25 if (mdp4_kms->rev > 1) {
26 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff);
27 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f);
28 }
29
30 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3);
31
32 /* max read pending cmd config, 3 pending requests: */
33 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222);
34
35 clk = clk_get_rate(mdp4_kms->clk);
36
37 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) {
38 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */
39 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */
40 } else {
41 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */
42 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */
43 }
44
45 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg);
46
47 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg);
48 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg);
49
50 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg);
51 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg);
52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg);
53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg);
54
55 if (mdp4_kms->rev >= 2)
56 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1);
57 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0);
58
59 /* disable CSC matrix / YUV by default: */
60 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0);
61 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0);
62 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0);
63 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0);
64 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0);
65 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0);
66
67 if (mdp4_kms->rev > 1)
68 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1);
69
70 pm_runtime_put_sync(dev->dev);
71
72 return 0;
73 }
74
mdp4_enable_commit(struct msm_kms * kms)75 static void mdp4_enable_commit(struct msm_kms *kms)
76 {
77 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
78 mdp4_enable(mdp4_kms);
79 }
80
mdp4_disable_commit(struct msm_kms * kms)81 static void mdp4_disable_commit(struct msm_kms *kms)
82 {
83 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
84 mdp4_disable(mdp4_kms);
85 }
86
mdp4_flush_commit(struct msm_kms * kms,unsigned crtc_mask)87 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask)
88 {
89 /* TODO */
90 }
91
mdp4_wait_flush(struct msm_kms * kms,unsigned crtc_mask)92 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask)
93 {
94 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
95 struct drm_crtc *crtc;
96
97 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask)
98 mdp4_crtc_wait_for_commit_done(crtc);
99 }
100
mdp4_complete_commit(struct msm_kms * kms,unsigned crtc_mask)101 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask)
102 {
103 }
104
mdp4_round_pixclk(struct msm_kms * kms,unsigned long rate,struct drm_encoder * encoder)105 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate,
106 struct drm_encoder *encoder)
107 {
108 /* if we had >1 encoder, we'd need something more clever: */
109 switch (encoder->encoder_type) {
110 case DRM_MODE_ENCODER_TMDS:
111 return mdp4_dtv_round_pixclk(encoder, rate);
112 case DRM_MODE_ENCODER_LVDS:
113 case DRM_MODE_ENCODER_DSI:
114 default:
115 return rate;
116 }
117 }
118
mdp4_destroy(struct msm_kms * kms)119 static void mdp4_destroy(struct msm_kms *kms)
120 {
121 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms));
122 struct device *dev = mdp4_kms->dev->dev;
123 struct msm_gem_address_space *aspace = kms->aspace;
124
125 if (mdp4_kms->blank_cursor_iova)
126 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->aspace);
127 drm_gem_object_put(mdp4_kms->blank_cursor_bo);
128
129 if (aspace) {
130 aspace->mmu->funcs->detach(aspace->mmu);
131 msm_gem_address_space_put(aspace);
132 }
133
134 if (mdp4_kms->rpm_enabled)
135 pm_runtime_disable(dev);
136
137 mdp_kms_destroy(&mdp4_kms->base);
138 }
139
140 static const struct mdp_kms_funcs kms_funcs = {
141 .base = {
142 .hw_init = mdp4_hw_init,
143 .irq_preinstall = mdp4_irq_preinstall,
144 .irq_postinstall = mdp4_irq_postinstall,
145 .irq_uninstall = mdp4_irq_uninstall,
146 .irq = mdp4_irq,
147 .enable_vblank = mdp4_enable_vblank,
148 .disable_vblank = mdp4_disable_vblank,
149 .enable_commit = mdp4_enable_commit,
150 .disable_commit = mdp4_disable_commit,
151 .flush_commit = mdp4_flush_commit,
152 .wait_flush = mdp4_wait_flush,
153 .complete_commit = mdp4_complete_commit,
154 .round_pixclk = mdp4_round_pixclk,
155 .destroy = mdp4_destroy,
156 },
157 .set_irqmask = mdp4_set_irqmask,
158 };
159
mdp4_disable(struct mdp4_kms * mdp4_kms)160 int mdp4_disable(struct mdp4_kms *mdp4_kms)
161 {
162 DBG("");
163
164 clk_disable_unprepare(mdp4_kms->clk);
165 clk_disable_unprepare(mdp4_kms->pclk);
166 clk_disable_unprepare(mdp4_kms->lut_clk);
167 clk_disable_unprepare(mdp4_kms->axi_clk);
168
169 return 0;
170 }
171
mdp4_enable(struct mdp4_kms * mdp4_kms)172 int mdp4_enable(struct mdp4_kms *mdp4_kms)
173 {
174 DBG("");
175
176 clk_prepare_enable(mdp4_kms->clk);
177 clk_prepare_enable(mdp4_kms->pclk);
178 clk_prepare_enable(mdp4_kms->lut_clk);
179 clk_prepare_enable(mdp4_kms->axi_clk);
180
181 return 0;
182 }
183
184
mdp4_modeset_init_intf(struct mdp4_kms * mdp4_kms,int intf_type)185 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms,
186 int intf_type)
187 {
188 struct drm_device *dev = mdp4_kms->dev;
189 struct msm_drm_private *priv = dev->dev_private;
190 struct drm_encoder *encoder;
191 struct drm_connector *connector;
192 struct device_node *panel_node;
193 int dsi_id;
194 int ret;
195
196 switch (intf_type) {
197 case DRM_MODE_ENCODER_LVDS:
198 /*
199 * bail out early if there is no panel node (no need to
200 * initialize LCDC encoder and LVDS connector)
201 */
202 panel_node = of_graph_get_remote_node(dev->dev->of_node, 0, 0);
203 if (!panel_node)
204 return 0;
205
206 encoder = mdp4_lcdc_encoder_init(dev, panel_node);
207 if (IS_ERR(encoder)) {
208 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n");
209 of_node_put(panel_node);
210 return PTR_ERR(encoder);
211 }
212
213 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */
214 encoder->possible_crtcs = 1 << DMA_P;
215
216 connector = mdp4_lvds_connector_init(dev, panel_node, encoder);
217 if (IS_ERR(connector)) {
218 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n");
219 of_node_put(panel_node);
220 return PTR_ERR(connector);
221 }
222
223 break;
224 case DRM_MODE_ENCODER_TMDS:
225 encoder = mdp4_dtv_encoder_init(dev);
226 if (IS_ERR(encoder)) {
227 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n");
228 return PTR_ERR(encoder);
229 }
230
231 /* DTV can be hooked to DMA_E: */
232 encoder->possible_crtcs = 1 << 1;
233
234 if (priv->hdmi) {
235 /* Construct bridge/connector for HDMI: */
236 ret = msm_hdmi_modeset_init(priv->hdmi, dev, encoder);
237 if (ret) {
238 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret);
239 return ret;
240 }
241 }
242
243 break;
244 case DRM_MODE_ENCODER_DSI:
245 /* only DSI1 supported for now */
246 dsi_id = 0;
247
248 if (!priv->dsi[dsi_id])
249 break;
250
251 encoder = mdp4_dsi_encoder_init(dev);
252 if (IS_ERR(encoder)) {
253 ret = PTR_ERR(encoder);
254 DRM_DEV_ERROR(dev->dev,
255 "failed to construct DSI encoder: %d\n", ret);
256 return ret;
257 }
258
259 /* TODO: Add DMA_S later? */
260 encoder->possible_crtcs = 1 << DMA_P;
261
262 ret = msm_dsi_modeset_init(priv->dsi[dsi_id], dev, encoder);
263 if (ret) {
264 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n",
265 ret);
266 return ret;
267 }
268
269 break;
270 default:
271 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n");
272 return -EINVAL;
273 }
274
275 return 0;
276 }
277
modeset_init(struct mdp4_kms * mdp4_kms)278 static int modeset_init(struct mdp4_kms *mdp4_kms)
279 {
280 struct drm_device *dev = mdp4_kms->dev;
281 struct msm_drm_private *priv = dev->dev_private;
282 struct drm_plane *plane;
283 struct drm_crtc *crtc;
284 int i, ret;
285 static const enum mdp4_pipe rgb_planes[] = {
286 RGB1, RGB2,
287 };
288 static const enum mdp4_pipe vg_planes[] = {
289 VG1, VG2,
290 };
291 static const enum mdp4_dma mdp4_crtcs[] = {
292 DMA_P, DMA_E,
293 };
294 static const char * const mdp4_crtc_names[] = {
295 "DMA_P", "DMA_E",
296 };
297 static const int mdp4_intfs[] = {
298 DRM_MODE_ENCODER_LVDS,
299 DRM_MODE_ENCODER_DSI,
300 DRM_MODE_ENCODER_TMDS,
301 };
302
303 /* construct non-private planes: */
304 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) {
305 plane = mdp4_plane_init(dev, vg_planes[i], false);
306 if (IS_ERR(plane)) {
307 DRM_DEV_ERROR(dev->dev,
308 "failed to construct plane for VG%d\n", i + 1);
309 ret = PTR_ERR(plane);
310 goto fail;
311 }
312 }
313
314 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) {
315 plane = mdp4_plane_init(dev, rgb_planes[i], true);
316 if (IS_ERR(plane)) {
317 DRM_DEV_ERROR(dev->dev,
318 "failed to construct plane for RGB%d\n", i + 1);
319 ret = PTR_ERR(plane);
320 goto fail;
321 }
322
323 crtc = mdp4_crtc_init(dev, plane, priv->num_crtcs, i,
324 mdp4_crtcs[i]);
325 if (IS_ERR(crtc)) {
326 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n",
327 mdp4_crtc_names[i]);
328 ret = PTR_ERR(crtc);
329 goto fail;
330 }
331
332 priv->num_crtcs++;
333 }
334
335 /*
336 * we currently set up two relatively fixed paths:
337 *
338 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS
339 * or
340 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel
341 *
342 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI
343 */
344
345 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) {
346 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]);
347 if (ret) {
348 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n",
349 i, ret);
350 goto fail;
351 }
352 }
353
354 return 0;
355
356 fail:
357 return ret;
358 }
359
read_mdp_hw_revision(struct mdp4_kms * mdp4_kms,u32 * major,u32 * minor)360 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms,
361 u32 *major, u32 *minor)
362 {
363 struct drm_device *dev = mdp4_kms->dev;
364 u32 version;
365
366 mdp4_enable(mdp4_kms);
367 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION);
368 mdp4_disable(mdp4_kms);
369
370 *major = FIELD(version, MDP4_VERSION_MAJOR);
371 *minor = FIELD(version, MDP4_VERSION_MINOR);
372
373 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor);
374 }
375
mdp4_kms_init(struct drm_device * dev)376 static int mdp4_kms_init(struct drm_device *dev)
377 {
378 struct platform_device *pdev = to_platform_device(dev->dev);
379 struct msm_drm_private *priv = dev->dev_private;
380 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms));
381 struct msm_kms *kms = NULL;
382 struct msm_mmu *mmu;
383 struct msm_gem_address_space *aspace;
384 int ret;
385 u32 major, minor;
386 unsigned long max_clk;
387
388 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */
389 max_clk = 266667000;
390
391 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs);
392 if (ret) {
393 DRM_DEV_ERROR(dev->dev, "failed to init kms\n");
394 goto fail;
395 }
396
397 kms = priv->kms;
398
399 mdp4_kms->dev = dev;
400
401 if (mdp4_kms->vdd) {
402 ret = regulator_enable(mdp4_kms->vdd);
403 if (ret) {
404 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret);
405 goto fail;
406 }
407 }
408
409 clk_set_rate(mdp4_kms->clk, max_clk);
410
411 read_mdp_hw_revision(mdp4_kms, &major, &minor);
412
413 if (major != 4) {
414 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n",
415 major, minor);
416 ret = -ENXIO;
417 goto fail;
418 }
419
420 mdp4_kms->rev = minor;
421
422 if (mdp4_kms->rev >= 2) {
423 if (!mdp4_kms->lut_clk) {
424 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n");
425 ret = -ENODEV;
426 goto fail;
427 }
428 clk_set_rate(mdp4_kms->lut_clk, max_clk);
429 }
430
431 pm_runtime_enable(dev->dev);
432 mdp4_kms->rpm_enabled = true;
433
434 /* make sure things are off before attaching iommu (bootloader could
435 * have left things on, in which case we'll start getting faults if
436 * we don't disable):
437 */
438 mdp4_enable(mdp4_kms);
439 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0);
440 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0);
441 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0);
442 mdp4_disable(mdp4_kms);
443 mdelay(16);
444
445 mmu = msm_iommu_new(&pdev->dev, 0);
446 if (IS_ERR(mmu)) {
447 ret = PTR_ERR(mmu);
448 goto fail;
449 } else if (!mmu) {
450 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys "
451 "contig buffers for scanout\n");
452 aspace = NULL;
453 } else {
454 aspace = msm_gem_address_space_create(mmu,
455 "mdp4", 0x1000, 0x100000000 - 0x1000);
456
457 if (IS_ERR(aspace)) {
458 if (!IS_ERR(mmu))
459 mmu->funcs->destroy(mmu);
460 ret = PTR_ERR(aspace);
461 goto fail;
462 }
463
464 kms->aspace = aspace;
465 }
466
467 ret = modeset_init(mdp4_kms);
468 if (ret) {
469 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret);
470 goto fail;
471 }
472
473 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT);
474 if (IS_ERR(mdp4_kms->blank_cursor_bo)) {
475 ret = PTR_ERR(mdp4_kms->blank_cursor_bo);
476 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret);
477 mdp4_kms->blank_cursor_bo = NULL;
478 goto fail;
479 }
480
481 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->aspace,
482 &mdp4_kms->blank_cursor_iova);
483 if (ret) {
484 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret);
485 goto fail;
486 }
487
488 dev->mode_config.min_width = 0;
489 dev->mode_config.min_height = 0;
490 dev->mode_config.max_width = 2048;
491 dev->mode_config.max_height = 2048;
492
493 return 0;
494
495 fail:
496 if (kms)
497 mdp4_destroy(kms);
498
499 return ret;
500 }
501
502 static const struct dev_pm_ops mdp4_pm_ops = {
503 .prepare = msm_kms_pm_prepare,
504 .complete = msm_kms_pm_complete,
505 };
506
mdp4_probe(struct platform_device * pdev)507 static int mdp4_probe(struct platform_device *pdev)
508 {
509 struct device *dev = &pdev->dev;
510 struct mdp4_kms *mdp4_kms;
511 int irq;
512
513 mdp4_kms = devm_kzalloc(dev, sizeof(*mdp4_kms), GFP_KERNEL);
514 if (!mdp4_kms)
515 return dev_err_probe(dev, -ENOMEM, "failed to allocate kms\n");
516
517 mdp4_kms->mmio = msm_ioremap(pdev, NULL);
518 if (IS_ERR(mdp4_kms->mmio))
519 return PTR_ERR(mdp4_kms->mmio);
520
521 irq = platform_get_irq(pdev, 0);
522 if (irq < 0)
523 return dev_err_probe(dev, irq, "failed to get irq\n");
524
525 mdp4_kms->base.base.irq = irq;
526
527 /* NOTE: driver for this regulator still missing upstream.. use
528 * _get_exclusive() and ignore the error if it does not exist
529 * (and hope that the bootloader left it on for us)
530 */
531 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd");
532 if (IS_ERR(mdp4_kms->vdd))
533 mdp4_kms->vdd = NULL;
534
535 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk");
536 if (IS_ERR(mdp4_kms->clk))
537 return dev_err_probe(dev, PTR_ERR(mdp4_kms->clk), "failed to get core_clk\n");
538
539 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk");
540 if (IS_ERR(mdp4_kms->pclk))
541 mdp4_kms->pclk = NULL;
542
543 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk");
544 if (IS_ERR(mdp4_kms->axi_clk))
545 return dev_err_probe(dev, PTR_ERR(mdp4_kms->axi_clk), "failed to get axi_clk\n");
546
547 /*
548 * This is required for revn >= 2. Handle errors here and let the kms
549 * init bail out if the clock is not provided.
550 */
551 mdp4_kms->lut_clk = devm_clk_get_optional(&pdev->dev, "lut_clk");
552 if (IS_ERR(mdp4_kms->lut_clk))
553 return dev_err_probe(dev, PTR_ERR(mdp4_kms->lut_clk), "failed to get lut_clk\n");
554
555 return msm_drv_probe(&pdev->dev, mdp4_kms_init, &mdp4_kms->base.base);
556 }
557
mdp4_remove(struct platform_device * pdev)558 static void mdp4_remove(struct platform_device *pdev)
559 {
560 component_master_del(&pdev->dev, &msm_drm_ops);
561 }
562
563 static const struct of_device_id mdp4_dt_match[] = {
564 { .compatible = "qcom,mdp4" },
565 { /* sentinel */ }
566 };
567 MODULE_DEVICE_TABLE(of, mdp4_dt_match);
568
569 static struct platform_driver mdp4_platform_driver = {
570 .probe = mdp4_probe,
571 .remove_new = mdp4_remove,
572 .shutdown = msm_kms_shutdown,
573 .driver = {
574 .name = "mdp4",
575 .of_match_table = mdp4_dt_match,
576 .pm = &mdp4_pm_ops,
577 },
578 };
579
msm_mdp4_register(void)580 void __init msm_mdp4_register(void)
581 {
582 platform_driver_register(&mdp4_platform_driver);
583 }
584
msm_mdp4_unregister(void)585 void __exit msm_mdp4_unregister(void)
586 {
587 platform_driver_unregister(&mdp4_platform_driver);
588 }
589