1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (C) 2013 Red Hat 4 * Author: Rob Clark <robdclark@gmail.com> 5 */ 6 7 #include <linux/delay.h> 8 9 #include <drm/drm_bridge.h> 10 #include <drm/drm_bridge_connector.h> 11 #include <drm/drm_vblank.h> 12 13 #include "msm_drv.h" 14 #include "msm_gem.h" 15 #include "msm_mmu.h" 16 #include "mdp4_kms.h" 17 18 static int mdp4_hw_init(struct msm_kms *kms) 19 { 20 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 21 struct drm_device *dev = mdp4_kms->dev; 22 u32 dmap_cfg, vg_cfg; 23 unsigned long clk; 24 25 pm_runtime_get_sync(dev->dev); 26 27 if (mdp4_kms->rev > 1) { 28 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER0, 0x0707ffff); 29 mdp4_write(mdp4_kms, REG_MDP4_CS_CONTROLLER1, 0x03073f3f); 30 } 31 32 mdp4_write(mdp4_kms, REG_MDP4_PORTMAP_MODE, 0x3); 33 34 /* max read pending cmd config, 3 pending requests: */ 35 mdp4_write(mdp4_kms, REG_MDP4_READ_CNFG, 0x02222); 36 37 clk = clk_get_rate(mdp4_kms->clk); 38 39 if ((mdp4_kms->rev >= 1) || (clk >= 90000000)) { 40 dmap_cfg = 0x47; /* 16 bytes-burst x 8 req */ 41 vg_cfg = 0x47; /* 16 bytes-burs x 8 req */ 42 } else { 43 dmap_cfg = 0x27; /* 8 bytes-burst x 8 req */ 44 vg_cfg = 0x43; /* 16 bytes-burst x 4 req */ 45 } 46 47 DBG("fetch config: dmap=%02x, vg=%02x", dmap_cfg, vg_cfg); 48 49 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_P), dmap_cfg); 50 mdp4_write(mdp4_kms, REG_MDP4_DMA_FETCH_CONFIG(DMA_E), dmap_cfg); 51 52 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG1), vg_cfg); 53 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(VG2), vg_cfg); 54 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB1), vg_cfg); 55 mdp4_write(mdp4_kms, REG_MDP4_PIPE_FETCH_CONFIG(RGB2), vg_cfg); 56 57 if (mdp4_kms->rev >= 2) 58 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG_UPDATE_METHOD, 1); 59 mdp4_write(mdp4_kms, REG_MDP4_LAYERMIXER_IN_CFG, 0); 60 61 /* disable CSC matrix / YUV by default: */ 62 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG1), 0); 63 mdp4_write(mdp4_kms, REG_MDP4_PIPE_OP_MODE(VG2), 0); 64 mdp4_write(mdp4_kms, REG_MDP4_DMA_P_OP_MODE, 0); 65 mdp4_write(mdp4_kms, REG_MDP4_DMA_S_OP_MODE, 0); 66 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(1), 0); 67 mdp4_write(mdp4_kms, REG_MDP4_OVLP_CSC_CONFIG(2), 0); 68 69 if (mdp4_kms->rev > 1) 70 mdp4_write(mdp4_kms, REG_MDP4_RESET_STATUS, 1); 71 72 pm_runtime_put_sync(dev->dev); 73 74 return 0; 75 } 76 77 static void mdp4_enable_commit(struct msm_kms *kms) 78 { 79 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 80 mdp4_enable(mdp4_kms); 81 } 82 83 static void mdp4_disable_commit(struct msm_kms *kms) 84 { 85 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 86 mdp4_disable(mdp4_kms); 87 } 88 89 static void mdp4_flush_commit(struct msm_kms *kms, unsigned crtc_mask) 90 { 91 /* TODO */ 92 } 93 94 static void mdp4_wait_flush(struct msm_kms *kms, unsigned crtc_mask) 95 { 96 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 97 struct drm_crtc *crtc; 98 99 for_each_crtc_mask(mdp4_kms->dev, crtc, crtc_mask) 100 mdp4_crtc_wait_for_commit_done(crtc); 101 } 102 103 static void mdp4_complete_commit(struct msm_kms *kms, unsigned crtc_mask) 104 { 105 } 106 107 static long mdp4_round_pixclk(struct msm_kms *kms, unsigned long rate, 108 struct drm_encoder *encoder) 109 { 110 /* if we had >1 encoder, we'd need something more clever: */ 111 switch (encoder->encoder_type) { 112 case DRM_MODE_ENCODER_TMDS: 113 return mdp4_dtv_round_pixclk(encoder, rate); 114 case DRM_MODE_ENCODER_LVDS: 115 case DRM_MODE_ENCODER_DSI: 116 default: 117 return rate; 118 } 119 } 120 121 static void mdp4_destroy(struct msm_kms *kms) 122 { 123 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(kms)); 124 struct device *dev = mdp4_kms->dev->dev; 125 126 if (mdp4_kms->blank_cursor_iova) 127 msm_gem_unpin_iova(mdp4_kms->blank_cursor_bo, kms->vm); 128 drm_gem_object_put(mdp4_kms->blank_cursor_bo); 129 130 if (kms->vm) { 131 struct msm_mmu *mmu = to_msm_vm(kms->vm)->mmu; 132 133 mmu->funcs->detach(mmu); 134 drm_gpuvm_put(kms->vm); 135 } 136 137 if (mdp4_kms->rpm_enabled) 138 pm_runtime_disable(dev); 139 140 mdp_kms_destroy(&mdp4_kms->base); 141 } 142 143 static const struct mdp_kms_funcs kms_funcs = { 144 .base = { 145 .hw_init = mdp4_hw_init, 146 .irq_preinstall = mdp4_irq_preinstall, 147 .irq_postinstall = mdp4_irq_postinstall, 148 .irq_uninstall = mdp4_irq_uninstall, 149 .irq = mdp4_irq, 150 .enable_vblank = mdp4_enable_vblank, 151 .disable_vblank = mdp4_disable_vblank, 152 .enable_commit = mdp4_enable_commit, 153 .disable_commit = mdp4_disable_commit, 154 .flush_commit = mdp4_flush_commit, 155 .wait_flush = mdp4_wait_flush, 156 .complete_commit = mdp4_complete_commit, 157 .round_pixclk = mdp4_round_pixclk, 158 .destroy = mdp4_destroy, 159 }, 160 .set_irqmask = mdp4_set_irqmask, 161 }; 162 163 int mdp4_disable(struct mdp4_kms *mdp4_kms) 164 { 165 DBG(""); 166 167 clk_disable_unprepare(mdp4_kms->clk); 168 clk_disable_unprepare(mdp4_kms->pclk); 169 clk_disable_unprepare(mdp4_kms->lut_clk); 170 clk_disable_unprepare(mdp4_kms->axi_clk); 171 172 return 0; 173 } 174 175 int mdp4_enable(struct mdp4_kms *mdp4_kms) 176 { 177 DBG(""); 178 179 clk_prepare_enable(mdp4_kms->clk); 180 clk_prepare_enable(mdp4_kms->pclk); 181 clk_prepare_enable(mdp4_kms->lut_clk); 182 clk_prepare_enable(mdp4_kms->axi_clk); 183 184 return 0; 185 } 186 187 188 static int mdp4_modeset_init_intf(struct mdp4_kms *mdp4_kms, 189 int intf_type) 190 { 191 struct drm_device *dev = mdp4_kms->dev; 192 struct msm_drm_private *priv = dev->dev_private; 193 struct drm_encoder *encoder; 194 struct drm_connector *connector; 195 struct drm_bridge *next_bridge; 196 int dsi_id; 197 int ret; 198 199 switch (intf_type) { 200 case DRM_MODE_ENCODER_LVDS: 201 /* 202 * bail out early if there is no panel node (no need to 203 * initialize LCDC encoder and LVDS connector) 204 */ 205 next_bridge = devm_drm_of_get_bridge(dev->dev, dev->dev->of_node, 0, 0); 206 if (IS_ERR(next_bridge)) { 207 ret = PTR_ERR(next_bridge); 208 if (ret == -ENODEV) 209 return 0; 210 return ret; 211 } 212 213 encoder = mdp4_lcdc_encoder_init(dev); 214 if (IS_ERR(encoder)) { 215 DRM_DEV_ERROR(dev->dev, "failed to construct LCDC encoder\n"); 216 return PTR_ERR(encoder); 217 } 218 219 /* LCDC can be hooked to DMA_P (TODO: Add DMA_S later?) */ 220 encoder->possible_crtcs = 1 << DMA_P; 221 222 ret = drm_bridge_attach(encoder, next_bridge, NULL, DRM_BRIDGE_ATTACH_NO_CONNECTOR); 223 if (ret) { 224 DRM_DEV_ERROR(dev->dev, "failed to attach LVDS panel/bridge: %d\n", ret); 225 226 return ret; 227 } 228 229 connector = drm_bridge_connector_init(dev, encoder); 230 if (IS_ERR(connector)) { 231 DRM_DEV_ERROR(dev->dev, "failed to initialize LVDS connector\n"); 232 return PTR_ERR(connector); 233 } 234 235 ret = drm_connector_attach_encoder(connector, encoder); 236 if (ret) { 237 DRM_DEV_ERROR(dev->dev, "failed to attach LVDS connector: %d\n", ret); 238 239 return ret; 240 } 241 242 break; 243 case DRM_MODE_ENCODER_TMDS: 244 encoder = mdp4_dtv_encoder_init(dev); 245 if (IS_ERR(encoder)) { 246 DRM_DEV_ERROR(dev->dev, "failed to construct DTV encoder\n"); 247 return PTR_ERR(encoder); 248 } 249 250 /* DTV can be hooked to DMA_E: */ 251 encoder->possible_crtcs = 1 << 1; 252 253 if (priv->kms->hdmi) { 254 /* Construct bridge/connector for HDMI: */ 255 ret = msm_hdmi_modeset_init(priv->kms->hdmi, dev, encoder); 256 if (ret) { 257 DRM_DEV_ERROR(dev->dev, "failed to initialize HDMI: %d\n", ret); 258 return ret; 259 } 260 } 261 262 break; 263 case DRM_MODE_ENCODER_DSI: 264 /* only DSI1 supported for now */ 265 dsi_id = 0; 266 267 if (!priv->kms->dsi[dsi_id]) 268 break; 269 270 encoder = mdp4_dsi_encoder_init(dev); 271 if (IS_ERR(encoder)) { 272 ret = PTR_ERR(encoder); 273 DRM_DEV_ERROR(dev->dev, 274 "failed to construct DSI encoder: %d\n", ret); 275 return ret; 276 } 277 278 /* TODO: Add DMA_S later? */ 279 encoder->possible_crtcs = 1 << DMA_P; 280 281 ret = msm_dsi_modeset_init(priv->kms->dsi[dsi_id], dev, encoder); 282 if (ret) { 283 DRM_DEV_ERROR(dev->dev, "failed to initialize DSI: %d\n", 284 ret); 285 return ret; 286 } 287 288 break; 289 default: 290 DRM_DEV_ERROR(dev->dev, "Invalid or unsupported interface\n"); 291 return -EINVAL; 292 } 293 294 return 0; 295 } 296 297 static int modeset_init(struct mdp4_kms *mdp4_kms) 298 { 299 struct drm_device *dev = mdp4_kms->dev; 300 struct drm_plane *plane; 301 struct drm_crtc *crtc; 302 int i, ret; 303 static const enum mdp4_pipe rgb_planes[] = { 304 RGB1, RGB2, 305 }; 306 static const enum mdp4_pipe vg_planes[] = { 307 VG1, VG2, 308 }; 309 static const enum mdp4_dma mdp4_crtcs[] = { 310 DMA_P, DMA_E, 311 }; 312 static const char * const mdp4_crtc_names[] = { 313 "DMA_P", "DMA_E", 314 }; 315 static const int mdp4_intfs[] = { 316 DRM_MODE_ENCODER_LVDS, 317 DRM_MODE_ENCODER_DSI, 318 DRM_MODE_ENCODER_TMDS, 319 }; 320 321 /* construct non-private planes: */ 322 for (i = 0; i < ARRAY_SIZE(vg_planes); i++) { 323 plane = mdp4_plane_init(dev, vg_planes[i], false); 324 if (IS_ERR(plane)) { 325 DRM_DEV_ERROR(dev->dev, 326 "failed to construct plane for VG%d\n", i + 1); 327 ret = PTR_ERR(plane); 328 goto fail; 329 } 330 } 331 332 for (i = 0; i < ARRAY_SIZE(mdp4_crtcs); i++) { 333 plane = mdp4_plane_init(dev, rgb_planes[i], true); 334 if (IS_ERR(plane)) { 335 DRM_DEV_ERROR(dev->dev, 336 "failed to construct plane for RGB%d\n", i + 1); 337 ret = PTR_ERR(plane); 338 goto fail; 339 } 340 341 crtc = mdp4_crtc_init(dev, plane, i, 342 mdp4_crtcs[i]); 343 if (IS_ERR(crtc)) { 344 DRM_DEV_ERROR(dev->dev, "failed to construct crtc for %s\n", 345 mdp4_crtc_names[i]); 346 ret = PTR_ERR(crtc); 347 goto fail; 348 } 349 } 350 351 /* 352 * we currently set up two relatively fixed paths: 353 * 354 * LCDC/LVDS path: RGB1 -> DMA_P -> LCDC -> LVDS 355 * or 356 * DSI path: RGB1 -> DMA_P -> DSI1 -> DSI Panel 357 * 358 * DTV/HDMI path: RGB2 -> DMA_E -> DTV -> HDMI 359 */ 360 361 for (i = 0; i < ARRAY_SIZE(mdp4_intfs); i++) { 362 ret = mdp4_modeset_init_intf(mdp4_kms, mdp4_intfs[i]); 363 if (ret) { 364 DRM_DEV_ERROR(dev->dev, "failed to initialize intf: %d, %d\n", 365 i, ret); 366 goto fail; 367 } 368 } 369 370 return 0; 371 372 fail: 373 return ret; 374 } 375 376 static void read_mdp_hw_revision(struct mdp4_kms *mdp4_kms, 377 u32 *major, u32 *minor) 378 { 379 struct drm_device *dev = mdp4_kms->dev; 380 u32 version; 381 382 mdp4_enable(mdp4_kms); 383 version = mdp4_read(mdp4_kms, REG_MDP4_VERSION); 384 mdp4_disable(mdp4_kms); 385 386 *major = FIELD(version, MDP4_VERSION_MAJOR); 387 *minor = FIELD(version, MDP4_VERSION_MINOR); 388 389 DRM_DEV_INFO(dev->dev, "MDP4 version v%d.%d", *major, *minor); 390 } 391 392 static int mdp4_kms_init(struct drm_device *dev) 393 { 394 struct platform_device *pdev = to_platform_device(dev->dev); 395 struct msm_drm_private *priv = dev->dev_private; 396 struct mdp4_kms *mdp4_kms = to_mdp4_kms(to_mdp_kms(priv->kms)); 397 struct msm_kms *kms = NULL; 398 struct msm_mmu *mmu; 399 struct drm_gpuvm *vm; 400 int ret; 401 u32 major, minor; 402 unsigned long max_clk; 403 404 /* TODO: Chips that aren't apq8064 have a 200 Mhz max_clk */ 405 max_clk = 266667000; 406 407 ret = mdp_kms_init(&mdp4_kms->base, &kms_funcs); 408 if (ret) { 409 DRM_DEV_ERROR(dev->dev, "failed to init kms\n"); 410 goto fail; 411 } 412 413 kms = priv->kms; 414 415 mdp4_kms->dev = dev; 416 417 if (mdp4_kms->vdd) { 418 ret = regulator_enable(mdp4_kms->vdd); 419 if (ret) { 420 DRM_DEV_ERROR(dev->dev, "failed to enable regulator vdd: %d\n", ret); 421 goto fail; 422 } 423 } 424 425 clk_set_rate(mdp4_kms->clk, max_clk); 426 427 read_mdp_hw_revision(mdp4_kms, &major, &minor); 428 429 if (major != 4) { 430 DRM_DEV_ERROR(dev->dev, "unexpected MDP version: v%d.%d\n", 431 major, minor); 432 ret = -ENXIO; 433 goto fail; 434 } 435 436 mdp4_kms->rev = minor; 437 438 if (mdp4_kms->rev >= 2) { 439 if (!mdp4_kms->lut_clk) { 440 DRM_DEV_ERROR(dev->dev, "failed to get lut_clk\n"); 441 ret = -ENODEV; 442 goto fail; 443 } 444 clk_set_rate(mdp4_kms->lut_clk, max_clk); 445 } 446 447 pm_runtime_enable(dev->dev); 448 mdp4_kms->rpm_enabled = true; 449 450 /* make sure things are off before attaching iommu (bootloader could 451 * have left things on, in which case we'll start getting faults if 452 * we don't disable): 453 */ 454 mdp4_enable(mdp4_kms); 455 mdp4_write(mdp4_kms, REG_MDP4_DTV_ENABLE, 0); 456 mdp4_write(mdp4_kms, REG_MDP4_LCDC_ENABLE, 0); 457 mdp4_write(mdp4_kms, REG_MDP4_DSI_ENABLE, 0); 458 mdp4_disable(mdp4_kms); 459 mdelay(16); 460 461 mmu = msm_iommu_new(&pdev->dev, 0); 462 if (IS_ERR(mmu)) { 463 ret = PTR_ERR(mmu); 464 goto fail; 465 } else if (!mmu) { 466 DRM_DEV_INFO(dev->dev, "no iommu, fallback to phys " 467 "contig buffers for scanout\n"); 468 vm = NULL; 469 } else { 470 vm = msm_gem_vm_create(dev, mmu, "mdp4", 471 0x1000, 0x100000000 - 0x1000, 472 true); 473 474 if (IS_ERR(vm)) { 475 if (!IS_ERR(mmu)) 476 mmu->funcs->destroy(mmu); 477 ret = PTR_ERR(vm); 478 goto fail; 479 } 480 481 kms->vm = vm; 482 } 483 484 ret = modeset_init(mdp4_kms); 485 if (ret) { 486 DRM_DEV_ERROR(dev->dev, "modeset_init failed: %d\n", ret); 487 goto fail; 488 } 489 490 mdp4_kms->blank_cursor_bo = msm_gem_new(dev, SZ_16K, MSM_BO_WC | MSM_BO_SCANOUT); 491 if (IS_ERR(mdp4_kms->blank_cursor_bo)) { 492 ret = PTR_ERR(mdp4_kms->blank_cursor_bo); 493 DRM_DEV_ERROR(dev->dev, "could not allocate blank-cursor bo: %d\n", ret); 494 mdp4_kms->blank_cursor_bo = NULL; 495 goto fail; 496 } 497 498 ret = msm_gem_get_and_pin_iova(mdp4_kms->blank_cursor_bo, kms->vm, 499 &mdp4_kms->blank_cursor_iova); 500 if (ret) { 501 DRM_DEV_ERROR(dev->dev, "could not pin blank-cursor bo: %d\n", ret); 502 goto fail; 503 } 504 505 dev->mode_config.min_width = 0; 506 dev->mode_config.min_height = 0; 507 dev->mode_config.max_width = 2048; 508 dev->mode_config.max_height = 2048; 509 510 return 0; 511 512 fail: 513 if (kms) 514 mdp4_destroy(kms); 515 516 return ret; 517 } 518 519 static const struct dev_pm_ops mdp4_pm_ops = { 520 .prepare = msm_kms_pm_prepare, 521 .complete = msm_kms_pm_complete, 522 }; 523 524 static int mdp4_probe(struct platform_device *pdev) 525 { 526 struct device *dev = &pdev->dev; 527 struct mdp4_kms *mdp4_kms; 528 int irq; 529 530 mdp4_kms = devm_kzalloc(dev, sizeof(*mdp4_kms), GFP_KERNEL); 531 if (!mdp4_kms) 532 return dev_err_probe(dev, -ENOMEM, "failed to allocate kms\n"); 533 534 mdp4_kms->mmio = msm_ioremap(pdev, NULL); 535 if (IS_ERR(mdp4_kms->mmio)) 536 return PTR_ERR(mdp4_kms->mmio); 537 538 irq = platform_get_irq(pdev, 0); 539 if (irq < 0) 540 return dev_err_probe(dev, irq, "failed to get irq\n"); 541 542 mdp4_kms->base.base.irq = irq; 543 544 /* NOTE: driver for this regulator still missing upstream.. use 545 * _get_exclusive() and ignore the error if it does not exist 546 * (and hope that the bootloader left it on for us) 547 */ 548 mdp4_kms->vdd = devm_regulator_get_exclusive(&pdev->dev, "vdd"); 549 if (IS_ERR(mdp4_kms->vdd)) 550 mdp4_kms->vdd = NULL; 551 552 mdp4_kms->clk = devm_clk_get(&pdev->dev, "core_clk"); 553 if (IS_ERR(mdp4_kms->clk)) 554 return dev_err_probe(dev, PTR_ERR(mdp4_kms->clk), "failed to get core_clk\n"); 555 556 mdp4_kms->pclk = devm_clk_get(&pdev->dev, "iface_clk"); 557 if (IS_ERR(mdp4_kms->pclk)) 558 mdp4_kms->pclk = NULL; 559 560 mdp4_kms->axi_clk = devm_clk_get(&pdev->dev, "bus_clk"); 561 if (IS_ERR(mdp4_kms->axi_clk)) 562 return dev_err_probe(dev, PTR_ERR(mdp4_kms->axi_clk), "failed to get axi_clk\n"); 563 564 /* 565 * This is required for revn >= 2. Handle errors here and let the kms 566 * init bail out if the clock is not provided. 567 */ 568 mdp4_kms->lut_clk = devm_clk_get_optional(&pdev->dev, "lut_clk"); 569 if (IS_ERR(mdp4_kms->lut_clk)) 570 return dev_err_probe(dev, PTR_ERR(mdp4_kms->lut_clk), "failed to get lut_clk\n"); 571 572 return msm_drv_probe(&pdev->dev, mdp4_kms_init, &mdp4_kms->base.base); 573 } 574 575 static void mdp4_remove(struct platform_device *pdev) 576 { 577 component_master_del(&pdev->dev, &msm_drm_ops); 578 } 579 580 static const struct of_device_id mdp4_dt_match[] = { 581 { .compatible = "qcom,mdp4" }, 582 { /* sentinel */ } 583 }; 584 MODULE_DEVICE_TABLE(of, mdp4_dt_match); 585 586 static struct platform_driver mdp4_platform_driver = { 587 .probe = mdp4_probe, 588 .remove = mdp4_remove, 589 .shutdown = msm_kms_shutdown, 590 .driver = { 591 .name = "mdp4", 592 .of_match_table = mdp4_dt_match, 593 .pm = &mdp4_pm_ops, 594 }, 595 }; 596 597 void __init msm_mdp4_register(void) 598 { 599 platform_driver_register(&mdp4_platform_driver); 600 } 601 602 void __exit msm_mdp4_unregister(void) 603 { 604 platform_driver_unregister(&mdp4_platform_driver); 605 } 606