1 /* SPDX-License-Identifier: GPL-2.0-only */ 2 /* 3 * Copyright (c) Qualcomm Innovation Center, Inc. All rights reserved. 4 */ 5 #ifndef __ADRENO_GEN7_17_0_SNAPSHOT_H 6 #define __ADRENO_GEN7_17_0_SNAPSHOT_H 7 8 #include "a6xx_gpu_state.h" 9 10 /* 11 * Snapshot tables for Adreno A722 (Eliza). 12 * Cluster sub-arrays that are identical to A730 reference gen7_0_0_* 13 * symbols; adreno_gen7_0_0_snapshot.h is included first in the TU. 14 */ 15 16 static const u32 gen7_17_0_rscc_registers[] = { 17 0x14000, 0x14034, 0x14036, 0x14036, 0x14040, 0x14042, 0x14044, 0x14045, 18 0x14047, 0x14047, 0x14080, 0x14084, 0x14089, 0x1408c, 0x14091, 0x14094, 19 0x14099, 0x1409c, 0x140a1, 0x140a4, 0x140a9, 0x140ac, 0x140b1, 0x140b4, 20 0x140b9, 0x140bc, 0x14100, 0x14104, 0x14114, 0x14119, 0x14124, 0x14132, 21 0x14154, 0x1416b, 0x14340, 0x14341, 0x14344, 0x14344, 0x14346, 0x1437c, 22 0x143f0, 0x143f8, 0x143fa, 0x143fe, 0x14400, 0x14404, 0x14406, 0x1440a, 23 0x1440c, 0x14410, 0x14412, 0x14416, 0x14418, 0x1441c, 0x1441e, 0x14422, 24 0x14424, 0x14424, 0x14498, 0x144a0, 0x144a2, 0x144a6, 0x144a8, 0x144ac, 25 0x144ae, 0x144b2, 0x144b4, 0x144b8, 0x144ba, 0x144be, 0x144c0, 0x144c4, 26 0x144c6, 0x144ca, 0x144cc, 0x144cc, 0x14540, 0x14548, 0x1454a, 0x1454e, 27 0x14550, 0x14554, 0x14556, 0x1455a, 0x1455c, 0x14560, 0x14562, 0x14566, 28 0x14568, 0x1456c, 0x1456e, 0x14572, 0x14574, 0x14574, 0x145e8, 0x145f0, 29 0x145f2, 0x145f6, 0x145f8, 0x145fc, 0x145fe, 0x14602, 0x14604, 0x14608, 30 0x1460a, 0x1460e, 0x14610, 0x14614, 0x14616, 0x1461a, 0x1461c, 0x1461c, 31 0x14690, 0x14698, 0x1469a, 0x1469e, 0x146a0, 0x146a4, 0x146a6, 0x146aa, 32 0x146ac, 0x146b0, 0x146b2, 0x146b6, 0x146b8, 0x146bc, 0x146be, 0x146c2, 33 0x146c4, 0x146c4, 0x14738, 0x14740, 0x14742, 0x14746, 0x14748, 0x1474c, 34 0x1474e, 0x14752, 0x14754, 0x14758, 0x1475a, 0x1475e, 0x14760, 0x14764, 35 0x14766, 0x1476a, 0x1476c, 0x1476c, 0x147e0, 0x147e8, 0x147ea, 0x147ee, 36 0x147f0, 0x147f4, 0x147f6, 0x147fa, 0x147fc, 0x14800, 0x14802, 0x14806, 37 0x14808, 0x1480c, 0x1480e, 0x14812, 0x14814, 0x14814, 0x14888, 0x14890, 38 0x14892, 0x14896, 0x14898, 0x1489c, 0x1489e, 0x148a2, 0x148a4, 0x148a8, 39 0x148aa, 0x148ae, 0x148b0, 0x148b4, 0x148b6, 0x148ba, 0x148bc, 0x148bc, 40 0x14930, 0x14938, 0x1493a, 0x1493e, 0x14940, 0x14944, 0x14946, 0x1494a, 41 0x1494c, 0x14950, 0x14952, 0x14956, 0x14958, 0x1495c, 0x1495e, 0x14962, 42 0x14964, 0x14964, 43 UINT_MAX, UINT_MAX, 44 }; 45 static_assert(IS_ALIGNED(sizeof(gen7_17_0_rscc_registers), 8)); 46 47 static const u32 gen7_17_0_cpr_registers[] = { 48 0x26800, 0x26805, 0x26808, 0x2680c, 0x26814, 0x26814, 0x2681c, 0x2681c, 49 0x26820, 0x26838, 0x26840, 0x26840, 0x26848, 0x26848, 0x26850, 0x26850, 50 0x26880, 0x2688e, 0x26980, 0x269b0, 0x269c0, 0x269c2, 0x269c6, 0x269c8, 51 0x269e0, 0x269ee, 0x269fb, 0x269ff, 0x26a02, 0x26a07, 0x26a09, 0x26a0b, 52 0x26a10, 0x26b0f, 0x27440, 0x27441, 0x27444, 0x27444, 0x27480, 0x274a2, 53 0x274ac, 0x274c4, 0x274c8, 0x274da, 54 UINT_MAX, UINT_MAX, 55 }; 56 static_assert(IS_ALIGNED(sizeof(gen7_17_0_cpr_registers), 8)); 57 58 static const u32 gen7_17_0_gpucc_registers[] = { 59 0x24000, 0x2400f, 0x24400, 0x2440f, 0x24800, 0x24805, 0x24c00, 0x24cff, 60 0x25400, 0x25404, 0x25800, 0x25804, 0x25c00, 0x25c04, 0x26000, 0x26004, 61 0x26400, 0x26405, 0x26414, 0x2641d, 0x2642a, 0x2642c, 0x2642e, 0x26432, 62 0x26434, 0x26434, 0x26443, 0x26457, 0x26459, 0x2645d, 0x2645f, 0x26464, 63 0x26477, 0x26479, 0x26489, 0x2648b, 0x2649a, 0x2649b, 0x264ad, 0x264af, 64 0x264b1, 0x264b5, 0x264d6, 0x264d8, 0x264e7, 0x264e9, 0x264f9, 0x264fa, 65 0x2650a, 0x2650d, 0x2651f, 0x26520, 0x2652d, 0x2652f, 0x2653e, 0x2653e, 66 0x26540, 0x2654e, 0x26554, 0x26573, 0x26576, 0x26576, 0x26593, 0x26593, 67 0x26600, 0x26616, 0x26620, 0x2662d, 0x26630, 0x26631, 0x26635, 0x26635, 68 0x26637, 0x26637, 0x2663a, 0x2663a, 0x26642, 0x26642, 0x26656, 0x26658, 69 0x2665b, 0x2665d, 0x2665f, 0x26662, 70 UINT_MAX, UINT_MAX, 71 }; 72 static_assert(IS_ALIGNED(sizeof(gen7_17_0_gpucc_registers), 8)); 73 74 static const u32 *gen7_17_0_external_core_regs[] = { 75 gen7_17_0_gpucc_registers, 76 gen7_17_0_cpr_registers, 77 }; 78 79 static const u32 gen7_17_0_debugbus_blocks[] = { 80 A7XX_DBGBUS_CP_0_0, 81 A7XX_DBGBUS_CP_0_1, 82 A7XX_DBGBUS_RBBM, 83 A7XX_DBGBUS_HLSQ, 84 A7XX_DBGBUS_UCHE_0, 85 A7XX_DBGBUS_TESS_BR, 86 A7XX_DBGBUS_PC_BR, 87 A7XX_DBGBUS_VFDP_BR, 88 A7XX_DBGBUS_VPC_BR, 89 A7XX_DBGBUS_TSE_BR, 90 A7XX_DBGBUS_RAS_BR, 91 A7XX_DBGBUS_VSC, 92 A7XX_DBGBUS_COM_0, 93 A7XX_DBGBUS_LRZ_BR, 94 A7XX_DBGBUS_UFC_0, 95 A7XX_DBGBUS_UFC_1, 96 A7XX_DBGBUS_GMU_GX, 97 A7XX_DBGBUS_DBGC, 98 A7XX_DBGBUS_GPC_BR, 99 A7XX_DBGBUS_LARC, 100 A7XX_DBGBUS_HLSQ_SPTP, 101 A7XX_DBGBUS_RB_0, 102 A7XX_DBGBUS_RB_1, 103 A7XX_DBGBUS_UCHE_WRAPPER, 104 A7XX_DBGBUS_CCU_0, 105 A7XX_DBGBUS_CCU_1, 106 A7XX_DBGBUS_VFD_BR_0, 107 A7XX_DBGBUS_VFD_BR_1, 108 A7XX_DBGBUS_VFD_BR_2, 109 A7XX_DBGBUS_VFD_BR_3, 110 A7XX_DBGBUS_USP_0, 111 A7XX_DBGBUS_USP_1, 112 A7XX_DBGBUS_TP_0, 113 A7XX_DBGBUS_TP_1, 114 A7XX_DBGBUS_TP_2, 115 A7XX_DBGBUS_TP_3, 116 A7XX_DBGBUS_USPTP_0, 117 A7XX_DBGBUS_USPTP_1, 118 A7XX_DBGBUS_USPTP_2, 119 A7XX_DBGBUS_USPTP_3, 120 }; 121 122 static const struct gen7_sel_reg gen7_17_0_rb_rac_sel = { 123 .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 124 .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 125 .val = 0x0, 126 }; 127 128 static const struct gen7_sel_reg gen7_17_0_rb_rbp_sel = { 129 .host_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_HOST, 130 .cd_reg = REG_A6XX_RB_SUB_BLOCK_SEL_CNTL_CD, 131 .val = 0x9, 132 }; 133 134 static const u32 gen7_17_0_post_crashdumper_registers[] = { 135 0x00535, 0x00535, 136 UINT_MAX, UINT_MAX, 137 }; 138 static_assert(IS_ALIGNED(sizeof(gen7_17_0_post_crashdumper_registers), 8)); 139 140 static const u32 gen7_17_0_gpu_registers[] = { 141 0x00000, 0x00000, 0x00002, 0x00002, 0x00011, 0x00012, 0x00016, 0x0001b, 142 0x0001f, 0x00032, 0x00038, 0x0003c, 0x00042, 0x00042, 0x00044, 0x00044, 143 0x00047, 0x00047, 0x00049, 0x0004a, 0x0004c, 0x0004c, 0x00050, 0x00050, 144 0x00056, 0x00056, 0x00073, 0x00075, 0x000ad, 0x000ae, 0x000b0, 0x000b0, 145 0x000b4, 0x000b4, 0x000b8, 0x000b8, 0x000bc, 0x000bc, 0x000c0, 0x000c0, 146 0x000c4, 0x000c4, 0x000c8, 0x000c8, 0x000cc, 0x000cc, 0x000d0, 0x000d0, 147 0x000d4, 0x000d4, 0x000d8, 0x000d8, 0x000dc, 0x000dc, 0x000e0, 0x000e0, 148 0x000e4, 0x000e4, 0x000e8, 0x000e8, 0x000ec, 0x000ec, 0x000f0, 0x000f0, 149 0x000f4, 0x000f4, 0x000f8, 0x000f8, 0x00100, 0x00100, 0x00104, 0x0010b, 150 0x0010f, 0x0011d, 0x0012f, 0x0012f, 0x00200, 0x0020d, 0x00215, 0x00243, 151 0x00260, 0x00268, 0x00272, 0x00274, 0x00286, 0x00286, 0x0028a, 0x0028a, 152 0x0028c, 0x0028c, 0x00300, 0x00401, 0x00500, 0x00500, 0x00507, 0x0050b, 153 0x0050f, 0x0050f, 0x00511, 0x00511, 0x00533, 0x00534, 0x00540, 0x00555, 154 0x00564, 0x00567, 0x00800, 0x00808, 0x00810, 0x00813, 0x00820, 0x00821, 155 0x00823, 0x00827, 0x00830, 0x00834, 0x00840, 0x00841, 0x00843, 0x00847, 156 0x0084f, 0x00886, 0x008a0, 0x008ab, 0x008c0, 0x008c0, 0x008c4, 0x008c5, 157 0x008d0, 0x008dd, 0x008f0, 0x008f3, 0x00900, 0x00903, 0x00908, 0x00911, 158 0x00928, 0x0093e, 0x00942, 0x0094d, 0x00980, 0x00984, 0x0098d, 0x0098f, 159 0x009b0, 0x009b4, 0x009c2, 0x009c9, 0x009ce, 0x009d7, 0x00a00, 0x00a00, 160 0x00a02, 0x00a03, 0x00a10, 0x00a4f, 0x00a67, 0x00a6c, 0x00a9c, 0x00a9f, 161 0x00c00, 0x00c00, 0x00c02, 0x00c04, 0x00c06, 0x00c06, 0x00c10, 0x00cd9, 162 0x00ce0, 0x00d0c, 0x00df0, 0x00df4, 0x00e01, 0x00e02, 0x00e07, 0x00e0e, 163 0x00e10, 0x00e12, 0x00e17, 0x00e17, 0x00e19, 0x00e19, 0x00e1b, 0x00e2b, 164 0x00e30, 0x00e32, 0x00e38, 0x00e3c, 165 UINT_MAX, UINT_MAX, 166 }; 167 static_assert(IS_ALIGNED(sizeof(gen7_17_0_gpu_registers), 8)); 168 169 static const u32 gen7_17_0_dbgc_registers[] = { 170 0x00600, 0x0061c, 0x0061e, 0x00634, 0x00640, 0x0065a, 0x00679, 0x0067a, 171 0x00699, 0x00699, 0x0069b, 0x0069e, 0x18400, 0x1841c, 0x1841e, 0x18434, 172 0x18440, 0x1845c, 0x18479, 0x1847c, 0x18580, 0x18581, 173 UINT_MAX, UINT_MAX, 174 }; 175 static_assert(IS_ALIGNED(sizeof(gen7_17_0_dbgc_registers), 8)); 176 177 static const u32 gen7_17_0_noncontext_pipe_br_registers[] = { 178 0x00887, 0x0088c, 0x08600, 0x08600, 0x08602, 0x08602, 0x08610, 0x0861b, 179 0x08620, 0x08620, 0x08630, 0x08630, 0x08637, 0x08639, 0x08640, 0x08640, 180 0x09600, 0x09600, 0x09602, 0x09603, 0x0960a, 0x09616, 0x09624, 0x0963a, 181 0x09640, 0x09640, 0x09e00, 0x09e00, 0x09e02, 0x09e07, 0x09e0a, 0x09e16, 182 0x09e19, 0x09e19, 0x09e1c, 0x09e1c, 0x09e20, 0x09e25, 0x09e30, 0x09e31, 183 0x09e40, 0x09e51, 0x09e64, 0x09e64, 0x09e70, 0x09e72, 0x09e78, 0x09e79, 184 0x09e80, 0x09fff, 0x0a600, 0x0a600, 0x0a603, 0x0a603, 0x0a610, 0x0a61f, 185 0x0a630, 0x0a631, 0x0a638, 0x0a638, 186 UINT_MAX, UINT_MAX, 187 }; 188 static_assert(IS_ALIGNED(sizeof(gen7_17_0_noncontext_pipe_br_registers), 8)); 189 190 static const u32 gen7_17_0_noncontext_rb_rac_pipe_br_registers[] = { 191 0x08e10, 0x08e1c, 0x08e20, 0x08e25, 0x08e51, 0x08e54, 192 UINT_MAX, UINT_MAX, 193 }; 194 static_assert(IS_ALIGNED(sizeof(gen7_17_0_noncontext_rb_rac_pipe_br_registers), 8)); 195 196 static const u32 gen7_17_0_noncontext_rb_rbp_pipe_br_registers[] = { 197 0x08e01, 0x08e01, 0x08e04, 0x08e04, 0x08e06, 0x08e09, 0x08e0c, 0x08e0c, 198 0x08e28, 0x08e28, 0x08e2c, 0x08e35, 0x08e3b, 0x08e3f, 0x08e50, 0x08e50, 199 0x08e5b, 0x08e5d, 0x08e5f, 0x08e5f, 0x08e61, 0x08e61, 0x08e63, 0x08e65, 200 0x08e68, 0x08e68, 0x08e70, 0x08e79, 0x08e80, 0x08e8f, 201 UINT_MAX, UINT_MAX, 202 }; 203 static_assert(IS_ALIGNED(sizeof(gen7_17_0_noncontext_rb_rbp_pipe_br_registers), 8)); 204 205 static const u32 gen7_17_0_pc_cluster_fe_pipe_br_registers[] = { 206 0x09800, 0x09804, 0x09806, 0x0980a, 0x09810, 0x09811, 0x09884, 0x09886, 207 0x09970, 0x09972, 0x09b00, 0x09b08, 208 UINT_MAX, UINT_MAX, 209 }; 210 static_assert(IS_ALIGNED(sizeof(gen7_17_0_pc_cluster_fe_pipe_br_registers), 8)); 211 212 static const u32 gen7_17_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers[] = { 213 0x0aa40, 0x0aabf, 214 UINT_MAX, UINT_MAX, 215 }; 216 static_assert(IS_ALIGNED(sizeof(gen7_17_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers), 8)); 217 218 static const u32 gen7_17_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers[] = { 219 0x0aa40, 0x0aabf, 220 UINT_MAX, UINT_MAX, 221 }; 222 static_assert(IS_ALIGNED(sizeof(gen7_17_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers), 8)); 223 224 static const u32 gen7_17_0_non_context_tpl1_pipe_none_usptp_registers[] = { 225 0x0b602, 0x0b602, 0x0b604, 0x0b604, 0x0b608, 0x0b60c, 0x0b60f, 0x0b621, 226 0x0b630, 0x0b633, 227 UINT_MAX, UINT_MAX, 228 }; 229 static_assert(IS_ALIGNED(sizeof(gen7_17_0_non_context_tpl1_pipe_none_usptp_registers), 8)); 230 231 static const u32 gen7_17_0_non_context_tpl1_pipe_br_usptp_registers[] = { 232 0x0b600, 0x0b600, 233 UINT_MAX, UINT_MAX, 234 }; 235 static_assert(IS_ALIGNED(sizeof(gen7_17_0_non_context_tpl1_pipe_br_usptp_registers), 8)); 236 237 static const u32 gen7_17_0_tpl1_cluster_sp_vs_pipe_br_usptp_registers[] = { 238 0x0b300, 0x0b307, 0x0b309, 0x0b309, 0x0b310, 0x0b310, 239 UINT_MAX, UINT_MAX, 240 }; 241 static_assert(IS_ALIGNED(sizeof(gen7_17_0_tpl1_cluster_sp_vs_pipe_br_usptp_registers), 8)); 242 243 static const u32 gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers[] = { 244 0x0b180, 0x0b183, 0x0b190, 0x0b195, 0x0b2c0, 0x0b2d5, 0x0b300, 0x0b307, 245 0x0b309, 0x0b309, 0x0b310, 0x0b310, 246 UINT_MAX, UINT_MAX, 247 }; 248 static_assert(IS_ALIGNED(sizeof(gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers), 8)); 249 250 /* No BV pipe — gen7_0_0_* sub-arrays are shared from adreno_gen7_0_0_snapshot.h */ 251 static struct gen7_cluster_registers gen7_17_0_clusters[] = { 252 { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, 253 gen7_17_0_noncontext_pipe_br_registers, }, 254 { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, 255 gen7_17_0_noncontext_rb_rac_pipe_br_registers, &gen7_17_0_rb_rac_sel, }, 256 { A7XX_CLUSTER_NONE, PIPE_BR, STATE_NON_CONTEXT, 257 gen7_17_0_noncontext_rb_rbp_pipe_br_registers, &gen7_17_0_rb_rbp_sel, }, 258 { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, 259 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_17_0_rb_rac_sel, }, 260 { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, 261 gen7_0_0_rb_rac_cluster_ps_pipe_br_registers, &gen7_17_0_rb_rac_sel, }, 262 { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_0, 263 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_17_0_rb_rbp_sel, }, 264 { A7XX_CLUSTER_PS, PIPE_BR, STATE_FORCE_CTXT_1, 265 gen7_0_0_rb_rbp_cluster_ps_pipe_br_registers, &gen7_17_0_rb_rbp_sel, }, 266 { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_0, 267 gen7_0_0_gras_cluster_gras_pipe_br_registers, }, 268 { A7XX_CLUSTER_GRAS, PIPE_BR, STATE_FORCE_CTXT_1, 269 gen7_0_0_gras_cluster_gras_pipe_br_registers, }, 270 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, 271 gen7_17_0_pc_cluster_fe_pipe_br_registers, }, 272 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, 273 gen7_17_0_pc_cluster_fe_pipe_br_registers, }, 274 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, 275 gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, 276 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, 277 gen7_0_0_vfd_cluster_fe_pipe_bv_registers, }, 278 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_0, 279 gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, 280 { A7XX_CLUSTER_FE, PIPE_BR, STATE_FORCE_CTXT_1, 281 gen7_0_0_vpc_cluster_fe_pipe_br_registers, }, 282 { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_0, 283 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, 284 { A7XX_CLUSTER_PC_VS, PIPE_BR, STATE_FORCE_CTXT_1, 285 gen7_0_0_vpc_cluster_pc_vs_pipe_br_registers, }, 286 { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_0, 287 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, 288 { A7XX_CLUSTER_VPC_PS, PIPE_BR, STATE_FORCE_CTXT_1, 289 gen7_0_0_vpc_cluster_vpc_ps_pipe_br_registers, }, 290 }; 291 292 /* No BV pipe; 2 SPs, 2 USPTPs */ 293 static struct gen7_sptp_cluster_registers gen7_17_0_sptp_clusters[] = { 294 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, 295 gen7_0_0_sp_noncontext_pipe_br_hlsq_state_registers, 0xae00 }, 296 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_SP_TOP, 297 gen7_0_0_sp_noncontext_pipe_br_sp_top_registers, 0xae00 }, 298 { A7XX_CLUSTER_NONE, A7XX_SP_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, 299 gen7_0_0_sp_noncontext_pipe_br_usptp_registers, 0xae00 }, 300 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, 301 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, 302 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_SP_TOP, 303 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, 304 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, 305 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, 306 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE, 307 gen7_0_0_sp_cluster_sp_vs_pipe_br_hlsq_state_registers, 0xa800 }, 308 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_SP_TOP, 309 gen7_0_0_sp_cluster_sp_vs_pipe_br_sp_top_registers, 0xa800 }, 310 { A7XX_CLUSTER_SP_VS, A7XX_SP_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, 311 gen7_0_0_sp_cluster_sp_vs_pipe_br_usptp_registers, 0xa800 }, 312 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_STATE, 313 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, 314 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_HLSQ_DP, 315 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, 316 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_SP_TOP, 317 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, 318 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, 319 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, 320 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_HLSQ_STATE, 321 gen7_17_0_sp_cluster_sp_ps_pipe_lpac_hlsq_state_registers, 0xa800 }, 322 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX0_3D_CPS_REG, PIPE_LPAC, 0, A7XX_USPTP, 323 gen7_17_0_sp_cluster_sp_ps_pipe_lpac_usptp_registers, 0xa800 }, 324 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_STATE, 325 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_state_registers, 0xa800 }, 326 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_HLSQ_DP, 327 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, 328 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_SP_TOP, 329 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, 330 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, 331 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, 332 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_HLSQ_DP, 333 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, 334 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_SP_TOP, 335 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, 336 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, 337 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, 338 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_HLSQ_DP, 339 gen7_0_0_sp_cluster_sp_ps_pipe_br_hlsq_dp_registers, 0xa800 }, 340 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_SP_TOP, 341 gen7_0_0_sp_cluster_sp_ps_pipe_br_sp_top_registers, 0xa800 }, 342 { A7XX_CLUSTER_SP_PS, A7XX_SP_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, 343 gen7_0_0_sp_cluster_sp_ps_pipe_br_usptp_registers, 0xa800 }, 344 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_NONE, 0, A7XX_USPTP, 345 gen7_17_0_non_context_tpl1_pipe_none_usptp_registers, 0xb600 }, 346 { A7XX_CLUSTER_NONE, A7XX_TP0_NCTX_REG, PIPE_BR, 0, A7XX_USPTP, 347 gen7_17_0_non_context_tpl1_pipe_br_usptp_registers, 0xb600 }, 348 { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX0_3D_CVS_REG, PIPE_BR, 0, A7XX_USPTP, 349 gen7_17_0_tpl1_cluster_sp_vs_pipe_br_usptp_registers, 0xb000 }, 350 { A7XX_CLUSTER_SP_VS, A7XX_TP0_CTX1_3D_CVS_REG, PIPE_BR, 1, A7XX_USPTP, 351 gen7_17_0_tpl1_cluster_sp_vs_pipe_br_usptp_registers, 0xb000 }, 352 { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX0_3D_CPS_REG, PIPE_BR, 0, A7XX_USPTP, 353 gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers, 0xb000 }, 354 { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX1_3D_CPS_REG, PIPE_BR, 1, A7XX_USPTP, 355 gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers, 0xb000 }, 356 { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX2_3D_CPS_REG, PIPE_BR, 2, A7XX_USPTP, 357 gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers, 0xb000 }, 358 { A7XX_CLUSTER_SP_PS, A7XX_TP0_CTX3_3D_CPS_REG, PIPE_BR, 3, A7XX_USPTP, 359 gen7_17_0_tpl1_cluster_sp_ps_pipe_br_usptp_registers, 0xb000 }, 360 }; 361 362 static struct gen7_shader_block gen7_17_0_shader_blocks[] = { 363 { A7XX_TP0_TMO_DATA, 0x0200, 2, 2, PIPE_BR, A7XX_USPTP }, 364 { A7XX_TP0_SMO_DATA, 0x0080, 2, 2, PIPE_BR, A7XX_USPTP }, 365 { A7XX_TP0_MIPMAP_BASE_DATA, 0x03c0, 2, 2, PIPE_BR, A7XX_USPTP }, 366 { A7XX_SP_INST_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 367 { A7XX_SP_INST_DATA_1, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 368 { A7XX_SP_LB_0_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 369 { A7XX_SP_LB_1_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 370 { A7XX_SP_LB_2_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 371 { A7XX_SP_LB_3_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 372 { A7XX_SP_LB_4_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 373 { A7XX_SP_LB_5_DATA, 0x0800, 2, 2, PIPE_BR, A7XX_USPTP }, 374 { A7XX_SP_CB_RAM, 0x0390, 2, 2, PIPE_BR, A7XX_USPTP }, 375 { A7XX_SP_INST_TAG, 0x0090, 2, 2, PIPE_BR, A7XX_USPTP }, 376 { A7XX_SP_TMO_TAG, 0x0080, 2, 2, PIPE_BR, A7XX_USPTP }, 377 { A7XX_SP_SMO_TAG, 0x0080, 2, 2, PIPE_BR, A7XX_USPTP }, 378 { A7XX_SP_STATE_DATA, 0x0040, 2, 2, PIPE_BR, A7XX_USPTP }, 379 { A7XX_SP_HWAVE_RAM, 0x0100, 2, 2, PIPE_BR, A7XX_USPTP }, 380 { A7XX_SP_L0_INST_BUF, 0x0050, 2, 2, PIPE_BR, A7XX_USPTP }, 381 { A7XX_HLSQ_CVS_BE_CTXT_BUF_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 382 { A7XX_HLSQ_CPS_BE_CTXT_BUF_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 383 { A7XX_HLSQ_GFX_CVS_BE_CTXT_BUF_RAM, 0x0300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 384 { A7XX_HLSQ_GFX_CPS_BE_CTXT_BUF_RAM, 0x0300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 385 { A7XX_HLSQ_CHUNK_CVS_RAM, 0x01c0, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 386 { A7XX_HLSQ_CHUNK_CPS_RAM, 0x0300, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 387 { A7XX_HLSQ_CHUNK_CVS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 388 { A7XX_HLSQ_CHUNK_CPS_RAM_TAG, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 389 { A7XX_HLSQ_ICB_CVS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 390 { A7XX_HLSQ_ICB_CPS_CB_BASE_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 391 { A7XX_HLSQ_CVS_MISC_RAM, 0x0280, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 392 { A7XX_HLSQ_CPS_MISC_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 393 { A7XX_HLSQ_CPS_MISC_RAM_1, 0x0200, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 394 { A7XX_HLSQ_INST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 395 { A7XX_HLSQ_GFX_CVS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 396 { A7XX_HLSQ_GFX_CPS_CONST_RAM, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 397 { A7XX_HLSQ_CVS_MISC_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 398 { A7XX_HLSQ_CPS_MISC_RAM_TAG, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 399 { A7XX_HLSQ_INST_RAM_TAG, 0x0080, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 400 { A7XX_HLSQ_GFX_CVS_CONST_RAM_TAG, 0x0064, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 401 { A7XX_HLSQ_GFX_CPS_CONST_RAM_TAG, 0x0064, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 402 { A7XX_HLSQ_INST_RAM_1, 0x0800, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 403 { A7XX_HLSQ_STPROC_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 404 { A7XX_HLSQ_BV_BE_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 405 { A7XX_HLSQ_DATAPATH_META, 0x0020, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 406 { A7XX_HLSQ_FRONTEND_META, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 407 { A7XX_HLSQ_INDIRECT_META, 0x0010, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 408 { A7XX_HLSQ_BACKEND_META, 0x0040, 1, 1, PIPE_BR, A7XX_HLSQ_STATE }, 409 }; 410 411 static struct gen7_reg_list gen7_17_0_reg_list[] = { 412 { gen7_17_0_gpu_registers, NULL }, 413 { gen7_17_0_dbgc_registers, NULL }, 414 { NULL, NULL }, 415 }; 416 417 static const struct a6xx_indexed_registers gen7_17_0_cp_indexed_reglist[] = { 418 { "CP_SQE_STAT", REG_A6XX_CP_SQE_STAT_ADDR, 419 REG_A6XX_CP_SQE_STAT_DATA, 0x40, NULL }, 420 { "CP_DRAW_STATE", REG_A6XX_CP_DRAW_STATE_ADDR, 421 REG_A6XX_CP_DRAW_STATE_DATA, 0x100, NULL }, 422 { "CP_SQE_UCODE_DBG", REG_A6XX_CP_SQE_UCODE_DBG_ADDR, 423 REG_A6XX_CP_SQE_UCODE_DBG_DATA, 0x8000, NULL }, 424 { "CP_ROQ_DBG", REG_A6XX_CP_ROQ_DBG_ADDR, 425 REG_A6XX_CP_ROQ_DBG_DATA, 0, a7xx_get_cp_roq_size }, 426 }; 427 428 #endif /* __ADRENO_GEN7_17_0_SNAPSHOT_H */ 429