1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2018 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved. 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/module.h> 10 #include <linux/mutex.h> 11 #include <linux/bitfield.h> 12 #include <linux/platform_device.h> 13 #include <drm/drmP.h> 14 #include <drm/drm_atomic.h> 15 #include <drm/drm_atomic_helper.h> 16 #include <drm/drm_plane_helper.h> 17 #include <drm/drm_gem_cma_helper.h> 18 #include <drm/drm_fb_cma_helper.h> 19 #include <drm/drm_gem_framebuffer_helper.h> 20 #include <drm/drm_rect.h> 21 22 #include "meson_overlay.h" 23 #include "meson_vpp.h" 24 #include "meson_viu.h" 25 #include "meson_canvas.h" 26 #include "meson_registers.h" 27 28 /* VD1_IF0_GEN_REG */ 29 #define VD_URGENT_CHROMA BIT(28) 30 #define VD_URGENT_LUMA BIT(27) 31 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines) 32 #define VD_DEMUX_MODE_RGB BIT(16) 33 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val) 34 #define VD_CHRO_RPT_LASTL_CTRL BIT(6) 35 #define VD_LITTLE_ENDIAN BIT(4) 36 #define VD_SEPARATE_EN BIT(1) 37 #define VD_ENABLE BIT(0) 38 39 /* VD1_IF0_CANVAS0 */ 40 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr) 41 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr) 42 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr) 43 44 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */ 45 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value) 46 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value) 47 48 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */ 49 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value) 50 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value) 51 52 /* VD1_IF0_GEN_REG2 */ 53 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value) 54 55 /* VIU_VD1_FMT_CTRL */ 56 #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value) 57 #define VD_HORZ_FMT_EN BIT(20) 58 #define VD_VERT_RPT_LINE0 BIT(16) 59 #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value) 60 #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value) 61 #define VD_VERT_FMT_EN BIT(0) 62 63 /* VPP_POSTBLEND_VD1_H_START_END */ 64 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value) 65 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), value) 66 67 /* VPP_POSTBLEND_VD1_V_START_END */ 68 #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value) 69 #define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value) 70 71 /* VPP_BLEND_VD2_V_START_END */ 72 #define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value) 73 #define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value) 74 75 /* VIU_VD1_FMT_W */ 76 #define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value) 77 #define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value) 78 79 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */ 80 #define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value) 81 #define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value) 82 83 struct meson_overlay { 84 struct drm_plane base; 85 struct meson_drm *priv; 86 }; 87 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base) 88 89 #define FRAC_16_16(mult, div) (((mult) << 16) / (div)) 90 91 static int meson_overlay_atomic_check(struct drm_plane *plane, 92 struct drm_plane_state *state) 93 { 94 struct drm_crtc_state *crtc_state; 95 96 if (!state->crtc) 97 return 0; 98 99 crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc); 100 if (IS_ERR(crtc_state)) 101 return PTR_ERR(crtc_state); 102 103 return drm_atomic_helper_check_plane_state(state, crtc_state, 104 FRAC_16_16(1, 5), 105 FRAC_16_16(5, 1), 106 true, true); 107 } 108 109 /* Takes a fixed 16.16 number and converts it to integer. */ 110 static inline int64_t fixed16_to_int(int64_t value) 111 { 112 return value >> 16; 113 } 114 115 static const uint8_t skip_tab[6] = { 116 0x24, 0x04, 0x68, 0x48, 0x28, 0x08, 117 }; 118 119 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase, 120 int *repeat, bool interlace) 121 { 122 int offset_in = 0; 123 int offset_out = 0; 124 int repeat_skip = 0; 125 126 if (!interlace && ratio_y > (1 << 18)) 127 offset_out = (1 * ratio_y) >> 10; 128 129 while ((offset_in + (4 << 8)) <= offset_out) { 130 repeat_skip++; 131 offset_in += 4 << 8; 132 } 133 134 *phase = (offset_out - offset_in) >> 2; 135 136 if (*phase > 0x100) 137 repeat_skip++; 138 139 *phase = *phase & 0xff; 140 141 if (repeat_skip > 5) 142 repeat_skip = 5; 143 144 *repeat = skip_tab[repeat_skip]; 145 } 146 147 static void meson_overlay_setup_scaler_params(struct meson_drm *priv, 148 struct drm_plane *plane, 149 bool interlace_mode) 150 { 151 struct drm_crtc_state *crtc_state = priv->crtc->state; 152 int video_top, video_left, video_width, video_height; 153 struct drm_plane_state *state = plane->state; 154 unsigned int vd_start_lines, vd_end_lines; 155 unsigned int hd_start_lines, hd_end_lines; 156 unsigned int crtc_height, crtc_width; 157 unsigned int vsc_startp, vsc_endp; 158 unsigned int hsc_startp, hsc_endp; 159 unsigned int crop_top, crop_left; 160 int vphase, vphase_repeat_skip; 161 unsigned int ratio_x, ratio_y; 162 int temp_height, temp_width; 163 unsigned int w_in, h_in; 164 int temp, start, end; 165 166 if (!crtc_state) { 167 DRM_ERROR("Invalid crtc_state\n"); 168 return; 169 } 170 171 crtc_height = crtc_state->mode.vdisplay; 172 crtc_width = crtc_state->mode.hdisplay; 173 174 w_in = fixed16_to_int(state->src_w); 175 h_in = fixed16_to_int(state->src_h); 176 crop_top = fixed16_to_int(state->src_x); 177 crop_left = fixed16_to_int(state->src_x); 178 179 video_top = state->crtc_y; 180 video_left = state->crtc_x; 181 video_width = state->crtc_w; 182 video_height = state->crtc_h; 183 184 DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n", 185 crtc_width, crtc_height, interlace_mode); 186 DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n", 187 w_in, h_in, crop_top, crop_left); 188 DRM_DEBUG("video top %d left %d width %d height %d\n", 189 video_top, video_left, video_width, video_height); 190 191 ratio_x = (w_in << 18) / video_width; 192 ratio_y = (h_in << 18) / video_height; 193 194 if (ratio_x * video_width < (w_in << 18)) 195 ratio_x++; 196 197 DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y); 198 199 meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip, 200 interlace_mode); 201 202 DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip); 203 204 /* Vertical */ 205 206 start = video_top + video_height / 2 - ((h_in << 17) / ratio_y); 207 end = (h_in << 18) / ratio_y + start - 1; 208 209 if (video_top < 0 && start < 0) 210 vd_start_lines = (-(start) * ratio_y) >> 18; 211 else if (start < video_top) 212 vd_start_lines = ((video_top - start) * ratio_y) >> 18; 213 else 214 vd_start_lines = 0; 215 216 if (video_top < 0) 217 temp_height = min_t(unsigned int, 218 video_top + video_height - 1, 219 crtc_height - 1); 220 else 221 temp_height = min_t(unsigned int, 222 video_top + video_height - 1, 223 crtc_height - 1) - video_top + 1; 224 225 temp = vd_start_lines + (temp_height * ratio_y >> 18); 226 vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1); 227 228 vd_start_lines += crop_left; 229 vd_end_lines += crop_left; 230 231 /* 232 * TOFIX: Input frames are handled and scaled like progressive frames, 233 * proper handling of interlaced field input frames need to be figured 234 * out using the proper framebuffer flags set by userspace. 235 */ 236 if (interlace_mode) { 237 start >>= 1; 238 end >>= 1; 239 } 240 241 vsc_startp = max_t(int, start, 242 max_t(int, 0, video_top)); 243 vsc_endp = min_t(int, end, 244 min_t(int, crtc_height - 1, 245 video_top + video_height - 1)); 246 247 DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n", 248 vsc_startp, vsc_endp, vd_start_lines, vd_end_lines); 249 250 /* Horizontal */ 251 252 start = video_left + video_width / 2 - ((w_in << 17) / ratio_x); 253 end = (w_in << 18) / ratio_x + start - 1; 254 255 if (video_left < 0 && start < 0) 256 hd_start_lines = (-(start) * ratio_x) >> 18; 257 else if (start < video_left) 258 hd_start_lines = ((video_left - start) * ratio_x) >> 18; 259 else 260 hd_start_lines = 0; 261 262 if (video_left < 0) 263 temp_width = min_t(unsigned int, 264 video_left + video_width - 1, 265 crtc_width - 1); 266 else 267 temp_width = min_t(unsigned int, 268 video_left + video_width - 1, 269 crtc_width - 1) - video_left + 1; 270 271 temp = hd_start_lines + (temp_width * ratio_x >> 18); 272 hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1); 273 274 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1; 275 hsc_startp = max_t(int, start, max_t(int, 0, video_left)); 276 hsc_endp = min_t(int, end, min_t(int, crtc_width - 1, 277 video_left + video_width - 1)); 278 279 hd_start_lines += crop_top; 280 hd_end_lines += crop_top; 281 282 DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n", 283 hsc_startp, hsc_endp, hd_start_lines, hd_end_lines); 284 285 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; 286 287 priv->viu.vpp_vsc_ini_phase = vphase << 8; 288 priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) | 289 vphase_repeat_skip; 290 291 priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) | 292 VD_X_END(hd_end_lines); 293 priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) | 294 VD_X_END(hd_end_lines >> 1); 295 296 priv->viu.viu_vd1_fmt_w = 297 VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) | 298 VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1); 299 300 priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) | 301 VD_Y_END(vd_end_lines); 302 303 priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) | 304 VD_Y_END(vd_end_lines >> 1); 305 306 priv->viu.vpp_pic_in_height = h_in; 307 308 priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) | 309 VD_H_END(hsc_endp); 310 priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) | 311 VD_H_END(hd_end_lines); 312 priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) | 313 VD_REGION24_START(hsc_startp); 314 priv->viu.vpp_hsc_region34_startp = 315 VD_REGION13_END(hsc_startp) | 316 VD_REGION24_START(hsc_endp - hsc_startp); 317 priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp; 318 priv->viu.vpp_hsc_start_phase_step = ratio_x << 6; 319 priv->viu.vpp_hsc_region1_phase_slope = 0; 320 priv->viu.vpp_hsc_region3_phase_slope = 0; 321 priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16); 322 323 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1; 324 priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1; 325 326 priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) | 327 VD_V_END(vsc_endp); 328 priv->viu.vpp_blend_vd2_v_start_end = 329 VD2_V_START((vd_end_lines + 1) >> 1) | 330 VD2_V_END(vd_end_lines); 331 332 priv->viu.vpp_vsc_region12_startp = 0; 333 priv->viu.vpp_vsc_region34_startp = 334 VD_REGION13_END(vsc_endp - vsc_startp) | 335 VD_REGION24_START(vsc_endp - vsc_startp); 336 priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp; 337 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6; 338 } 339 340 static void meson_overlay_atomic_update(struct drm_plane *plane, 341 struct drm_plane_state *old_state) 342 { 343 struct meson_overlay *meson_overlay = to_meson_overlay(plane); 344 struct drm_plane_state *state = plane->state; 345 struct drm_framebuffer *fb = state->fb; 346 struct meson_drm *priv = meson_overlay->priv; 347 struct drm_gem_cma_object *gem; 348 unsigned long flags; 349 bool interlace_mode; 350 351 DRM_DEBUG_DRIVER("\n"); 352 353 /* Fallback is canvas provider is not available */ 354 if (!priv->canvas) { 355 priv->canvas_id_vd1_0 = MESON_CANVAS_ID_VD1_0; 356 priv->canvas_id_vd1_1 = MESON_CANVAS_ID_VD1_1; 357 priv->canvas_id_vd1_2 = MESON_CANVAS_ID_VD1_2; 358 } 359 360 interlace_mode = state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE; 361 362 spin_lock_irqsave(&priv->drm->event_lock, flags); 363 364 priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA | 365 VD_URGENT_LUMA | 366 VD_HOLD_LINES(9) | 367 VD_CHRO_RPT_LASTL_CTRL | 368 VD_ENABLE; 369 370 /* Setup scaler params */ 371 meson_overlay_setup_scaler_params(priv, plane, interlace_mode); 372 373 priv->viu.vd1_if0_repeat_loop = 0; 374 priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0; 375 priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0; 376 priv->viu.vd1_range_map_y = 0; 377 priv->viu.vd1_range_map_cb = 0; 378 priv->viu.vd1_range_map_cr = 0; 379 380 /* Default values for RGB888/YUV444 */ 381 priv->viu.vd1_if0_gen_reg2 = 0; 382 priv->viu.viu_vd1_fmt_ctrl = 0; 383 384 switch (fb->format->format) { 385 /* TOFIX DRM_FORMAT_RGB888 should be supported */ 386 case DRM_FORMAT_YUYV: 387 priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1); 388 priv->viu.vd1_if0_canvas0 = 389 CANVAS_ADDR2(priv->canvas_id_vd1_0) | 390 CANVAS_ADDR1(priv->canvas_id_vd1_0) | 391 CANVAS_ADDR0(priv->canvas_id_vd1_0); 392 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */ 393 VD_HORZ_FMT_EN | 394 VD_VERT_RPT_LINE0 | 395 VD_VERT_INITIAL_PHASE(12) | 396 VD_VERT_PHASE_STEP(16) | /* /2 */ 397 VD_VERT_FMT_EN; 398 break; 399 case DRM_FORMAT_NV12: 400 case DRM_FORMAT_NV21: 401 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN; 402 priv->viu.vd1_if0_canvas0 = 403 CANVAS_ADDR2(priv->canvas_id_vd1_1) | 404 CANVAS_ADDR1(priv->canvas_id_vd1_1) | 405 CANVAS_ADDR0(priv->canvas_id_vd1_0); 406 if (fb->format->format == DRM_FORMAT_NV12) 407 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1); 408 else 409 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2); 410 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */ 411 VD_HORZ_FMT_EN | 412 VD_VERT_RPT_LINE0 | 413 VD_VERT_INITIAL_PHASE(12) | 414 VD_VERT_PHASE_STEP(8) | /* /4 */ 415 VD_VERT_FMT_EN; 416 break; 417 case DRM_FORMAT_YUV444: 418 case DRM_FORMAT_YUV422: 419 case DRM_FORMAT_YUV420: 420 case DRM_FORMAT_YUV411: 421 case DRM_FORMAT_YUV410: 422 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN; 423 priv->viu.vd1_if0_canvas0 = 424 CANVAS_ADDR2(priv->canvas_id_vd1_2) | 425 CANVAS_ADDR1(priv->canvas_id_vd1_1) | 426 CANVAS_ADDR0(priv->canvas_id_vd1_0); 427 switch (fb->format->format) { 428 case DRM_FORMAT_YUV422: 429 priv->viu.viu_vd1_fmt_ctrl = 430 VD_HORZ_Y_C_RATIO(1) | /* /2 */ 431 VD_HORZ_FMT_EN | 432 VD_VERT_RPT_LINE0 | 433 VD_VERT_INITIAL_PHASE(12) | 434 VD_VERT_PHASE_STEP(16) | /* /2 */ 435 VD_VERT_FMT_EN; 436 break; 437 case DRM_FORMAT_YUV420: 438 priv->viu.viu_vd1_fmt_ctrl = 439 VD_HORZ_Y_C_RATIO(1) | /* /2 */ 440 VD_HORZ_FMT_EN | 441 VD_VERT_RPT_LINE0 | 442 VD_VERT_INITIAL_PHASE(12) | 443 VD_VERT_PHASE_STEP(8) | /* /4 */ 444 VD_VERT_FMT_EN; 445 break; 446 case DRM_FORMAT_YUV411: 447 priv->viu.viu_vd1_fmt_ctrl = 448 VD_HORZ_Y_C_RATIO(2) | /* /4 */ 449 VD_HORZ_FMT_EN | 450 VD_VERT_RPT_LINE0 | 451 VD_VERT_INITIAL_PHASE(12) | 452 VD_VERT_PHASE_STEP(16) | /* /2 */ 453 VD_VERT_FMT_EN; 454 break; 455 case DRM_FORMAT_YUV410: 456 priv->viu.viu_vd1_fmt_ctrl = 457 VD_HORZ_Y_C_RATIO(2) | /* /4 */ 458 VD_HORZ_FMT_EN | 459 VD_VERT_RPT_LINE0 | 460 VD_VERT_INITIAL_PHASE(12) | 461 VD_VERT_PHASE_STEP(8) | /* /4 */ 462 VD_VERT_FMT_EN; 463 break; 464 } 465 break; 466 } 467 468 /* Update Canvas with buffer address */ 469 priv->viu.vd1_planes = drm_format_num_planes(fb->format->format); 470 471 switch (priv->viu.vd1_planes) { 472 case 3: 473 gem = drm_fb_cma_get_gem_obj(fb, 2); 474 priv->viu.vd1_addr2 = gem->paddr + fb->offsets[2]; 475 priv->viu.vd1_stride2 = fb->pitches[2]; 476 priv->viu.vd1_height2 = 477 drm_format_plane_height(fb->height, 478 fb->format->format, 2); 479 DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n", 480 priv->viu.vd1_addr2, 481 priv->viu.vd1_stride2, 482 priv->viu.vd1_height2); 483 /* fallthrough */ 484 case 2: 485 gem = drm_fb_cma_get_gem_obj(fb, 1); 486 priv->viu.vd1_addr1 = gem->paddr + fb->offsets[1]; 487 priv->viu.vd1_stride1 = fb->pitches[1]; 488 priv->viu.vd1_height1 = 489 drm_format_plane_height(fb->height, 490 fb->format->format, 1); 491 DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n", 492 priv->viu.vd1_addr1, 493 priv->viu.vd1_stride1, 494 priv->viu.vd1_height1); 495 /* fallthrough */ 496 case 1: 497 gem = drm_fb_cma_get_gem_obj(fb, 0); 498 priv->viu.vd1_addr0 = gem->paddr + fb->offsets[0]; 499 priv->viu.vd1_stride0 = fb->pitches[0]; 500 priv->viu.vd1_height0 = 501 drm_format_plane_height(fb->height, 502 fb->format->format, 0); 503 DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n", 504 priv->viu.vd1_addr0, 505 priv->viu.vd1_stride0, 506 priv->viu.vd1_height0); 507 } 508 509 priv->viu.vd1_enabled = true; 510 511 spin_unlock_irqrestore(&priv->drm->event_lock, flags); 512 513 DRM_DEBUG_DRIVER("\n"); 514 } 515 516 static void meson_overlay_atomic_disable(struct drm_plane *plane, 517 struct drm_plane_state *old_state) 518 { 519 struct meson_overlay *meson_overlay = to_meson_overlay(plane); 520 struct meson_drm *priv = meson_overlay->priv; 521 522 DRM_DEBUG_DRIVER("\n"); 523 524 priv->viu.vd1_enabled = false; 525 526 /* Disable VD1 */ 527 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0, 528 priv->io_base + _REG(VPP_MISC)); 529 530 } 531 532 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = { 533 .atomic_check = meson_overlay_atomic_check, 534 .atomic_disable = meson_overlay_atomic_disable, 535 .atomic_update = meson_overlay_atomic_update, 536 .prepare_fb = drm_gem_fb_prepare_fb, 537 }; 538 539 static const struct drm_plane_funcs meson_overlay_funcs = { 540 .update_plane = drm_atomic_helper_update_plane, 541 .disable_plane = drm_atomic_helper_disable_plane, 542 .destroy = drm_plane_cleanup, 543 .reset = drm_atomic_helper_plane_reset, 544 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state, 545 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state, 546 }; 547 548 static const uint32_t supported_drm_formats[] = { 549 DRM_FORMAT_YUYV, 550 DRM_FORMAT_NV12, 551 DRM_FORMAT_NV21, 552 DRM_FORMAT_YUV444, 553 DRM_FORMAT_YUV422, 554 DRM_FORMAT_YUV420, 555 DRM_FORMAT_YUV411, 556 DRM_FORMAT_YUV410, 557 }; 558 559 int meson_overlay_create(struct meson_drm *priv) 560 { 561 struct meson_overlay *meson_overlay; 562 struct drm_plane *plane; 563 564 DRM_DEBUG_DRIVER("\n"); 565 566 meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay), 567 GFP_KERNEL); 568 if (!meson_overlay) 569 return -ENOMEM; 570 571 meson_overlay->priv = priv; 572 plane = &meson_overlay->base; 573 574 drm_universal_plane_init(priv->drm, plane, 0xFF, 575 &meson_overlay_funcs, 576 supported_drm_formats, 577 ARRAY_SIZE(supported_drm_formats), 578 NULL, 579 DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane"); 580 581 drm_plane_helper_add(plane, &meson_overlay_helper_funcs); 582 583 priv->overlay_plane = plane; 584 585 DRM_DEBUG_DRIVER("\n"); 586 587 return 0; 588 } 589