1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (C) 2018 BayLibre, SAS
4 * Author: Neil Armstrong <narmstrong@baylibre.com>
5 * Copyright (C) 2015 Amlogic, Inc. All rights reserved.
6 */
7
8 #include <linux/bitfield.h>
9
10 #include <drm/drm_atomic.h>
11 #include <drm/drm_atomic_helper.h>
12 #include <drm/drm_blend.h>
13 #include <drm/drm_device.h>
14 #include <drm/drm_fb_dma_helper.h>
15 #include <drm/drm_fourcc.h>
16 #include <drm/drm_framebuffer.h>
17 #include <drm/drm_gem_atomic_helper.h>
18 #include <drm/drm_gem_dma_helper.h>
19
20 #include "meson_overlay.h"
21 #include "meson_registers.h"
22 #include "meson_viu.h"
23 #include "meson_vpp.h"
24
25 /* VD1_IF0_GEN_REG */
26 #define VD_URGENT_CHROMA BIT(28)
27 #define VD_URGENT_LUMA BIT(27)
28 #define VD_HOLD_LINES(lines) FIELD_PREP(GENMASK(24, 19), lines)
29 #define VD_DEMUX_MODE_RGB BIT(16)
30 #define VD_BYTES_PER_PIXEL(val) FIELD_PREP(GENMASK(15, 14), val)
31 #define VD_CHRO_RPT_LASTL_CTRL BIT(6)
32 #define VD_LITTLE_ENDIAN BIT(4)
33 #define VD_SEPARATE_EN BIT(1)
34 #define VD_ENABLE BIT(0)
35
36 /* VD1_IF0_CANVAS0 */
37 #define CANVAS_ADDR2(addr) FIELD_PREP(GENMASK(23, 16), addr)
38 #define CANVAS_ADDR1(addr) FIELD_PREP(GENMASK(15, 8), addr)
39 #define CANVAS_ADDR0(addr) FIELD_PREP(GENMASK(7, 0), addr)
40
41 /* VD1_IF0_LUMA_X0 VD1_IF0_CHROMA_X0 */
42 #define VD_X_START(value) FIELD_PREP(GENMASK(14, 0), value)
43 #define VD_X_END(value) FIELD_PREP(GENMASK(30, 16), value)
44
45 /* VD1_IF0_LUMA_Y0 VD1_IF0_CHROMA_Y0 */
46 #define VD_Y_START(value) FIELD_PREP(GENMASK(12, 0), value)
47 #define VD_Y_END(value) FIELD_PREP(GENMASK(28, 16), value)
48
49 /* VD1_IF0_GEN_REG2 */
50 #define VD_COLOR_MAP(value) FIELD_PREP(GENMASK(1, 0), value)
51
52 /* VIU_VD1_FMT_CTRL */
53 #define VD_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
54 #define VD_HORZ_FMT_EN BIT(20)
55 #define VD_VERT_RPT_LINE0 BIT(16)
56 #define VD_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
57 #define VD_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
58 #define VD_VERT_FMT_EN BIT(0)
59
60 /* VPP_POSTBLEND_VD1_H_START_END */
61 #define VD_H_END(value) FIELD_PREP(GENMASK(11, 0), value)
62 #define VD_H_START(value) FIELD_PREP(GENMASK(27, 16), \
63 ((value) & GENMASK(13, 0)))
64
65 /* VPP_POSTBLEND_VD1_V_START_END */
66 #define VD_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
67 #define VD_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
68
69 /* VPP_BLEND_VD2_V_START_END */
70 #define VD2_V_END(value) FIELD_PREP(GENMASK(11, 0), value)
71 #define VD2_V_START(value) FIELD_PREP(GENMASK(27, 16), value)
72
73 /* VIU_VD1_FMT_W */
74 #define VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
75 #define VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
76
77 /* VPP_HSC_REGION12_STARTP VPP_HSC_REGION34_STARTP */
78 #define VD_REGION24_START(value) FIELD_PREP(GENMASK(11, 0), value)
79 #define VD_REGION13_END(value) FIELD_PREP(GENMASK(27, 16), value)
80
81 /* AFBC_ENABLE */
82 #define AFBC_DEC_ENABLE BIT(8)
83 #define AFBC_FRM_START BIT(0)
84
85 /* AFBC_MODE */
86 #define AFBC_HORZ_SKIP_UV(value) FIELD_PREP(GENMASK(1, 0), value)
87 #define AFBC_VERT_SKIP_UV(value) FIELD_PREP(GENMASK(3, 2), value)
88 #define AFBC_HORZ_SKIP_Y(value) FIELD_PREP(GENMASK(5, 4), value)
89 #define AFBC_VERT_SKIP_Y(value) FIELD_PREP(GENMASK(7, 6), value)
90 #define AFBC_COMPBITS_YUV(value) FIELD_PREP(GENMASK(13, 8), value)
91 #define AFBC_COMPBITS_8BIT 0
92 #define AFBC_COMPBITS_10BIT (2 | (2 << 2) | (2 << 4))
93 #define AFBC_BURST_LEN(value) FIELD_PREP(GENMASK(15, 14), value)
94 #define AFBC_HOLD_LINE_NUM(value) FIELD_PREP(GENMASK(22, 16), value)
95 #define AFBC_MIF_URGENT(value) FIELD_PREP(GENMASK(25, 24), value)
96 #define AFBC_REV_MODE(value) FIELD_PREP(GENMASK(27, 26), value)
97 #define AFBC_BLK_MEM_MODE BIT(28)
98 #define AFBC_SCATTER_MODE BIT(29)
99 #define AFBC_SOFT_RESET BIT(31)
100
101 /* AFBC_SIZE_IN */
102 #define AFBC_HSIZE_IN(value) FIELD_PREP(GENMASK(28, 16), value)
103 #define AFBC_VSIZE_IN(value) FIELD_PREP(GENMASK(12, 0), value)
104
105 /* AFBC_DEC_DEF_COLOR */
106 #define AFBC_DEF_COLOR_Y(value) FIELD_PREP(GENMASK(29, 20), value)
107 #define AFBC_DEF_COLOR_U(value) FIELD_PREP(GENMASK(19, 10), value)
108 #define AFBC_DEF_COLOR_V(value) FIELD_PREP(GENMASK(9, 0), value)
109
110 /* AFBC_CONV_CTRL */
111 #define AFBC_CONV_LBUF_LEN(value) FIELD_PREP(GENMASK(11, 0), value)
112
113 /* AFBC_LBUF_DEPTH */
114 #define AFBC_DEC_LBUF_DEPTH(value) FIELD_PREP(GENMASK(27, 16), value)
115 #define AFBC_MIF_LBUF_DEPTH(value) FIELD_PREP(GENMASK(11, 0), value)
116
117 /* AFBC_OUT_XSCOPE/AFBC_SIZE_OUT */
118 #define AFBC_HSIZE_OUT(value) FIELD_PREP(GENMASK(28, 16), value)
119 #define AFBC_VSIZE_OUT(value) FIELD_PREP(GENMASK(12, 0), value)
120 #define AFBC_OUT_HORZ_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
121 #define AFBC_OUT_HORZ_END(value) FIELD_PREP(GENMASK(12, 0), value)
122
123 /* AFBC_OUT_YSCOPE */
124 #define AFBC_OUT_VERT_BGN(value) FIELD_PREP(GENMASK(28, 16), value)
125 #define AFBC_OUT_VERT_END(value) FIELD_PREP(GENMASK(12, 0), value)
126
127 /* AFBC_VD_CFMT_CTRL */
128 #define AFBC_HORZ_RPT_PIXEL0 BIT(23)
129 #define AFBC_HORZ_Y_C_RATIO(value) FIELD_PREP(GENMASK(22, 21), value)
130 #define AFBC_HORZ_FMT_EN BIT(20)
131 #define AFBC_VERT_RPT_LINE0 BIT(16)
132 #define AFBC_VERT_INITIAL_PHASE(value) FIELD_PREP(GENMASK(11, 8), value)
133 #define AFBC_VERT_PHASE_STEP(value) FIELD_PREP(GENMASK(7, 1), value)
134 #define AFBC_VERT_FMT_EN BIT(0)
135
136 /* AFBC_VD_CFMT_W */
137 #define AFBC_VD_V_WIDTH(value) FIELD_PREP(GENMASK(11, 0), value)
138 #define AFBC_VD_H_WIDTH(value) FIELD_PREP(GENMASK(27, 16), value)
139
140 /* AFBC_MIF_HOR_SCOPE */
141 #define AFBC_MIF_BLK_BGN_H(value) FIELD_PREP(GENMASK(25, 16), value)
142 #define AFBC_MIF_BLK_END_H(value) FIELD_PREP(GENMASK(9, 0), value)
143
144 /* AFBC_MIF_VER_SCOPE */
145 #define AFBC_MIF_BLK_BGN_V(value) FIELD_PREP(GENMASK(27, 16), value)
146 #define AFBC_MIF_BLK_END_V(value) FIELD_PREP(GENMASK(11, 0), value)
147
148 /* AFBC_PIXEL_HOR_SCOPE */
149 #define AFBC_DEC_PIXEL_BGN_H(value) FIELD_PREP(GENMASK(28, 16), \
150 ((value) & GENMASK(12, 0)))
151 #define AFBC_DEC_PIXEL_END_H(value) FIELD_PREP(GENMASK(12, 0), value)
152
153 /* AFBC_PIXEL_VER_SCOPE */
154 #define AFBC_DEC_PIXEL_BGN_V(value) FIELD_PREP(GENMASK(28, 16), value)
155 #define AFBC_DEC_PIXEL_END_V(value) FIELD_PREP(GENMASK(12, 0), value)
156
157 /* AFBC_VD_CFMT_H */
158 #define AFBC_VD_HEIGHT(value) FIELD_PREP(GENMASK(12, 0), value)
159
160 struct meson_overlay {
161 struct drm_plane base;
162 struct meson_drm *priv;
163 };
164 #define to_meson_overlay(x) container_of(x, struct meson_overlay, base)
165
166 #define FRAC_16_16(mult, div) (((mult) << 16) / (div))
167
meson_overlay_atomic_check(struct drm_plane * plane,struct drm_atomic_state * state)168 static int meson_overlay_atomic_check(struct drm_plane *plane,
169 struct drm_atomic_state *state)
170 {
171 struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
172 plane);
173 struct drm_crtc_state *crtc_state;
174
175 if (!new_plane_state->crtc)
176 return 0;
177
178 crtc_state = drm_atomic_get_crtc_state(state,
179 new_plane_state->crtc);
180 if (IS_ERR(crtc_state))
181 return PTR_ERR(crtc_state);
182
183 return drm_atomic_helper_check_plane_state(new_plane_state,
184 crtc_state,
185 FRAC_16_16(1, 5),
186 FRAC_16_16(5, 1),
187 true, true);
188 }
189
190 /* Takes a fixed 16.16 number and converts it to integer. */
fixed16_to_int(int64_t value)191 static inline int64_t fixed16_to_int(int64_t value)
192 {
193 return value >> 16;
194 }
195
196 static const uint8_t skip_tab[6] = {
197 0x24, 0x04, 0x68, 0x48, 0x28, 0x08,
198 };
199
meson_overlay_get_vertical_phase(unsigned int ratio_y,int * phase,int * repeat,bool interlace)200 static void meson_overlay_get_vertical_phase(unsigned int ratio_y, int *phase,
201 int *repeat, bool interlace)
202 {
203 int offset_in = 0;
204 int offset_out = 0;
205 int repeat_skip = 0;
206
207 if (!interlace && ratio_y > (1 << 18))
208 offset_out = (1 * ratio_y) >> 10;
209
210 while ((offset_in + (4 << 8)) <= offset_out) {
211 repeat_skip++;
212 offset_in += 4 << 8;
213 }
214
215 *phase = (offset_out - offset_in) >> 2;
216
217 if (*phase > 0x100)
218 repeat_skip++;
219
220 *phase = *phase & 0xff;
221
222 if (repeat_skip > 5)
223 repeat_skip = 5;
224
225 *repeat = skip_tab[repeat_skip];
226 }
227
meson_overlay_setup_scaler_params(struct meson_drm * priv,struct drm_plane * plane,bool interlace_mode)228 static void meson_overlay_setup_scaler_params(struct meson_drm *priv,
229 struct drm_plane *plane,
230 bool interlace_mode)
231 {
232 struct drm_crtc_state *crtc_state = priv->crtc->state;
233 int video_top, video_left, video_width, video_height;
234 struct drm_plane_state *state = plane->state;
235 unsigned int vd_start_lines, vd_end_lines;
236 unsigned int hd_start_lines, hd_end_lines;
237 unsigned int crtc_height, crtc_width;
238 unsigned int vsc_startp, vsc_endp;
239 unsigned int hsc_startp, hsc_endp;
240 unsigned int crop_top, crop_left;
241 int vphase, vphase_repeat_skip;
242 unsigned int ratio_x, ratio_y;
243 int temp_height, temp_width;
244 unsigned int w_in, h_in;
245 int afbc_left, afbc_right;
246 int afbc_top_src, afbc_bottom_src;
247 int afbc_top, afbc_bottom;
248 int temp, start, end;
249
250 if (!crtc_state) {
251 DRM_ERROR("Invalid crtc_state\n");
252 return;
253 }
254
255 crtc_height = crtc_state->mode.vdisplay;
256 crtc_width = crtc_state->mode.hdisplay;
257
258 w_in = fixed16_to_int(state->src_w);
259 h_in = fixed16_to_int(state->src_h);
260 crop_top = fixed16_to_int(state->src_y);
261 crop_left = fixed16_to_int(state->src_x);
262
263 video_top = state->crtc_y;
264 video_left = state->crtc_x;
265 video_width = state->crtc_w;
266 video_height = state->crtc_h;
267
268 DRM_DEBUG("crtc_width %d crtc_height %d interlace %d\n",
269 crtc_width, crtc_height, interlace_mode);
270 DRM_DEBUG("w_in %d h_in %d crop_top %d crop_left %d\n",
271 w_in, h_in, crop_top, crop_left);
272 DRM_DEBUG("video top %d left %d width %d height %d\n",
273 video_top, video_left, video_width, video_height);
274
275 ratio_x = (w_in << 18) / video_width;
276 ratio_y = (h_in << 18) / video_height;
277
278 if (ratio_x * video_width < (w_in << 18))
279 ratio_x++;
280
281 DRM_DEBUG("ratio x 0x%x y 0x%x\n", ratio_x, ratio_y);
282
283 meson_overlay_get_vertical_phase(ratio_y, &vphase, &vphase_repeat_skip,
284 interlace_mode);
285
286 DRM_DEBUG("vphase 0x%x skip %d\n", vphase, vphase_repeat_skip);
287
288 /* Vertical */
289
290 start = video_top + video_height / 2 - ((h_in << 17) / ratio_y);
291 end = (h_in << 18) / ratio_y + start - 1;
292
293 if (video_top < 0 && start < 0)
294 vd_start_lines = (-(start) * ratio_y) >> 18;
295 else if (start < video_top)
296 vd_start_lines = ((video_top - start) * ratio_y) >> 18;
297 else
298 vd_start_lines = 0;
299
300 if (video_top < 0)
301 temp_height = min_t(unsigned int,
302 video_top + video_height - 1,
303 crtc_height - 1);
304 else
305 temp_height = min_t(unsigned int,
306 video_top + video_height - 1,
307 crtc_height - 1) - video_top + 1;
308
309 temp = vd_start_lines + (temp_height * ratio_y >> 18);
310 vd_end_lines = (temp <= (h_in - 1)) ? temp : (h_in - 1);
311
312 vd_start_lines += crop_left;
313 vd_end_lines += crop_left;
314
315 /*
316 * TOFIX: Input frames are handled and scaled like progressive frames,
317 * proper handling of interlaced field input frames need to be figured
318 * out using the proper framebuffer flags set by userspace.
319 */
320 if (interlace_mode) {
321 start >>= 1;
322 end >>= 1;
323 }
324
325 vsc_startp = max_t(int, start,
326 max_t(int, 0, video_top));
327 vsc_endp = min_t(int, end,
328 min_t(int, crtc_height - 1,
329 video_top + video_height - 1));
330
331 DRM_DEBUG("vsc startp %d endp %d start_lines %d end_lines %d\n",
332 vsc_startp, vsc_endp, vd_start_lines, vd_end_lines);
333
334 afbc_top = round_down(vd_start_lines, 4);
335 afbc_bottom = round_up(vd_end_lines + 1, 4);
336 afbc_top_src = 0;
337 afbc_bottom_src = round_up(h_in + 1, 4);
338
339 DRM_DEBUG("afbc top %d (src %d) bottom %d (src %d)\n",
340 afbc_top, afbc_top_src, afbc_bottom, afbc_bottom_src);
341
342 /* Horizontal */
343
344 start = video_left + video_width / 2 - ((w_in << 17) / ratio_x);
345 end = (w_in << 18) / ratio_x + start - 1;
346
347 if (video_left < 0 && start < 0)
348 hd_start_lines = (-(start) * ratio_x) >> 18;
349 else if (start < video_left)
350 hd_start_lines = ((video_left - start) * ratio_x) >> 18;
351 else
352 hd_start_lines = 0;
353
354 if (video_left < 0)
355 temp_width = min_t(unsigned int,
356 video_left + video_width - 1,
357 crtc_width - 1);
358 else
359 temp_width = min_t(unsigned int,
360 video_left + video_width - 1,
361 crtc_width - 1) - video_left + 1;
362
363 temp = hd_start_lines + (temp_width * ratio_x >> 18);
364 hd_end_lines = (temp <= (w_in - 1)) ? temp : (w_in - 1);
365
366 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
367 hsc_startp = max_t(int, start, max_t(int, 0, video_left));
368 hsc_endp = min_t(int, end, min_t(int, crtc_width - 1,
369 video_left + video_width - 1));
370
371 hd_start_lines += crop_top;
372 hd_end_lines += crop_top;
373
374 DRM_DEBUG("hsc startp %d endp %d start_lines %d end_lines %d\n",
375 hsc_startp, hsc_endp, hd_start_lines, hd_end_lines);
376
377 if (hd_start_lines > 0 || (hd_end_lines < w_in)) {
378 afbc_left = 0;
379 afbc_right = round_up(w_in, 32);
380 } else {
381 afbc_left = round_down(hd_start_lines, 32);
382 afbc_right = round_up(hd_end_lines + 1, 32);
383 }
384
385 DRM_DEBUG("afbc left %d right %d\n", afbc_left, afbc_right);
386
387 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
388
389 priv->viu.vpp_vsc_ini_phase = vphase << 8;
390 priv->viu.vpp_vsc_phase_ctrl = (1 << 13) | (4 << 8) |
391 vphase_repeat_skip;
392
393 priv->viu.vd1_if0_luma_x0 = VD_X_START(hd_start_lines) |
394 VD_X_END(hd_end_lines);
395 priv->viu.vd1_if0_chroma_x0 = VD_X_START(hd_start_lines >> 1) |
396 VD_X_END(hd_end_lines >> 1);
397
398 priv->viu.viu_vd1_fmt_w =
399 VD_H_WIDTH(hd_end_lines - hd_start_lines + 1) |
400 VD_V_WIDTH(hd_end_lines/2 - hd_start_lines/2 + 1);
401
402 priv->viu.vd1_afbc_vd_cfmt_w =
403 AFBC_VD_H_WIDTH(afbc_right - afbc_left) |
404 AFBC_VD_V_WIDTH(afbc_right / 2 - afbc_left / 2);
405
406 priv->viu.vd1_afbc_vd_cfmt_h =
407 AFBC_VD_HEIGHT((afbc_bottom - afbc_top) / 2);
408
409 priv->viu.vd1_afbc_mif_hor_scope = AFBC_MIF_BLK_BGN_H(afbc_left / 32) |
410 AFBC_MIF_BLK_END_H((afbc_right / 32) - 1);
411
412 priv->viu.vd1_afbc_mif_ver_scope = AFBC_MIF_BLK_BGN_V(afbc_top / 4) |
413 AFBC_MIF_BLK_END_H((afbc_bottom / 4) - 1);
414
415 priv->viu.vd1_afbc_size_out =
416 AFBC_HSIZE_OUT(afbc_right - afbc_left) |
417 AFBC_VSIZE_OUT(afbc_bottom - afbc_top);
418
419 priv->viu.vd1_afbc_pixel_hor_scope =
420 AFBC_DEC_PIXEL_BGN_H(hd_start_lines - afbc_left) |
421 AFBC_DEC_PIXEL_END_H(hd_end_lines - afbc_left);
422
423 priv->viu.vd1_afbc_pixel_ver_scope =
424 AFBC_DEC_PIXEL_BGN_V(vd_start_lines - afbc_top) |
425 AFBC_DEC_PIXEL_END_V(vd_end_lines - afbc_top);
426
427 priv->viu.vd1_afbc_size_in =
428 AFBC_HSIZE_IN(afbc_right - afbc_left) |
429 AFBC_VSIZE_IN(afbc_bottom_src - afbc_top_src);
430
431 priv->viu.vd1_if0_luma_y0 = VD_Y_START(vd_start_lines) |
432 VD_Y_END(vd_end_lines);
433
434 priv->viu.vd1_if0_chroma_y0 = VD_Y_START(vd_start_lines >> 1) |
435 VD_Y_END(vd_end_lines >> 1);
436
437 priv->viu.vpp_pic_in_height = h_in;
438
439 priv->viu.vpp_postblend_vd1_h_start_end = VD_H_START(hsc_startp) |
440 VD_H_END(hsc_endp);
441 priv->viu.vpp_blend_vd2_h_start_end = VD_H_START(hd_start_lines) |
442 VD_H_END(hd_end_lines);
443 priv->viu.vpp_hsc_region12_startp = VD_REGION13_END(0) |
444 VD_REGION24_START(hsc_startp);
445 priv->viu.vpp_hsc_region34_startp =
446 VD_REGION13_END(hsc_startp) |
447 VD_REGION24_START(hsc_endp - hsc_startp);
448 priv->viu.vpp_hsc_region4_endp = hsc_endp - hsc_startp;
449 priv->viu.vpp_hsc_start_phase_step = ratio_x << 6;
450 priv->viu.vpp_hsc_region1_phase_slope = 0;
451 priv->viu.vpp_hsc_region3_phase_slope = 0;
452 priv->viu.vpp_hsc_phase_ctrl = (1 << 21) | (4 << 16);
453
454 priv->viu.vpp_line_in_length = hd_end_lines - hd_start_lines + 1;
455 priv->viu.vpp_preblend_h_size = hd_end_lines - hd_start_lines + 1;
456
457 priv->viu.vpp_postblend_vd1_v_start_end = VD_V_START(vsc_startp) |
458 VD_V_END(vsc_endp);
459 priv->viu.vpp_blend_vd2_v_start_end =
460 VD2_V_START((vd_end_lines + 1) >> 1) |
461 VD2_V_END(vd_end_lines);
462
463 priv->viu.vpp_vsc_region12_startp = 0;
464 priv->viu.vpp_vsc_region34_startp =
465 VD_REGION13_END(vsc_endp - vsc_startp) |
466 VD_REGION24_START(vsc_endp - vsc_startp);
467 priv->viu.vpp_vsc_region4_endp = vsc_endp - vsc_startp;
468 priv->viu.vpp_vsc_start_phase_step = ratio_y << 6;
469 }
470
meson_overlay_atomic_update(struct drm_plane * plane,struct drm_atomic_state * state)471 static void meson_overlay_atomic_update(struct drm_plane *plane,
472 struct drm_atomic_state *state)
473 {
474 struct meson_overlay *meson_overlay = to_meson_overlay(plane);
475 struct drm_plane_state *new_state = drm_atomic_get_new_plane_state(state,
476 plane);
477 struct drm_framebuffer *fb = new_state->fb;
478 struct meson_drm *priv = meson_overlay->priv;
479 struct drm_gem_dma_object *gem;
480 unsigned long flags;
481 bool interlace_mode;
482
483 DRM_DEBUG_DRIVER("\n");
484
485 interlace_mode = new_state->crtc->mode.flags & DRM_MODE_FLAG_INTERLACE;
486
487 spin_lock_irqsave(&priv->drm->event_lock, flags);
488
489 if ((fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
490 DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
491 priv->viu.vd1_afbc = true;
492
493 priv->viu.vd1_afbc_mode = AFBC_MIF_URGENT(3) |
494 AFBC_HOLD_LINE_NUM(8) |
495 AFBC_BURST_LEN(2);
496
497 if (fb->modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0,
498 AMLOGIC_FBC_OPTION_MEM_SAVING))
499 priv->viu.vd1_afbc_mode |= AFBC_BLK_MEM_MODE;
500
501 if ((fb->modifier & __fourcc_mod_amlogic_layout_mask) ==
502 AMLOGIC_FBC_LAYOUT_SCATTER)
503 priv->viu.vd1_afbc_mode |= AFBC_SCATTER_MODE;
504
505 priv->viu.vd1_afbc_en = 0x1600 | AFBC_DEC_ENABLE;
506
507 priv->viu.vd1_afbc_conv_ctrl = AFBC_CONV_LBUF_LEN(256);
508
509 priv->viu.vd1_afbc_dec_def_color = AFBC_DEF_COLOR_Y(1023);
510
511 /* 420: horizontal / 2, vertical / 4 */
512 priv->viu.vd1_afbc_vd_cfmt_ctrl = AFBC_HORZ_RPT_PIXEL0 |
513 AFBC_HORZ_Y_C_RATIO(1) |
514 AFBC_HORZ_FMT_EN |
515 AFBC_VERT_RPT_LINE0 |
516 AFBC_VERT_INITIAL_PHASE(12) |
517 AFBC_VERT_PHASE_STEP(8) |
518 AFBC_VERT_FMT_EN;
519
520 switch (fb->format->format) {
521 /* AFBC Only formats */
522 case DRM_FORMAT_YUV420_10BIT:
523 priv->viu.vd1_afbc_mode |=
524 AFBC_COMPBITS_YUV(AFBC_COMPBITS_10BIT);
525 priv->viu.vd1_afbc_dec_def_color |=
526 AFBC_DEF_COLOR_U(512) |
527 AFBC_DEF_COLOR_V(512);
528 break;
529 case DRM_FORMAT_YUV420_8BIT:
530 priv->viu.vd1_afbc_dec_def_color |=
531 AFBC_DEF_COLOR_U(128) |
532 AFBC_DEF_COLOR_V(128);
533 break;
534 }
535
536 priv->viu.vd1_if0_gen_reg = 0;
537 priv->viu.vd1_if0_canvas0 = 0;
538 priv->viu.viu_vd1_fmt_ctrl = 0;
539 } else {
540 priv->viu.vd1_afbc = false;
541
542 priv->viu.vd1_if0_gen_reg = VD_URGENT_CHROMA |
543 VD_URGENT_LUMA |
544 VD_HOLD_LINES(9) |
545 VD_CHRO_RPT_LASTL_CTRL |
546 VD_ENABLE;
547 }
548
549 /* Setup scaler params */
550 meson_overlay_setup_scaler_params(priv, plane, interlace_mode);
551
552 priv->viu.vd1_if0_repeat_loop = 0;
553 priv->viu.vd1_if0_luma0_rpt_pat = interlace_mode ? 8 : 0;
554 priv->viu.vd1_if0_chroma0_rpt_pat = interlace_mode ? 8 : 0;
555 priv->viu.vd1_range_map_y = 0;
556 priv->viu.vd1_range_map_cb = 0;
557 priv->viu.vd1_range_map_cr = 0;
558
559 /* Default values for RGB888/YUV444 */
560 priv->viu.vd1_if0_gen_reg2 = 0;
561 priv->viu.viu_vd1_fmt_ctrl = 0;
562
563 /* None will match for AFBC Only formats */
564 switch (fb->format->format) {
565 /* TOFIX DRM_FORMAT_RGB888 should be supported */
566 case DRM_FORMAT_YUYV:
567 priv->viu.vd1_if0_gen_reg |= VD_BYTES_PER_PIXEL(1);
568 priv->viu.vd1_if0_canvas0 =
569 CANVAS_ADDR2(priv->canvas_id_vd1_0) |
570 CANVAS_ADDR1(priv->canvas_id_vd1_0) |
571 CANVAS_ADDR0(priv->canvas_id_vd1_0);
572 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
573 VD_HORZ_FMT_EN |
574 VD_VERT_RPT_LINE0 |
575 VD_VERT_INITIAL_PHASE(12) |
576 VD_VERT_PHASE_STEP(16) | /* /2 */
577 VD_VERT_FMT_EN;
578 break;
579 case DRM_FORMAT_NV12:
580 case DRM_FORMAT_NV21:
581 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
582 priv->viu.vd1_if0_canvas0 =
583 CANVAS_ADDR2(priv->canvas_id_vd1_1) |
584 CANVAS_ADDR1(priv->canvas_id_vd1_1) |
585 CANVAS_ADDR0(priv->canvas_id_vd1_0);
586 if (fb->format->format == DRM_FORMAT_NV12)
587 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(1);
588 else
589 priv->viu.vd1_if0_gen_reg2 = VD_COLOR_MAP(2);
590 priv->viu.viu_vd1_fmt_ctrl = VD_HORZ_Y_C_RATIO(1) | /* /2 */
591 VD_HORZ_FMT_EN |
592 VD_VERT_RPT_LINE0 |
593 VD_VERT_INITIAL_PHASE(12) |
594 VD_VERT_PHASE_STEP(8) | /* /4 */
595 VD_VERT_FMT_EN;
596 break;
597 case DRM_FORMAT_YUV444:
598 case DRM_FORMAT_YUV422:
599 case DRM_FORMAT_YUV420:
600 case DRM_FORMAT_YUV411:
601 case DRM_FORMAT_YUV410:
602 priv->viu.vd1_if0_gen_reg |= VD_SEPARATE_EN;
603 priv->viu.vd1_if0_canvas0 =
604 CANVAS_ADDR2(priv->canvas_id_vd1_2) |
605 CANVAS_ADDR1(priv->canvas_id_vd1_1) |
606 CANVAS_ADDR0(priv->canvas_id_vd1_0);
607 switch (fb->format->format) {
608 case DRM_FORMAT_YUV422:
609 priv->viu.viu_vd1_fmt_ctrl =
610 VD_HORZ_Y_C_RATIO(1) | /* /2 */
611 VD_HORZ_FMT_EN |
612 VD_VERT_RPT_LINE0 |
613 VD_VERT_INITIAL_PHASE(12) |
614 VD_VERT_PHASE_STEP(16) | /* /2 */
615 VD_VERT_FMT_EN;
616 break;
617 case DRM_FORMAT_YUV420:
618 priv->viu.viu_vd1_fmt_ctrl =
619 VD_HORZ_Y_C_RATIO(1) | /* /2 */
620 VD_HORZ_FMT_EN |
621 VD_VERT_RPT_LINE0 |
622 VD_VERT_INITIAL_PHASE(12) |
623 VD_VERT_PHASE_STEP(8) | /* /4 */
624 VD_VERT_FMT_EN;
625 break;
626 case DRM_FORMAT_YUV411:
627 priv->viu.viu_vd1_fmt_ctrl =
628 VD_HORZ_Y_C_RATIO(2) | /* /4 */
629 VD_HORZ_FMT_EN |
630 VD_VERT_RPT_LINE0 |
631 VD_VERT_INITIAL_PHASE(12) |
632 VD_VERT_PHASE_STEP(16) | /* /2 */
633 VD_VERT_FMT_EN;
634 break;
635 case DRM_FORMAT_YUV410:
636 priv->viu.viu_vd1_fmt_ctrl =
637 VD_HORZ_Y_C_RATIO(2) | /* /4 */
638 VD_HORZ_FMT_EN |
639 VD_VERT_RPT_LINE0 |
640 VD_VERT_INITIAL_PHASE(12) |
641 VD_VERT_PHASE_STEP(8) | /* /4 */
642 VD_VERT_FMT_EN;
643 break;
644 }
645 break;
646 }
647
648 /* Update Canvas with buffer address */
649 priv->viu.vd1_planes = fb->format->num_planes;
650
651 switch (priv->viu.vd1_planes) {
652 case 3:
653 gem = drm_fb_dma_get_gem_obj(fb, 2);
654 priv->viu.vd1_addr2 = gem->dma_addr + fb->offsets[2];
655 priv->viu.vd1_stride2 = fb->pitches[2];
656 priv->viu.vd1_height2 =
657 drm_format_info_plane_height(fb->format,
658 fb->height, 2);
659 DRM_DEBUG("plane 2 addr 0x%x stride %d height %d\n",
660 priv->viu.vd1_addr2,
661 priv->viu.vd1_stride2,
662 priv->viu.vd1_height2);
663 fallthrough;
664 case 2:
665 gem = drm_fb_dma_get_gem_obj(fb, 1);
666 priv->viu.vd1_addr1 = gem->dma_addr + fb->offsets[1];
667 priv->viu.vd1_stride1 = fb->pitches[1];
668 priv->viu.vd1_height1 =
669 drm_format_info_plane_height(fb->format,
670 fb->height, 1);
671 DRM_DEBUG("plane 1 addr 0x%x stride %d height %d\n",
672 priv->viu.vd1_addr1,
673 priv->viu.vd1_stride1,
674 priv->viu.vd1_height1);
675 fallthrough;
676 case 1:
677 gem = drm_fb_dma_get_gem_obj(fb, 0);
678 priv->viu.vd1_addr0 = gem->dma_addr + fb->offsets[0];
679 priv->viu.vd1_stride0 = fb->pitches[0];
680 priv->viu.vd1_height0 =
681 drm_format_info_plane_height(fb->format,
682 fb->height, 0);
683 DRM_DEBUG("plane 0 addr 0x%x stride %d height %d\n",
684 priv->viu.vd1_addr0,
685 priv->viu.vd1_stride0,
686 priv->viu.vd1_height0);
687 }
688
689 if (priv->viu.vd1_afbc) {
690 if (priv->viu.vd1_afbc_mode & AFBC_SCATTER_MODE) {
691 /*
692 * In Scatter mode, the header contains the physical
693 * body content layout, thus the body content
694 * size isn't needed.
695 */
696 priv->viu.vd1_afbc_head_addr = priv->viu.vd1_addr0 >> 4;
697 priv->viu.vd1_afbc_body_addr = 0;
698 } else {
699 /* Default mode is 4k per superblock */
700 unsigned long block_size = 4096;
701 unsigned long body_size;
702
703 /* 8bit mem saving mode is 3072bytes per superblock */
704 if (priv->viu.vd1_afbc_mode & AFBC_BLK_MEM_MODE)
705 block_size = 3072;
706
707 body_size = (ALIGN(priv->viu.vd1_stride0, 64) / 64) *
708 (ALIGN(priv->viu.vd1_height0, 32) / 32) *
709 block_size;
710
711 priv->viu.vd1_afbc_body_addr = priv->viu.vd1_addr0 >> 4;
712 /* Header is after body content */
713 priv->viu.vd1_afbc_head_addr = (priv->viu.vd1_addr0 +
714 body_size) >> 4;
715 }
716 }
717
718 priv->viu.vd1_enabled = true;
719
720 spin_unlock_irqrestore(&priv->drm->event_lock, flags);
721
722 DRM_DEBUG_DRIVER("\n");
723 }
724
meson_overlay_atomic_disable(struct drm_plane * plane,struct drm_atomic_state * state)725 static void meson_overlay_atomic_disable(struct drm_plane *plane,
726 struct drm_atomic_state *state)
727 {
728 struct meson_overlay *meson_overlay = to_meson_overlay(plane);
729 struct meson_drm *priv = meson_overlay->priv;
730
731 DRM_DEBUG_DRIVER("\n");
732
733 priv->viu.vd1_enabled = false;
734
735 /* Disable VD1 */
736 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) {
737 writel_relaxed(0, priv->io_base + _REG(VD1_BLEND_SRC_CTRL));
738 writel_relaxed(0, priv->io_base + _REG(VD2_BLEND_SRC_CTRL));
739 writel_relaxed(0, priv->io_base + _REG(VD1_IF0_GEN_REG + 0x17b0));
740 writel_relaxed(0, priv->io_base + _REG(VD2_IF0_GEN_REG + 0x17b0));
741 } else
742 writel_bits_relaxed(VPP_VD1_POSTBLEND | VPP_VD1_PREBLEND, 0,
743 priv->io_base + _REG(VPP_MISC));
744
745 }
746
747 static const struct drm_plane_helper_funcs meson_overlay_helper_funcs = {
748 .atomic_check = meson_overlay_atomic_check,
749 .atomic_disable = meson_overlay_atomic_disable,
750 .atomic_update = meson_overlay_atomic_update,
751 };
752
meson_overlay_format_mod_supported(struct drm_plane * plane,u32 format,u64 modifier)753 static bool meson_overlay_format_mod_supported(struct drm_plane *plane,
754 u32 format, u64 modifier)
755 {
756 if (modifier == DRM_FORMAT_MOD_LINEAR &&
757 format != DRM_FORMAT_YUV420_8BIT &&
758 format != DRM_FORMAT_YUV420_10BIT)
759 return true;
760
761 if ((modifier & DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) ==
762 DRM_FORMAT_MOD_AMLOGIC_FBC(0, 0)) {
763 unsigned int layout = modifier &
764 DRM_FORMAT_MOD_AMLOGIC_FBC(
765 __fourcc_mod_amlogic_layout_mask, 0);
766 unsigned int options =
767 (modifier >> __fourcc_mod_amlogic_options_shift) &
768 __fourcc_mod_amlogic_options_mask;
769
770 if (format != DRM_FORMAT_YUV420_8BIT &&
771 format != DRM_FORMAT_YUV420_10BIT) {
772 DRM_DEBUG_KMS("%llx invalid format 0x%08x\n",
773 modifier, format);
774 return false;
775 }
776
777 if (layout != AMLOGIC_FBC_LAYOUT_BASIC &&
778 layout != AMLOGIC_FBC_LAYOUT_SCATTER) {
779 DRM_DEBUG_KMS("%llx invalid layout %x\n",
780 modifier, layout);
781 return false;
782 }
783
784 if (options &&
785 options != AMLOGIC_FBC_OPTION_MEM_SAVING) {
786 DRM_DEBUG_KMS("%llx invalid layout %x\n",
787 modifier, layout);
788 return false;
789 }
790
791 return true;
792 }
793
794 DRM_DEBUG_KMS("invalid modifier %llx for format 0x%08x\n",
795 modifier, format);
796
797 return false;
798 }
799
800 static const struct drm_plane_funcs meson_overlay_funcs = {
801 .update_plane = drm_atomic_helper_update_plane,
802 .disable_plane = drm_atomic_helper_disable_plane,
803 .destroy = drm_plane_cleanup,
804 .reset = drm_atomic_helper_plane_reset,
805 .atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
806 .atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
807 .format_mod_supported = meson_overlay_format_mod_supported,
808 };
809
810 static const uint32_t supported_drm_formats[] = {
811 DRM_FORMAT_YUYV,
812 DRM_FORMAT_NV12,
813 DRM_FORMAT_NV21,
814 DRM_FORMAT_YUV444,
815 DRM_FORMAT_YUV422,
816 DRM_FORMAT_YUV420,
817 DRM_FORMAT_YUV411,
818 DRM_FORMAT_YUV410,
819 DRM_FORMAT_YUV420_8BIT, /* Amlogic FBC Only */
820 DRM_FORMAT_YUV420_10BIT, /* Amlogic FBC Only */
821 };
822
823 static const uint64_t format_modifiers[] = {
824 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER,
825 AMLOGIC_FBC_OPTION_MEM_SAVING),
826 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC,
827 AMLOGIC_FBC_OPTION_MEM_SAVING),
828 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_SCATTER, 0),
829 DRM_FORMAT_MOD_AMLOGIC_FBC(AMLOGIC_FBC_LAYOUT_BASIC, 0),
830 DRM_FORMAT_MOD_LINEAR,
831 DRM_FORMAT_MOD_INVALID,
832 };
833
meson_overlay_create(struct meson_drm * priv)834 int meson_overlay_create(struct meson_drm *priv)
835 {
836 struct meson_overlay *meson_overlay;
837 struct drm_plane *plane;
838
839 DRM_DEBUG_DRIVER("\n");
840
841 meson_overlay = devm_kzalloc(priv->drm->dev, sizeof(*meson_overlay),
842 GFP_KERNEL);
843 if (!meson_overlay)
844 return -ENOMEM;
845
846 meson_overlay->priv = priv;
847 plane = &meson_overlay->base;
848
849 drm_universal_plane_init(priv->drm, plane, 0xFF,
850 &meson_overlay_funcs,
851 supported_drm_formats,
852 ARRAY_SIZE(supported_drm_formats),
853 format_modifiers,
854 DRM_PLANE_TYPE_OVERLAY, "meson_overlay_plane");
855
856 drm_plane_helper_add(plane, &meson_overlay_helper_funcs);
857
858 /* For now, VD Overlay plane is always on the back */
859 drm_plane_create_zpos_immutable_property(plane, 0);
860
861 priv->overlay_plane = plane;
862
863 DRM_DEBUG_DRIVER("\n");
864
865 return 0;
866 }
867