1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * Written by: 8 * Jasper St. Pierre <jstpierre@mecheye.net> 9 */ 10 11 #include <linux/aperture.h> 12 #include <linux/component.h> 13 #include <linux/module.h> 14 #include <linux/of_graph.h> 15 #include <linux/sys_soc.h> 16 #include <linux/platform_device.h> 17 #include <linux/soc/amlogic/meson-canvas.h> 18 19 #include <drm/clients/drm_client_setup.h> 20 #include <drm/drm_atomic_helper.h> 21 #include <drm/drm_drv.h> 22 #include <drm/drm_fbdev_dma.h> 23 #include <drm/drm_gem_dma_helper.h> 24 #include <drm/drm_gem_framebuffer_helper.h> 25 #include <drm/drm_modeset_helper_vtables.h> 26 #include <drm/drm_module.h> 27 #include <drm/drm_probe_helper.h> 28 #include <drm/drm_vblank.h> 29 30 #include "meson_crtc.h" 31 #include "meson_drv.h" 32 #include "meson_overlay.h" 33 #include "meson_plane.h" 34 #include "meson_osd_afbcd.h" 35 #include "meson_registers.h" 36 #include "meson_encoder_cvbs.h" 37 #include "meson_encoder_hdmi.h" 38 #include "meson_encoder_dsi.h" 39 #include "meson_viu.h" 40 #include "meson_vpp.h" 41 #include "meson_rdma.h" 42 43 #define DRIVER_NAME "meson" 44 #define DRIVER_DESC "Amlogic Meson DRM driver" 45 46 /** 47 * DOC: Video Processing Unit 48 * 49 * VPU Handles the Global Video Processing, it includes management of the 50 * clocks gates, blocks reset lines and power domains. 51 * 52 * What is missing : 53 * 54 * - Full reset of entire video processing HW blocks 55 * - Scaling and setup of the VPU clock 56 * - Bus clock gates 57 * - Powering up video processing HW blocks 58 * - Powering Up HDMI controller and PHY 59 */ 60 61 static const struct drm_mode_config_funcs meson_mode_config_funcs = { 62 .atomic_check = drm_atomic_helper_check, 63 .atomic_commit = drm_atomic_helper_commit, 64 .fb_create = drm_gem_fb_create, 65 }; 66 67 static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = { 68 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 69 }; 70 71 static irqreturn_t meson_irq(int irq, void *arg) 72 { 73 struct drm_device *dev = arg; 74 struct meson_drm *priv = dev->dev_private; 75 76 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); 77 78 meson_crtc_irq(priv); 79 80 return IRQ_HANDLED; 81 } 82 83 static int meson_dumb_create(struct drm_file *file, struct drm_device *dev, 84 struct drm_mode_create_dumb *args) 85 { 86 /* 87 * We need 64bytes aligned stride, and PAGE aligned size 88 */ 89 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64); 90 args->size = PAGE_ALIGN(args->pitch * args->height); 91 92 return drm_gem_dma_dumb_create_internal(file, dev, args); 93 } 94 95 DEFINE_DRM_GEM_DMA_FOPS(fops); 96 97 static const struct drm_driver meson_driver = { 98 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 99 100 /* DMA Ops */ 101 DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create), 102 DRM_FBDEV_DMA_DRIVER_OPS, 103 104 /* Misc */ 105 .fops = &fops, 106 .name = DRIVER_NAME, 107 .desc = DRIVER_DESC, 108 .major = 1, 109 .minor = 0, 110 }; 111 112 static bool meson_vpu_has_available_connectors(struct device *dev) 113 { 114 struct device_node *ep, *remote; 115 116 /* Parses each endpoint and check if remote exists */ 117 for_each_endpoint_of_node(dev->of_node, ep) { 118 /* If the endpoint node exists, consider it enabled */ 119 remote = of_graph_get_remote_port(ep); 120 if (remote) { 121 of_node_put(remote); 122 of_node_put(ep); 123 return true; 124 } 125 } 126 127 return false; 128 } 129 130 static const struct regmap_config meson_regmap_config = { 131 .reg_bits = 32, 132 .val_bits = 32, 133 .reg_stride = 4, 134 .max_register = 0x1000, 135 }; 136 137 static void meson_vpu_init(struct meson_drm *priv) 138 { 139 u32 value; 140 141 /* 142 * Slave dc0 and dc5 connected to master port 1. 143 * By default other slaves are connected to master port 0. 144 */ 145 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | 146 VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); 147 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); 148 149 /* Slave dc0 connected to master port 1 */ 150 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); 151 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); 152 153 /* Slave dc4 and dc7 connected to master port 1 */ 154 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | 155 VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); 156 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); 157 158 /* Slave dc1 connected to master port 1 */ 159 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); 160 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); 161 } 162 163 struct meson_drm_soc_attr { 164 struct meson_drm_soc_limits limits; 165 const struct soc_device_attribute *attrs; 166 }; 167 168 static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { 169 /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ 170 { 171 .limits = { 172 .max_hdmi_phy_freq = 1650000, 173 }, 174 .attrs = (const struct soc_device_attribute []) { 175 { .soc_id = "GXL (S805*)", }, 176 { /* sentinel */ } 177 } 178 }, 179 }; 180 181 static int meson_drv_bind_master(struct device *dev, bool has_components) 182 { 183 struct platform_device *pdev = to_platform_device(dev); 184 const struct meson_drm_match_data *match; 185 struct meson_drm *priv; 186 struct drm_device *drm; 187 struct resource *res; 188 void __iomem *regs; 189 int ret, i; 190 191 /* Checks if an output connector is available */ 192 if (!meson_vpu_has_available_connectors(dev)) { 193 dev_err(dev, "No output connector available\n"); 194 return -ENODEV; 195 } 196 197 match = of_device_get_match_data(dev); 198 if (!match) 199 return -ENODEV; 200 201 drm = drm_dev_alloc(&meson_driver, dev); 202 if (IS_ERR(drm)) 203 return PTR_ERR(drm); 204 205 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 206 if (!priv) { 207 ret = -ENOMEM; 208 goto free_drm; 209 } 210 drm->dev_private = priv; 211 priv->drm = drm; 212 priv->dev = dev; 213 priv->compat = match->compat; 214 priv->afbcd.ops = match->afbcd_ops; 215 216 regs = devm_platform_ioremap_resource_byname(pdev, "vpu"); 217 if (IS_ERR(regs)) { 218 ret = PTR_ERR(regs); 219 goto free_drm; 220 } 221 222 priv->io_base = regs; 223 224 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); 225 if (!res) { 226 ret = -EINVAL; 227 goto free_drm; 228 } 229 /* Simply ioremap since it may be a shared register zone */ 230 regs = devm_ioremap(dev, res->start, resource_size(res)); 231 if (!regs) { 232 ret = -EADDRNOTAVAIL; 233 goto free_drm; 234 } 235 236 priv->hhi = devm_regmap_init_mmio(dev, regs, 237 &meson_regmap_config); 238 if (IS_ERR(priv->hhi)) { 239 dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); 240 ret = PTR_ERR(priv->hhi); 241 goto free_drm; 242 } 243 244 priv->canvas = meson_canvas_get(dev); 245 if (IS_ERR(priv->canvas)) { 246 ret = PTR_ERR(priv->canvas); 247 goto free_drm; 248 } 249 250 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); 251 if (ret) 252 goto free_drm; 253 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); 254 if (ret) 255 goto free_canvas_osd1; 256 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); 257 if (ret) 258 goto free_canvas_vd1_0; 259 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); 260 if (ret) 261 goto free_canvas_vd1_1; 262 263 priv->vsync_irq = platform_get_irq(pdev, 0); 264 265 ret = drm_vblank_init(drm, 1); 266 if (ret) 267 goto free_canvas_vd1_2; 268 269 /* Assign limits per soc revision/package */ 270 for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) { 271 if (soc_device_match(meson_drm_soc_attrs[i].attrs)) { 272 priv->limits = &meson_drm_soc_attrs[i].limits; 273 break; 274 } 275 } 276 277 /* 278 * Remove early framebuffers (ie. simplefb). The framebuffer can be 279 * located anywhere in RAM 280 */ 281 ret = aperture_remove_all_conflicting_devices(meson_driver.name); 282 if (ret) 283 goto free_canvas_vd1_2; 284 285 ret = drmm_mode_config_init(drm); 286 if (ret) 287 goto free_canvas_vd1_2; 288 drm->mode_config.max_width = 3840; 289 drm->mode_config.max_height = 2160; 290 drm->mode_config.funcs = &meson_mode_config_funcs; 291 drm->mode_config.helper_private = &meson_mode_config_helpers; 292 293 /* Hardware Initialization */ 294 295 meson_vpu_init(priv); 296 meson_venc_init(priv); 297 meson_vpp_init(priv); 298 meson_viu_init(priv); 299 if (priv->afbcd.ops) { 300 ret = priv->afbcd.ops->init(priv); 301 if (ret) 302 goto free_canvas_vd1_2; 303 } 304 305 /* Encoder Initialization */ 306 307 ret = meson_encoder_cvbs_probe(priv); 308 if (ret) 309 goto exit_afbcd; 310 311 if (has_components) { 312 ret = component_bind_all(dev, drm); 313 if (ret) { 314 dev_err(drm->dev, "Couldn't bind all components\n"); 315 /* Do not try to unbind */ 316 has_components = false; 317 goto exit_afbcd; 318 } 319 } 320 321 ret = meson_encoder_hdmi_probe(priv); 322 if (ret) 323 goto exit_afbcd; 324 325 if (meson_vpu_is_compatible(priv, VPU_COMPATIBLE_G12A)) { 326 ret = meson_encoder_dsi_probe(priv); 327 if (ret) 328 goto exit_afbcd; 329 } 330 331 ret = meson_plane_create(priv); 332 if (ret) 333 goto exit_afbcd; 334 335 ret = meson_overlay_create(priv); 336 if (ret) 337 goto exit_afbcd; 338 339 ret = meson_crtc_create(priv); 340 if (ret) 341 goto exit_afbcd; 342 343 ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm); 344 if (ret) 345 goto exit_afbcd; 346 347 drm_mode_config_reset(drm); 348 349 drm_kms_helper_poll_init(drm); 350 351 platform_set_drvdata(pdev, priv); 352 353 ret = drm_dev_register(drm, 0); 354 if (ret) 355 goto uninstall_irq; 356 357 drm_client_setup(drm, NULL); 358 359 return 0; 360 361 uninstall_irq: 362 free_irq(priv->vsync_irq, drm); 363 exit_afbcd: 364 if (priv->afbcd.ops) 365 priv->afbcd.ops->exit(priv); 366 free_canvas_vd1_2: 367 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2); 368 free_canvas_vd1_1: 369 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); 370 free_canvas_vd1_0: 371 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); 372 free_canvas_osd1: 373 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 374 free_drm: 375 drm_dev_put(drm); 376 377 meson_encoder_dsi_remove(priv); 378 meson_encoder_hdmi_remove(priv); 379 meson_encoder_cvbs_remove(priv); 380 381 if (has_components) 382 component_unbind_all(dev, drm); 383 384 return ret; 385 } 386 387 static int meson_drv_bind(struct device *dev) 388 { 389 return meson_drv_bind_master(dev, true); 390 } 391 392 static void meson_drv_unbind(struct device *dev) 393 { 394 struct meson_drm *priv = dev_get_drvdata(dev); 395 struct drm_device *drm = priv->drm; 396 397 if (priv->canvas) { 398 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 399 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); 400 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); 401 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2); 402 } 403 404 drm_dev_unregister(drm); 405 drm_kms_helper_poll_fini(drm); 406 drm_atomic_helper_shutdown(drm); 407 free_irq(priv->vsync_irq, drm); 408 drm_dev_put(drm); 409 410 meson_encoder_dsi_remove(priv); 411 meson_encoder_hdmi_remove(priv); 412 meson_encoder_cvbs_remove(priv); 413 414 component_unbind_all(dev, drm); 415 416 if (priv->afbcd.ops) 417 priv->afbcd.ops->exit(priv); 418 } 419 420 static const struct component_master_ops meson_drv_master_ops = { 421 .bind = meson_drv_bind, 422 .unbind = meson_drv_unbind, 423 }; 424 425 static int __maybe_unused meson_drv_pm_suspend(struct device *dev) 426 { 427 struct meson_drm *priv = dev_get_drvdata(dev); 428 429 if (!priv) 430 return 0; 431 432 return drm_mode_config_helper_suspend(priv->drm); 433 } 434 435 static int __maybe_unused meson_drv_pm_resume(struct device *dev) 436 { 437 struct meson_drm *priv = dev_get_drvdata(dev); 438 439 if (!priv) 440 return 0; 441 442 meson_vpu_init(priv); 443 meson_venc_init(priv); 444 meson_vpp_init(priv); 445 meson_viu_init(priv); 446 if (priv->afbcd.ops) 447 priv->afbcd.ops->init(priv); 448 449 return drm_mode_config_helper_resume(priv->drm); 450 } 451 452 static void meson_drv_shutdown(struct platform_device *pdev) 453 { 454 struct meson_drm *priv = dev_get_drvdata(&pdev->dev); 455 456 if (!priv) 457 return; 458 459 drm_kms_helper_poll_fini(priv->drm); 460 drm_atomic_helper_shutdown(priv->drm); 461 } 462 463 /* 464 * Only devices to use as components 465 * TOFIX: get rid of components when we can finally 466 * get meson_dx_hdmi to stop using the meson_drm 467 * private structure for HHI registers. 468 */ 469 static const struct of_device_id components_dev_match[] = { 470 { .compatible = "amlogic,meson-gxbb-dw-hdmi" }, 471 { .compatible = "amlogic,meson-gxl-dw-hdmi" }, 472 { .compatible = "amlogic,meson-gxm-dw-hdmi" }, 473 { .compatible = "amlogic,meson-g12a-dw-hdmi" }, 474 {} 475 }; 476 477 static int meson_drv_probe(struct platform_device *pdev) 478 { 479 struct component_match *match = NULL; 480 struct device_node *np = pdev->dev.of_node; 481 struct device_node *ep, *remote; 482 int count = 0; 483 484 for_each_endpoint_of_node(np, ep) { 485 remote = of_graph_get_remote_port_parent(ep); 486 if (!remote || !of_device_is_available(remote)) { 487 of_node_put(remote); 488 continue; 489 } 490 491 if (of_match_node(components_dev_match, remote)) { 492 component_match_add(&pdev->dev, &match, component_compare_of, remote); 493 494 dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n", 495 np, remote, dev_name(&pdev->dev)); 496 } 497 498 of_node_put(remote); 499 500 ++count; 501 } 502 503 if (count && !match) 504 return meson_drv_bind_master(&pdev->dev, false); 505 506 /* If some endpoints were found, initialize the nodes */ 507 if (count) { 508 dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count); 509 510 return component_master_add_with_match(&pdev->dev, 511 &meson_drv_master_ops, 512 match); 513 } 514 515 /* If no output endpoints were available, simply bail out */ 516 return 0; 517 }; 518 519 static void meson_drv_remove(struct platform_device *pdev) 520 { 521 component_master_del(&pdev->dev, &meson_drv_master_ops); 522 } 523 524 static struct meson_drm_match_data meson_drm_gxbb_data = { 525 .compat = VPU_COMPATIBLE_GXBB, 526 }; 527 528 static struct meson_drm_match_data meson_drm_gxl_data = { 529 .compat = VPU_COMPATIBLE_GXL, 530 }; 531 532 static struct meson_drm_match_data meson_drm_gxm_data = { 533 .compat = VPU_COMPATIBLE_GXM, 534 .afbcd_ops = &meson_afbcd_gxm_ops, 535 }; 536 537 static struct meson_drm_match_data meson_drm_g12a_data = { 538 .compat = VPU_COMPATIBLE_G12A, 539 .afbcd_ops = &meson_afbcd_g12a_ops, 540 }; 541 542 static const struct of_device_id dt_match[] = { 543 { .compatible = "amlogic,meson-gxbb-vpu", 544 .data = (void *)&meson_drm_gxbb_data }, 545 { .compatible = "amlogic,meson-gxl-vpu", 546 .data = (void *)&meson_drm_gxl_data }, 547 { .compatible = "amlogic,meson-gxm-vpu", 548 .data = (void *)&meson_drm_gxm_data }, 549 { .compatible = "amlogic,meson-g12a-vpu", 550 .data = (void *)&meson_drm_g12a_data }, 551 {} 552 }; 553 MODULE_DEVICE_TABLE(of, dt_match); 554 555 static const struct dev_pm_ops meson_drv_pm_ops = { 556 SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume) 557 }; 558 559 static struct platform_driver meson_drm_platform_driver = { 560 .probe = meson_drv_probe, 561 .remove = meson_drv_remove, 562 .shutdown = meson_drv_shutdown, 563 .driver = { 564 .name = "meson-drm", 565 .of_match_table = dt_match, 566 .pm = &meson_drv_pm_ops, 567 }, 568 }; 569 570 drm_module_platform_driver(meson_drm_platform_driver); 571 572 MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>"); 573 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 574 MODULE_DESCRIPTION(DRIVER_DESC); 575 MODULE_LICENSE("GPL"); 576