1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Copyright (C) 2016 BayLibre, SAS 4 * Author: Neil Armstrong <narmstrong@baylibre.com> 5 * Copyright (C) 2014 Endless Mobile 6 * 7 * Written by: 8 * Jasper St. Pierre <jstpierre@mecheye.net> 9 */ 10 11 #include <linux/component.h> 12 #include <linux/module.h> 13 #include <linux/of_graph.h> 14 #include <linux/sys_soc.h> 15 #include <linux/platform_device.h> 16 #include <linux/soc/amlogic/meson-canvas.h> 17 18 #include <drm/drm_aperture.h> 19 #include <drm/drm_atomic_helper.h> 20 #include <drm/drm_drv.h> 21 #include <drm/drm_fbdev_dma.h> 22 #include <drm/drm_gem_dma_helper.h> 23 #include <drm/drm_gem_framebuffer_helper.h> 24 #include <drm/drm_modeset_helper_vtables.h> 25 #include <drm/drm_module.h> 26 #include <drm/drm_probe_helper.h> 27 #include <drm/drm_vblank.h> 28 29 #include "meson_crtc.h" 30 #include "meson_drv.h" 31 #include "meson_overlay.h" 32 #include "meson_plane.h" 33 #include "meson_osd_afbcd.h" 34 #include "meson_registers.h" 35 #include "meson_encoder_cvbs.h" 36 #include "meson_encoder_hdmi.h" 37 #include "meson_viu.h" 38 #include "meson_vpp.h" 39 #include "meson_rdma.h" 40 41 #define DRIVER_NAME "meson" 42 #define DRIVER_DESC "Amlogic Meson DRM driver" 43 44 /** 45 * DOC: Video Processing Unit 46 * 47 * VPU Handles the Global Video Processing, it includes management of the 48 * clocks gates, blocks reset lines and power domains. 49 * 50 * What is missing : 51 * 52 * - Full reset of entire video processing HW blocks 53 * - Scaling and setup of the VPU clock 54 * - Bus clock gates 55 * - Powering up video processing HW blocks 56 * - Powering Up HDMI controller and PHY 57 */ 58 59 static const struct drm_mode_config_funcs meson_mode_config_funcs = { 60 .atomic_check = drm_atomic_helper_check, 61 .atomic_commit = drm_atomic_helper_commit, 62 .fb_create = drm_gem_fb_create, 63 }; 64 65 static const struct drm_mode_config_helper_funcs meson_mode_config_helpers = { 66 .atomic_commit_tail = drm_atomic_helper_commit_tail_rpm, 67 }; 68 69 static irqreturn_t meson_irq(int irq, void *arg) 70 { 71 struct drm_device *dev = arg; 72 struct meson_drm *priv = dev->dev_private; 73 74 (void)readl_relaxed(priv->io_base + _REG(VENC_INTFLAG)); 75 76 meson_crtc_irq(priv); 77 78 return IRQ_HANDLED; 79 } 80 81 static int meson_dumb_create(struct drm_file *file, struct drm_device *dev, 82 struct drm_mode_create_dumb *args) 83 { 84 /* 85 * We need 64bytes aligned stride, and PAGE aligned size 86 */ 87 args->pitch = ALIGN(DIV_ROUND_UP(args->width * args->bpp, 8), SZ_64); 88 args->size = PAGE_ALIGN(args->pitch * args->height); 89 90 return drm_gem_dma_dumb_create_internal(file, dev, args); 91 } 92 93 DEFINE_DRM_GEM_DMA_FOPS(fops); 94 95 static const struct drm_driver meson_driver = { 96 .driver_features = DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC, 97 98 /* DMA Ops */ 99 DRM_GEM_DMA_DRIVER_OPS_WITH_DUMB_CREATE(meson_dumb_create), 100 101 /* Misc */ 102 .fops = &fops, 103 .name = DRIVER_NAME, 104 .desc = DRIVER_DESC, 105 .date = "20161109", 106 .major = 1, 107 .minor = 0, 108 }; 109 110 static bool meson_vpu_has_available_connectors(struct device *dev) 111 { 112 struct device_node *ep, *remote; 113 114 /* Parses each endpoint and check if remote exists */ 115 for_each_endpoint_of_node(dev->of_node, ep) { 116 /* If the endpoint node exists, consider it enabled */ 117 remote = of_graph_get_remote_port(ep); 118 if (remote) { 119 of_node_put(remote); 120 of_node_put(ep); 121 return true; 122 } 123 } 124 125 return false; 126 } 127 128 static struct regmap_config meson_regmap_config = { 129 .reg_bits = 32, 130 .val_bits = 32, 131 .reg_stride = 4, 132 .max_register = 0x1000, 133 }; 134 135 static void meson_vpu_init(struct meson_drm *priv) 136 { 137 u32 value; 138 139 /* 140 * Slave dc0 and dc5 connected to master port 1. 141 * By default other slaves are connected to master port 0. 142 */ 143 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1) | 144 VPU_RDARB_SLAVE_TO_MASTER_PORT(5, 1); 145 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C1)); 146 147 /* Slave dc0 connected to master port 1 */ 148 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(0, 1); 149 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L1C2)); 150 151 /* Slave dc4 and dc7 connected to master port 1 */ 152 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(4, 1) | 153 VPU_RDARB_SLAVE_TO_MASTER_PORT(7, 1); 154 writel_relaxed(value, priv->io_base + _REG(VPU_RDARB_MODE_L2C1)); 155 156 /* Slave dc1 connected to master port 1 */ 157 value = VPU_RDARB_SLAVE_TO_MASTER_PORT(1, 1); 158 writel_relaxed(value, priv->io_base + _REG(VPU_WRARB_MODE_L2C1)); 159 } 160 161 struct meson_drm_soc_attr { 162 struct meson_drm_soc_limits limits; 163 const struct soc_device_attribute *attrs; 164 }; 165 166 static const struct meson_drm_soc_attr meson_drm_soc_attrs[] = { 167 /* S805X/S805Y HDMI PLL won't lock for HDMI PHY freq > 1,65GHz */ 168 { 169 .limits = { 170 .max_hdmi_phy_freq = 1650000, 171 }, 172 .attrs = (const struct soc_device_attribute []) { 173 { .soc_id = "GXL (S805*)", }, 174 { /* sentinel */ } 175 } 176 }, 177 }; 178 179 static int meson_drv_bind_master(struct device *dev, bool has_components) 180 { 181 struct platform_device *pdev = to_platform_device(dev); 182 const struct meson_drm_match_data *match; 183 struct meson_drm *priv; 184 struct drm_device *drm; 185 struct resource *res; 186 void __iomem *regs; 187 int ret, i; 188 189 /* Checks if an output connector is available */ 190 if (!meson_vpu_has_available_connectors(dev)) { 191 dev_err(dev, "No output connector available\n"); 192 return -ENODEV; 193 } 194 195 match = of_device_get_match_data(dev); 196 if (!match) 197 return -ENODEV; 198 199 drm = drm_dev_alloc(&meson_driver, dev); 200 if (IS_ERR(drm)) 201 return PTR_ERR(drm); 202 203 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 204 if (!priv) { 205 ret = -ENOMEM; 206 goto free_drm; 207 } 208 drm->dev_private = priv; 209 priv->drm = drm; 210 priv->dev = dev; 211 priv->compat = match->compat; 212 priv->afbcd.ops = match->afbcd_ops; 213 214 regs = devm_platform_ioremap_resource_byname(pdev, "vpu"); 215 if (IS_ERR(regs)) { 216 ret = PTR_ERR(regs); 217 goto free_drm; 218 } 219 220 priv->io_base = regs; 221 222 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hhi"); 223 if (!res) { 224 ret = -EINVAL; 225 goto free_drm; 226 } 227 /* Simply ioremap since it may be a shared register zone */ 228 regs = devm_ioremap(dev, res->start, resource_size(res)); 229 if (!regs) { 230 ret = -EADDRNOTAVAIL; 231 goto free_drm; 232 } 233 234 priv->hhi = devm_regmap_init_mmio(dev, regs, 235 &meson_regmap_config); 236 if (IS_ERR(priv->hhi)) { 237 dev_err(&pdev->dev, "Couldn't create the HHI regmap\n"); 238 ret = PTR_ERR(priv->hhi); 239 goto free_drm; 240 } 241 242 priv->canvas = meson_canvas_get(dev); 243 if (IS_ERR(priv->canvas)) { 244 ret = PTR_ERR(priv->canvas); 245 goto free_drm; 246 } 247 248 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_osd1); 249 if (ret) 250 goto free_drm; 251 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_0); 252 if (ret) { 253 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 254 goto free_drm; 255 } 256 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_1); 257 if (ret) { 258 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 259 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); 260 goto free_drm; 261 } 262 ret = meson_canvas_alloc(priv->canvas, &priv->canvas_id_vd1_2); 263 if (ret) { 264 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 265 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); 266 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); 267 goto free_drm; 268 } 269 270 priv->vsync_irq = platform_get_irq(pdev, 0); 271 272 ret = drm_vblank_init(drm, 1); 273 if (ret) 274 goto free_drm; 275 276 /* Assign limits per soc revision/package */ 277 for (i = 0 ; i < ARRAY_SIZE(meson_drm_soc_attrs) ; ++i) { 278 if (soc_device_match(meson_drm_soc_attrs[i].attrs)) { 279 priv->limits = &meson_drm_soc_attrs[i].limits; 280 break; 281 } 282 } 283 284 /* 285 * Remove early framebuffers (ie. simplefb). The framebuffer can be 286 * located anywhere in RAM 287 */ 288 ret = drm_aperture_remove_framebuffers(false, &meson_driver); 289 if (ret) 290 goto free_drm; 291 292 ret = drmm_mode_config_init(drm); 293 if (ret) 294 goto free_drm; 295 drm->mode_config.max_width = 3840; 296 drm->mode_config.max_height = 2160; 297 drm->mode_config.funcs = &meson_mode_config_funcs; 298 drm->mode_config.helper_private = &meson_mode_config_helpers; 299 300 /* Hardware Initialization */ 301 302 meson_vpu_init(priv); 303 meson_venc_init(priv); 304 meson_vpp_init(priv); 305 meson_viu_init(priv); 306 if (priv->afbcd.ops) { 307 ret = priv->afbcd.ops->init(priv); 308 if (ret) 309 goto free_drm; 310 } 311 312 /* Encoder Initialization */ 313 314 ret = meson_encoder_cvbs_init(priv); 315 if (ret) 316 goto exit_afbcd; 317 318 if (has_components) { 319 ret = component_bind_all(drm->dev, drm); 320 if (ret) { 321 dev_err(drm->dev, "Couldn't bind all components\n"); 322 goto exit_afbcd; 323 } 324 } 325 326 ret = meson_encoder_hdmi_init(priv); 327 if (ret) 328 goto exit_afbcd; 329 330 ret = meson_plane_create(priv); 331 if (ret) 332 goto exit_afbcd; 333 334 ret = meson_overlay_create(priv); 335 if (ret) 336 goto exit_afbcd; 337 338 ret = meson_crtc_create(priv); 339 if (ret) 340 goto exit_afbcd; 341 342 ret = request_irq(priv->vsync_irq, meson_irq, 0, drm->driver->name, drm); 343 if (ret) 344 goto exit_afbcd; 345 346 drm_mode_config_reset(drm); 347 348 drm_kms_helper_poll_init(drm); 349 350 platform_set_drvdata(pdev, priv); 351 352 ret = drm_dev_register(drm, 0); 353 if (ret) 354 goto uninstall_irq; 355 356 drm_fbdev_dma_setup(drm, 32); 357 358 return 0; 359 360 uninstall_irq: 361 free_irq(priv->vsync_irq, drm); 362 exit_afbcd: 363 if (priv->afbcd.ops) 364 priv->afbcd.ops->exit(priv); 365 free_drm: 366 drm_dev_put(drm); 367 368 return ret; 369 } 370 371 static int meson_drv_bind(struct device *dev) 372 { 373 return meson_drv_bind_master(dev, true); 374 } 375 376 static void meson_drv_unbind(struct device *dev) 377 { 378 struct meson_drm *priv = dev_get_drvdata(dev); 379 struct drm_device *drm = priv->drm; 380 381 if (priv->canvas) { 382 meson_canvas_free(priv->canvas, priv->canvas_id_osd1); 383 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_0); 384 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_1); 385 meson_canvas_free(priv->canvas, priv->canvas_id_vd1_2); 386 } 387 388 drm_dev_unregister(drm); 389 drm_kms_helper_poll_fini(drm); 390 drm_atomic_helper_shutdown(drm); 391 free_irq(priv->vsync_irq, drm); 392 drm_dev_put(drm); 393 394 meson_encoder_hdmi_remove(priv); 395 meson_encoder_cvbs_remove(priv); 396 397 component_unbind_all(dev, drm); 398 399 if (priv->afbcd.ops) 400 priv->afbcd.ops->exit(priv); 401 } 402 403 static const struct component_master_ops meson_drv_master_ops = { 404 .bind = meson_drv_bind, 405 .unbind = meson_drv_unbind, 406 }; 407 408 static int __maybe_unused meson_drv_pm_suspend(struct device *dev) 409 { 410 struct meson_drm *priv = dev_get_drvdata(dev); 411 412 if (!priv) 413 return 0; 414 415 return drm_mode_config_helper_suspend(priv->drm); 416 } 417 418 static int __maybe_unused meson_drv_pm_resume(struct device *dev) 419 { 420 struct meson_drm *priv = dev_get_drvdata(dev); 421 422 if (!priv) 423 return 0; 424 425 meson_vpu_init(priv); 426 meson_venc_init(priv); 427 meson_vpp_init(priv); 428 meson_viu_init(priv); 429 if (priv->afbcd.ops) 430 priv->afbcd.ops->init(priv); 431 432 return drm_mode_config_helper_resume(priv->drm); 433 } 434 435 static void meson_drv_shutdown(struct platform_device *pdev) 436 { 437 struct meson_drm *priv = dev_get_drvdata(&pdev->dev); 438 439 if (!priv) 440 return; 441 442 drm_kms_helper_poll_fini(priv->drm); 443 drm_atomic_helper_shutdown(priv->drm); 444 } 445 446 /* Possible connectors nodes to ignore */ 447 static const struct of_device_id connectors_match[] = { 448 { .compatible = "composite-video-connector" }, 449 { .compatible = "svideo-connector" }, 450 {} 451 }; 452 453 static int meson_drv_probe(struct platform_device *pdev) 454 { 455 struct component_match *match = NULL; 456 struct device_node *np = pdev->dev.of_node; 457 struct device_node *ep, *remote; 458 int count = 0; 459 460 for_each_endpoint_of_node(np, ep) { 461 remote = of_graph_get_remote_port_parent(ep); 462 if (!remote || !of_device_is_available(remote)) { 463 of_node_put(remote); 464 continue; 465 } 466 467 /* If an analog connector is detected, count it as an output */ 468 if (of_match_node(connectors_match, remote)) { 469 ++count; 470 of_node_put(remote); 471 continue; 472 } 473 474 dev_dbg(&pdev->dev, "parent %pOF remote match add %pOF parent %s\n", 475 np, remote, dev_name(&pdev->dev)); 476 477 component_match_add(&pdev->dev, &match, component_compare_of, remote); 478 479 of_node_put(remote); 480 481 ++count; 482 } 483 484 if (count && !match) 485 return meson_drv_bind_master(&pdev->dev, false); 486 487 /* If some endpoints were found, initialize the nodes */ 488 if (count) { 489 dev_info(&pdev->dev, "Queued %d outputs on vpu\n", count); 490 491 return component_master_add_with_match(&pdev->dev, 492 &meson_drv_master_ops, 493 match); 494 } 495 496 /* If no output endpoints were available, simply bail out */ 497 return 0; 498 }; 499 500 static int meson_drv_remove(struct platform_device *pdev) 501 { 502 component_master_del(&pdev->dev, &meson_drv_master_ops); 503 504 return 0; 505 } 506 507 static struct meson_drm_match_data meson_drm_gxbb_data = { 508 .compat = VPU_COMPATIBLE_GXBB, 509 }; 510 511 static struct meson_drm_match_data meson_drm_gxl_data = { 512 .compat = VPU_COMPATIBLE_GXL, 513 }; 514 515 static struct meson_drm_match_data meson_drm_gxm_data = { 516 .compat = VPU_COMPATIBLE_GXM, 517 .afbcd_ops = &meson_afbcd_gxm_ops, 518 }; 519 520 static struct meson_drm_match_data meson_drm_g12a_data = { 521 .compat = VPU_COMPATIBLE_G12A, 522 .afbcd_ops = &meson_afbcd_g12a_ops, 523 }; 524 525 static const struct of_device_id dt_match[] = { 526 { .compatible = "amlogic,meson-gxbb-vpu", 527 .data = (void *)&meson_drm_gxbb_data }, 528 { .compatible = "amlogic,meson-gxl-vpu", 529 .data = (void *)&meson_drm_gxl_data }, 530 { .compatible = "amlogic,meson-gxm-vpu", 531 .data = (void *)&meson_drm_gxm_data }, 532 { .compatible = "amlogic,meson-g12a-vpu", 533 .data = (void *)&meson_drm_g12a_data }, 534 {} 535 }; 536 MODULE_DEVICE_TABLE(of, dt_match); 537 538 static const struct dev_pm_ops meson_drv_pm_ops = { 539 SET_SYSTEM_SLEEP_PM_OPS(meson_drv_pm_suspend, meson_drv_pm_resume) 540 }; 541 542 static struct platform_driver meson_drm_platform_driver = { 543 .probe = meson_drv_probe, 544 .remove = meson_drv_remove, 545 .shutdown = meson_drv_shutdown, 546 .driver = { 547 .name = "meson-drm", 548 .of_match_table = dt_match, 549 .pm = &meson_drv_pm_ops, 550 }, 551 }; 552 553 drm_module_platform_driver(meson_drm_platform_driver); 554 555 MODULE_AUTHOR("Jasper St. Pierre <jstpierre@mecheye.net>"); 556 MODULE_AUTHOR("Neil Armstrong <narmstrong@baylibre.com>"); 557 MODULE_DESCRIPTION(DRIVER_DESC); 558 MODULE_LICENSE("GPL"); 559