xref: /linux/drivers/gpu/drm/mediatek/mtk_plane.h (revision 269ce3bd62e8ad83dadc80a2f755a799697ca4a3)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  * Author: CK Hu <ck.hu@mediatek.com>
5  */
6 
7 #ifndef _MTK_PLANE_H_
8 #define _MTK_PLANE_H_
9 
10 #include <drm/drm_crtc.h>
11 #include <linux/types.h>
12 
13 #define AFBC_DATA_BLOCK_WIDTH 32
14 #define AFBC_DATA_BLOCK_HEIGHT 8
15 #define AFBC_HEADER_BLOCK_SIZE 16
16 #define AFBC_HEADER_ALIGNMENT 1024
17 
18 struct mtk_plane_pending_state {
19 	bool				config;
20 	bool				enable;
21 	dma_addr_t			addr;
22 	dma_addr_t			hdr_addr;
23 	unsigned int			pitch;
24 	unsigned int			hdr_pitch;
25 	unsigned int			format;
26 	unsigned long long		modifier;
27 	unsigned int			x;
28 	unsigned int			y;
29 	unsigned int			width;
30 	unsigned int			height;
31 	unsigned int			rotation;
32 	bool				dirty;
33 	bool				async_dirty;
34 	bool				async_config;
35 	enum drm_color_encoding		color_encoding;
36 };
37 
38 struct mtk_plane_state {
39 	struct drm_plane_state		base;
40 	struct mtk_plane_pending_state	pending;
41 };
42 
43 static inline struct mtk_plane_state *
to_mtk_plane_state(struct drm_plane_state * state)44 to_mtk_plane_state(struct drm_plane_state *state)
45 {
46 	return container_of(state, struct mtk_plane_state, base);
47 }
48 
49 int mtk_plane_init(struct drm_device *dev, struct drm_plane *plane,
50 		   unsigned long possible_crtcs, enum drm_plane_type type,
51 		   unsigned int supported_rotations, const u32 blend_modes,
52 		   const u32 *formats, size_t num_formats, unsigned int plane_idx);
53 #endif
54