1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Copyright (c) 2015 MediaTek Inc. 4 * Author: YT SHEN <yt.shen@mediatek.com> 5 */ 6 7 #include <linux/component.h> 8 #include <linux/iommu.h> 9 #include <linux/module.h> 10 #include <linux/of_address.h> 11 #include <linux/of_platform.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/dma-mapping.h> 14 15 #include <drm/drm_atomic.h> 16 #include <drm/drm_atomic_helper.h> 17 #include <drm/drm_drv.h> 18 #include <drm/drm_fb_helper.h> 19 #include <drm/drm_fourcc.h> 20 #include <drm/drm_gem.h> 21 #include <drm/drm_gem_cma_helper.h> 22 #include <drm/drm_gem_framebuffer_helper.h> 23 #include <drm/drm_of.h> 24 #include <drm/drm_probe_helper.h> 25 #include <drm/drm_vblank.h> 26 27 #include "mtk_drm_crtc.h" 28 #include "mtk_drm_ddp.h" 29 #include "mtk_drm_ddp.h" 30 #include "mtk_drm_ddp_comp.h" 31 #include "mtk_drm_drv.h" 32 #include "mtk_drm_gem.h" 33 34 #define DRIVER_NAME "mediatek" 35 #define DRIVER_DESC "Mediatek SoC DRM" 36 #define DRIVER_DATE "20150513" 37 #define DRIVER_MAJOR 1 38 #define DRIVER_MINOR 0 39 40 static void mtk_atomic_schedule(struct mtk_drm_private *private, 41 struct drm_atomic_state *state) 42 { 43 private->commit.state = state; 44 schedule_work(&private->commit.work); 45 } 46 47 static void mtk_atomic_complete(struct mtk_drm_private *private, 48 struct drm_atomic_state *state) 49 { 50 struct drm_device *drm = private->drm; 51 52 drm_atomic_helper_wait_for_fences(drm, state, false); 53 54 /* 55 * Mediatek drm supports runtime PM, so plane registers cannot be 56 * written when their crtc is disabled. 57 * 58 * The comment for drm_atomic_helper_commit states: 59 * For drivers supporting runtime PM the recommended sequence is 60 * 61 * drm_atomic_helper_commit_modeset_disables(dev, state); 62 * drm_atomic_helper_commit_modeset_enables(dev, state); 63 * drm_atomic_helper_commit_planes(dev, state, 64 * DRM_PLANE_COMMIT_ACTIVE_ONLY); 65 * 66 * See the kerneldoc entries for these three functions for more details. 67 */ 68 drm_atomic_helper_commit_modeset_disables(drm, state); 69 drm_atomic_helper_commit_modeset_enables(drm, state); 70 drm_atomic_helper_commit_planes(drm, state, 71 DRM_PLANE_COMMIT_ACTIVE_ONLY); 72 73 drm_atomic_helper_wait_for_vblanks(drm, state); 74 75 drm_atomic_helper_cleanup_planes(drm, state); 76 drm_atomic_state_put(state); 77 } 78 79 static void mtk_atomic_work(struct work_struct *work) 80 { 81 struct mtk_drm_private *private = container_of(work, 82 struct mtk_drm_private, commit.work); 83 84 mtk_atomic_complete(private, private->commit.state); 85 } 86 87 static int mtk_atomic_commit(struct drm_device *drm, 88 struct drm_atomic_state *state, 89 bool async) 90 { 91 struct mtk_drm_private *private = drm->dev_private; 92 int ret; 93 94 ret = drm_atomic_helper_prepare_planes(drm, state); 95 if (ret) 96 return ret; 97 98 mutex_lock(&private->commit.lock); 99 flush_work(&private->commit.work); 100 101 ret = drm_atomic_helper_swap_state(state, true); 102 if (ret) { 103 mutex_unlock(&private->commit.lock); 104 drm_atomic_helper_cleanup_planes(drm, state); 105 return ret; 106 } 107 108 drm_atomic_state_get(state); 109 if (async) 110 mtk_atomic_schedule(private, state); 111 else 112 mtk_atomic_complete(private, state); 113 114 mutex_unlock(&private->commit.lock); 115 116 return 0; 117 } 118 119 static struct drm_framebuffer * 120 mtk_drm_mode_fb_create(struct drm_device *dev, 121 struct drm_file *file, 122 const struct drm_mode_fb_cmd2 *cmd) 123 { 124 const struct drm_format_info *info = drm_get_format_info(dev, cmd); 125 126 if (info->num_planes != 1) 127 return ERR_PTR(-EINVAL); 128 129 return drm_gem_fb_create(dev, file, cmd); 130 } 131 132 static const struct drm_mode_config_funcs mtk_drm_mode_config_funcs = { 133 .fb_create = mtk_drm_mode_fb_create, 134 .atomic_check = drm_atomic_helper_check, 135 .atomic_commit = mtk_atomic_commit, 136 }; 137 138 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_main[] = { 139 DDP_COMPONENT_OVL0, 140 DDP_COMPONENT_RDMA0, 141 DDP_COMPONENT_COLOR0, 142 DDP_COMPONENT_BLS, 143 DDP_COMPONENT_DSI0, 144 }; 145 146 static const enum mtk_ddp_comp_id mt2701_mtk_ddp_ext[] = { 147 DDP_COMPONENT_RDMA1, 148 DDP_COMPONENT_DPI0, 149 }; 150 151 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_main[] = { 152 DDP_COMPONENT_OVL0, 153 DDP_COMPONENT_COLOR0, 154 DDP_COMPONENT_AAL0, 155 DDP_COMPONENT_OD0, 156 DDP_COMPONENT_RDMA0, 157 DDP_COMPONENT_DPI0, 158 DDP_COMPONENT_PWM0, 159 }; 160 161 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_ext[] = { 162 DDP_COMPONENT_OVL1, 163 DDP_COMPONENT_COLOR1, 164 DDP_COMPONENT_AAL1, 165 DDP_COMPONENT_OD1, 166 DDP_COMPONENT_RDMA1, 167 DDP_COMPONENT_DPI1, 168 DDP_COMPONENT_PWM1, 169 }; 170 171 static const enum mtk_ddp_comp_id mt2712_mtk_ddp_third[] = { 172 DDP_COMPONENT_RDMA2, 173 DDP_COMPONENT_DSI3, 174 DDP_COMPONENT_PWM2, 175 }; 176 177 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_main[] = { 178 DDP_COMPONENT_OVL0, 179 DDP_COMPONENT_COLOR0, 180 DDP_COMPONENT_AAL0, 181 DDP_COMPONENT_OD0, 182 DDP_COMPONENT_RDMA0, 183 DDP_COMPONENT_UFOE, 184 DDP_COMPONENT_DSI0, 185 DDP_COMPONENT_PWM0, 186 }; 187 188 static const enum mtk_ddp_comp_id mt8173_mtk_ddp_ext[] = { 189 DDP_COMPONENT_OVL1, 190 DDP_COMPONENT_COLOR1, 191 DDP_COMPONENT_GAMMA, 192 DDP_COMPONENT_RDMA1, 193 DDP_COMPONENT_DPI0, 194 }; 195 196 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = { 197 .main_path = mt2701_mtk_ddp_main, 198 .main_len = ARRAY_SIZE(mt2701_mtk_ddp_main), 199 .ext_path = mt2701_mtk_ddp_ext, 200 .ext_len = ARRAY_SIZE(mt2701_mtk_ddp_ext), 201 .shadow_register = true, 202 }; 203 204 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = { 205 .main_path = mt2712_mtk_ddp_main, 206 .main_len = ARRAY_SIZE(mt2712_mtk_ddp_main), 207 .ext_path = mt2712_mtk_ddp_ext, 208 .ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext), 209 .third_path = mt2712_mtk_ddp_third, 210 .third_len = ARRAY_SIZE(mt2712_mtk_ddp_third), 211 }; 212 213 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = { 214 .main_path = mt8173_mtk_ddp_main, 215 .main_len = ARRAY_SIZE(mt8173_mtk_ddp_main), 216 .ext_path = mt8173_mtk_ddp_ext, 217 .ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext), 218 }; 219 220 static int mtk_drm_kms_init(struct drm_device *drm) 221 { 222 struct mtk_drm_private *private = drm->dev_private; 223 struct platform_device *pdev; 224 struct device_node *np; 225 struct device *dma_dev; 226 int ret; 227 228 if (!iommu_present(&platform_bus_type)) 229 return -EPROBE_DEFER; 230 231 pdev = of_find_device_by_node(private->mutex_node); 232 if (!pdev) { 233 dev_err(drm->dev, "Waiting for disp-mutex device %pOF\n", 234 private->mutex_node); 235 of_node_put(private->mutex_node); 236 return -EPROBE_DEFER; 237 } 238 private->mutex_dev = &pdev->dev; 239 240 drm_mode_config_init(drm); 241 242 drm->mode_config.min_width = 64; 243 drm->mode_config.min_height = 64; 244 245 /* 246 * set max width and height as default value(4096x4096). 247 * this value would be used to check framebuffer size limitation 248 * at drm_mode_addfb(). 249 */ 250 drm->mode_config.max_width = 4096; 251 drm->mode_config.max_height = 4096; 252 drm->mode_config.funcs = &mtk_drm_mode_config_funcs; 253 254 ret = component_bind_all(drm->dev, drm); 255 if (ret) 256 goto err_config_cleanup; 257 258 /* 259 * We currently support two fixed data streams, each optional, 260 * and each statically assigned to a crtc: 261 * OVL0 -> COLOR0 -> AAL -> OD -> RDMA0 -> UFOE -> DSI0 ... 262 */ 263 ret = mtk_drm_crtc_create(drm, private->data->main_path, 264 private->data->main_len); 265 if (ret < 0) 266 goto err_component_unbind; 267 /* ... and OVL1 -> COLOR1 -> GAMMA -> RDMA1 -> DPI0. */ 268 ret = mtk_drm_crtc_create(drm, private->data->ext_path, 269 private->data->ext_len); 270 if (ret < 0) 271 goto err_component_unbind; 272 273 ret = mtk_drm_crtc_create(drm, private->data->third_path, 274 private->data->third_len); 275 if (ret < 0) 276 goto err_component_unbind; 277 278 /* Use OVL device for all DMA memory allocations */ 279 np = private->comp_node[private->data->main_path[0]] ?: 280 private->comp_node[private->data->ext_path[0]]; 281 pdev = of_find_device_by_node(np); 282 if (!pdev) { 283 ret = -ENODEV; 284 dev_err(drm->dev, "Need at least one OVL device\n"); 285 goto err_component_unbind; 286 } 287 288 dma_dev = &pdev->dev; 289 private->dma_dev = dma_dev; 290 291 /* 292 * Configure the DMA segment size to make sure we get contiguous IOVA 293 * when importing PRIME buffers. 294 */ 295 if (!dma_dev->dma_parms) { 296 private->dma_parms_allocated = true; 297 dma_dev->dma_parms = 298 devm_kzalloc(drm->dev, sizeof(*dma_dev->dma_parms), 299 GFP_KERNEL); 300 } 301 if (!dma_dev->dma_parms) { 302 ret = -ENOMEM; 303 goto err_component_unbind; 304 } 305 306 ret = dma_set_max_seg_size(dma_dev, (unsigned int)DMA_BIT_MASK(32)); 307 if (ret) { 308 dev_err(dma_dev, "Failed to set DMA segment size\n"); 309 goto err_unset_dma_parms; 310 } 311 312 /* 313 * We don't use the drm_irq_install() helpers provided by the DRM 314 * core, so we need to set this manually in order to allow the 315 * DRM_IOCTL_WAIT_VBLANK to operate correctly. 316 */ 317 drm->irq_enabled = true; 318 ret = drm_vblank_init(drm, MAX_CRTC); 319 if (ret < 0) 320 goto err_unset_dma_parms; 321 322 drm_kms_helper_poll_init(drm); 323 drm_mode_config_reset(drm); 324 325 return 0; 326 327 err_unset_dma_parms: 328 if (private->dma_parms_allocated) 329 dma_dev->dma_parms = NULL; 330 err_component_unbind: 331 component_unbind_all(drm->dev, drm); 332 err_config_cleanup: 333 drm_mode_config_cleanup(drm); 334 335 return ret; 336 } 337 338 static void mtk_drm_kms_deinit(struct drm_device *drm) 339 { 340 struct mtk_drm_private *private = drm->dev_private; 341 342 drm_kms_helper_poll_fini(drm); 343 drm_atomic_helper_shutdown(drm); 344 345 if (private->dma_parms_allocated) 346 private->dma_dev->dma_parms = NULL; 347 348 component_unbind_all(drm->dev, drm); 349 drm_mode_config_cleanup(drm); 350 } 351 352 static const struct file_operations mtk_drm_fops = { 353 .owner = THIS_MODULE, 354 .open = drm_open, 355 .release = drm_release, 356 .unlocked_ioctl = drm_ioctl, 357 .mmap = mtk_drm_gem_mmap, 358 .poll = drm_poll, 359 .read = drm_read, 360 .compat_ioctl = drm_compat_ioctl, 361 }; 362 363 /* 364 * We need to override this because the device used to import the memory is 365 * not dev->dev, as drm_gem_prime_import() expects. 366 */ 367 struct drm_gem_object *mtk_drm_gem_prime_import(struct drm_device *dev, 368 struct dma_buf *dma_buf) 369 { 370 struct mtk_drm_private *private = dev->dev_private; 371 372 return drm_gem_prime_import_dev(dev, dma_buf, private->dma_dev); 373 } 374 375 static struct drm_driver mtk_drm_driver = { 376 .driver_features = DRIVER_MODESET | DRIVER_GEM | DRIVER_ATOMIC, 377 378 .gem_free_object_unlocked = mtk_drm_gem_free_object, 379 .gem_vm_ops = &drm_gem_cma_vm_ops, 380 .dumb_create = mtk_drm_gem_dumb_create, 381 382 .prime_handle_to_fd = drm_gem_prime_handle_to_fd, 383 .prime_fd_to_handle = drm_gem_prime_fd_to_handle, 384 .gem_prime_import = mtk_drm_gem_prime_import, 385 .gem_prime_get_sg_table = mtk_gem_prime_get_sg_table, 386 .gem_prime_import_sg_table = mtk_gem_prime_import_sg_table, 387 .gem_prime_mmap = mtk_drm_gem_mmap_buf, 388 .gem_prime_vmap = mtk_drm_gem_prime_vmap, 389 .gem_prime_vunmap = mtk_drm_gem_prime_vunmap, 390 .fops = &mtk_drm_fops, 391 392 .name = DRIVER_NAME, 393 .desc = DRIVER_DESC, 394 .date = DRIVER_DATE, 395 .major = DRIVER_MAJOR, 396 .minor = DRIVER_MINOR, 397 }; 398 399 static int compare_of(struct device *dev, void *data) 400 { 401 return dev->of_node == data; 402 } 403 404 static int mtk_drm_bind(struct device *dev) 405 { 406 struct mtk_drm_private *private = dev_get_drvdata(dev); 407 struct drm_device *drm; 408 int ret; 409 410 drm = drm_dev_alloc(&mtk_drm_driver, dev); 411 if (IS_ERR(drm)) 412 return PTR_ERR(drm); 413 414 drm->dev_private = private; 415 private->drm = drm; 416 417 ret = mtk_drm_kms_init(drm); 418 if (ret < 0) 419 goto err_free; 420 421 ret = drm_dev_register(drm, 0); 422 if (ret < 0) 423 goto err_deinit; 424 425 ret = drm_fbdev_generic_setup(drm, 32); 426 if (ret) 427 DRM_ERROR("Failed to initialize fbdev: %d\n", ret); 428 429 return 0; 430 431 err_deinit: 432 mtk_drm_kms_deinit(drm); 433 err_free: 434 drm_dev_put(drm); 435 return ret; 436 } 437 438 static void mtk_drm_unbind(struct device *dev) 439 { 440 struct mtk_drm_private *private = dev_get_drvdata(dev); 441 442 drm_dev_unregister(private->drm); 443 mtk_drm_kms_deinit(private->drm); 444 drm_dev_put(private->drm); 445 private->num_pipes = 0; 446 private->drm = NULL; 447 } 448 449 static const struct component_master_ops mtk_drm_ops = { 450 .bind = mtk_drm_bind, 451 .unbind = mtk_drm_unbind, 452 }; 453 454 static const struct of_device_id mtk_ddp_comp_dt_ids[] = { 455 { .compatible = "mediatek,mt2701-disp-ovl", 456 .data = (void *)MTK_DISP_OVL }, 457 { .compatible = "mediatek,mt8173-disp-ovl", 458 .data = (void *)MTK_DISP_OVL }, 459 { .compatible = "mediatek,mt2701-disp-rdma", 460 .data = (void *)MTK_DISP_RDMA }, 461 { .compatible = "mediatek,mt8173-disp-rdma", 462 .data = (void *)MTK_DISP_RDMA }, 463 { .compatible = "mediatek,mt8173-disp-wdma", 464 .data = (void *)MTK_DISP_WDMA }, 465 { .compatible = "mediatek,mt2701-disp-color", 466 .data = (void *)MTK_DISP_COLOR }, 467 { .compatible = "mediatek,mt8173-disp-color", 468 .data = (void *)MTK_DISP_COLOR }, 469 { .compatible = "mediatek,mt8173-disp-aal", 470 .data = (void *)MTK_DISP_AAL}, 471 { .compatible = "mediatek,mt8173-disp-gamma", 472 .data = (void *)MTK_DISP_GAMMA, }, 473 { .compatible = "mediatek,mt8173-disp-ufoe", 474 .data = (void *)MTK_DISP_UFOE }, 475 { .compatible = "mediatek,mt2701-dsi", 476 .data = (void *)MTK_DSI }, 477 { .compatible = "mediatek,mt8173-dsi", 478 .data = (void *)MTK_DSI }, 479 { .compatible = "mediatek,mt2701-dpi", 480 .data = (void *)MTK_DPI }, 481 { .compatible = "mediatek,mt8173-dpi", 482 .data = (void *)MTK_DPI }, 483 { .compatible = "mediatek,mt2701-disp-mutex", 484 .data = (void *)MTK_DISP_MUTEX }, 485 { .compatible = "mediatek,mt2712-disp-mutex", 486 .data = (void *)MTK_DISP_MUTEX }, 487 { .compatible = "mediatek,mt8173-disp-mutex", 488 .data = (void *)MTK_DISP_MUTEX }, 489 { .compatible = "mediatek,mt2701-disp-pwm", 490 .data = (void *)MTK_DISP_BLS }, 491 { .compatible = "mediatek,mt8173-disp-pwm", 492 .data = (void *)MTK_DISP_PWM }, 493 { .compatible = "mediatek,mt8173-disp-od", 494 .data = (void *)MTK_DISP_OD }, 495 { } 496 }; 497 498 static int mtk_drm_probe(struct platform_device *pdev) 499 { 500 struct device *dev = &pdev->dev; 501 struct mtk_drm_private *private; 502 struct resource *mem; 503 struct device_node *node; 504 struct component_match *match = NULL; 505 int ret; 506 int i; 507 508 private = devm_kzalloc(dev, sizeof(*private), GFP_KERNEL); 509 if (!private) 510 return -ENOMEM; 511 512 mutex_init(&private->commit.lock); 513 INIT_WORK(&private->commit.work, mtk_atomic_work); 514 private->data = of_device_get_match_data(dev); 515 516 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); 517 private->config_regs = devm_ioremap_resource(dev, mem); 518 if (IS_ERR(private->config_regs)) { 519 ret = PTR_ERR(private->config_regs); 520 dev_err(dev, "Failed to ioremap mmsys-config resource: %d\n", 521 ret); 522 return ret; 523 } 524 525 /* Iterate over sibling DISP function blocks */ 526 for_each_child_of_node(dev->of_node->parent, node) { 527 const struct of_device_id *of_id; 528 enum mtk_ddp_comp_type comp_type; 529 int comp_id; 530 531 of_id = of_match_node(mtk_ddp_comp_dt_ids, node); 532 if (!of_id) 533 continue; 534 535 if (!of_device_is_available(node)) { 536 dev_dbg(dev, "Skipping disabled component %pOF\n", 537 node); 538 continue; 539 } 540 541 comp_type = (enum mtk_ddp_comp_type)of_id->data; 542 543 if (comp_type == MTK_DISP_MUTEX) { 544 private->mutex_node = of_node_get(node); 545 continue; 546 } 547 548 comp_id = mtk_ddp_comp_get_id(node, comp_type); 549 if (comp_id < 0) { 550 dev_warn(dev, "Skipping unknown component %pOF\n", 551 node); 552 continue; 553 } 554 555 private->comp_node[comp_id] = of_node_get(node); 556 557 /* 558 * Currently only the COLOR, OVL, RDMA, DSI, and DPI blocks have 559 * separate component platform drivers and initialize their own 560 * DDP component structure. The others are initialized here. 561 */ 562 if (comp_type == MTK_DISP_COLOR || 563 comp_type == MTK_DISP_OVL || 564 comp_type == MTK_DISP_OVL_2L || 565 comp_type == MTK_DISP_RDMA || 566 comp_type == MTK_DSI || 567 comp_type == MTK_DPI) { 568 dev_info(dev, "Adding component match for %pOF\n", 569 node); 570 drm_of_component_match_add(dev, &match, compare_of, 571 node); 572 } else { 573 struct mtk_ddp_comp *comp; 574 575 comp = devm_kzalloc(dev, sizeof(*comp), GFP_KERNEL); 576 if (!comp) { 577 ret = -ENOMEM; 578 of_node_put(node); 579 goto err_node; 580 } 581 582 ret = mtk_ddp_comp_init(dev, node, comp, comp_id, NULL); 583 if (ret) { 584 of_node_put(node); 585 goto err_node; 586 } 587 588 private->ddp_comp[comp_id] = comp; 589 } 590 } 591 592 if (!private->mutex_node) { 593 dev_err(dev, "Failed to find disp-mutex node\n"); 594 ret = -ENODEV; 595 goto err_node; 596 } 597 598 pm_runtime_enable(dev); 599 600 platform_set_drvdata(pdev, private); 601 602 ret = component_master_add_with_match(dev, &mtk_drm_ops, match); 603 if (ret) 604 goto err_pm; 605 606 return 0; 607 608 err_pm: 609 pm_runtime_disable(dev); 610 err_node: 611 of_node_put(private->mutex_node); 612 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 613 of_node_put(private->comp_node[i]); 614 return ret; 615 } 616 617 static int mtk_drm_remove(struct platform_device *pdev) 618 { 619 struct mtk_drm_private *private = platform_get_drvdata(pdev); 620 int i; 621 622 component_master_del(&pdev->dev, &mtk_drm_ops); 623 pm_runtime_disable(&pdev->dev); 624 of_node_put(private->mutex_node); 625 for (i = 0; i < DDP_COMPONENT_ID_MAX; i++) 626 of_node_put(private->comp_node[i]); 627 628 return 0; 629 } 630 631 #ifdef CONFIG_PM_SLEEP 632 static int mtk_drm_sys_suspend(struct device *dev) 633 { 634 struct mtk_drm_private *private = dev_get_drvdata(dev); 635 struct drm_device *drm = private->drm; 636 int ret; 637 638 ret = drm_mode_config_helper_suspend(drm); 639 DRM_DEBUG_DRIVER("mtk_drm_sys_suspend\n"); 640 641 return ret; 642 } 643 644 static int mtk_drm_sys_resume(struct device *dev) 645 { 646 struct mtk_drm_private *private = dev_get_drvdata(dev); 647 struct drm_device *drm = private->drm; 648 int ret; 649 650 ret = drm_mode_config_helper_resume(drm); 651 DRM_DEBUG_DRIVER("mtk_drm_sys_resume\n"); 652 653 return ret; 654 } 655 #endif 656 657 static SIMPLE_DEV_PM_OPS(mtk_drm_pm_ops, mtk_drm_sys_suspend, 658 mtk_drm_sys_resume); 659 660 static const struct of_device_id mtk_drm_of_ids[] = { 661 { .compatible = "mediatek,mt2701-mmsys", 662 .data = &mt2701_mmsys_driver_data}, 663 { .compatible = "mediatek,mt2712-mmsys", 664 .data = &mt2712_mmsys_driver_data}, 665 { .compatible = "mediatek,mt8173-mmsys", 666 .data = &mt8173_mmsys_driver_data}, 667 { } 668 }; 669 670 static struct platform_driver mtk_drm_platform_driver = { 671 .probe = mtk_drm_probe, 672 .remove = mtk_drm_remove, 673 .driver = { 674 .name = "mediatek-drm", 675 .of_match_table = mtk_drm_of_ids, 676 .pm = &mtk_drm_pm_ops, 677 }, 678 }; 679 680 static struct platform_driver * const mtk_drm_drivers[] = { 681 &mtk_ddp_driver, 682 &mtk_disp_color_driver, 683 &mtk_disp_ovl_driver, 684 &mtk_disp_rdma_driver, 685 &mtk_dpi_driver, 686 &mtk_drm_platform_driver, 687 &mtk_mipi_tx_driver, 688 &mtk_dsi_driver, 689 }; 690 691 static int __init mtk_drm_init(void) 692 { 693 return platform_register_drivers(mtk_drm_drivers, 694 ARRAY_SIZE(mtk_drm_drivers)); 695 } 696 697 static void __exit mtk_drm_exit(void) 698 { 699 platform_unregister_drivers(mtk_drm_drivers, 700 ARRAY_SIZE(mtk_drm_drivers)); 701 } 702 703 module_init(mtk_drm_init); 704 module_exit(mtk_drm_exit); 705 706 MODULE_AUTHOR("YT SHEN <yt.shen@mediatek.com>"); 707 MODULE_DESCRIPTION("Mediatek SoC DRM driver"); 708 MODULE_LICENSE("GPL v2"); 709