xref: /linux/drivers/gpu/drm/mediatek/mtk_crtc.c (revision 52a5a22d8afe3bd195f7b470c7535c63717f5ff7)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Copyright (c) 2015 MediaTek Inc.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/dma-mapping.h>
8 #include <linux/mailbox_controller.h>
9 #include <linux/of.h>
10 #include <linux/pm_runtime.h>
11 #include <linux/soc/mediatek/mtk-cmdq.h>
12 #include <linux/soc/mediatek/mtk-mmsys.h>
13 #include <linux/soc/mediatek/mtk-mutex.h>
14 
15 #include <asm/barrier.h>
16 
17 #include <drm/drm_atomic.h>
18 #include <drm/drm_atomic_helper.h>
19 #include <drm/drm_probe_helper.h>
20 #include <drm/drm_vblank.h>
21 
22 #include "mtk_crtc.h"
23 #include "mtk_ddp_comp.h"
24 #include "mtk_drm_drv.h"
25 #include "mtk_gem.h"
26 #include "mtk_plane.h"
27 
28 /*
29  * struct mtk_crtc - MediaTek specific crtc structure.
30  * @base: crtc object.
31  * @enabled: records whether crtc_enable succeeded
32  * @planes: array of 4 drm_plane structures, one for each overlay plane
33  * @pending_planes: whether any plane has pending changes to be applied
34  * @mmsys_dev: pointer to the mmsys device for configuration registers
35  * @mutex: handle to one of the ten disp_mutex streams
36  * @ddp_comp_nr: number of components in ddp_comp
37  * @ddp_comp: array of pointers the mtk_ddp_comp structures used by this crtc
38  *
39  * TODO: Needs update: this header is missing a bunch of member descriptions.
40  */
41 struct mtk_crtc {
42 	struct drm_crtc			base;
43 	bool				enabled;
44 
45 	bool				pending_needs_vblank;
46 	struct drm_pending_vblank_event	*event;
47 
48 	struct drm_plane		*planes;
49 	unsigned int			layer_nr;
50 	bool				pending_planes;
51 	bool				pending_async_planes;
52 
53 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
54 	struct cmdq_client		cmdq_client;
55 	struct cmdq_pkt			cmdq_handle;
56 	u32				cmdq_event;
57 	u32				cmdq_vblank_cnt;
58 	wait_queue_head_t		cb_blocking_queue;
59 #endif
60 
61 	struct device			*mmsys_dev;
62 	struct device			*dma_dev;
63 	struct mtk_mutex		*mutex;
64 	unsigned int			ddp_comp_nr;
65 	struct mtk_ddp_comp		**ddp_comp;
66 	unsigned int			num_conn_routes;
67 	const struct mtk_drm_route	*conn_routes;
68 
69 	/* lock for display hardware access */
70 	struct mutex			hw_lock;
71 	bool				config_updating;
72 	/* lock for config_updating to cmd buffer */
73 	spinlock_t			config_lock;
74 };
75 
76 struct mtk_crtc_state {
77 	struct drm_crtc_state		base;
78 
79 	bool				pending_config;
80 	unsigned int			pending_width;
81 	unsigned int			pending_height;
82 	unsigned int			pending_vrefresh;
83 };
84 
85 static inline struct mtk_crtc *to_mtk_crtc(struct drm_crtc *c)
86 {
87 	return container_of(c, struct mtk_crtc, base);
88 }
89 
90 static inline struct mtk_crtc_state *to_mtk_crtc_state(struct drm_crtc_state *s)
91 {
92 	return container_of(s, struct mtk_crtc_state, base);
93 }
94 
95 static void mtk_crtc_finish_page_flip(struct mtk_crtc *mtk_crtc)
96 {
97 	struct drm_crtc *crtc = &mtk_crtc->base;
98 	unsigned long flags;
99 
100 	if (mtk_crtc->event) {
101 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
102 		drm_crtc_send_vblank_event(crtc, mtk_crtc->event);
103 		drm_crtc_vblank_put(crtc);
104 		mtk_crtc->event = NULL;
105 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
106 	}
107 }
108 
109 static void mtk_drm_finish_page_flip(struct mtk_crtc *mtk_crtc)
110 {
111 	unsigned long flags;
112 
113 	drm_crtc_handle_vblank(&mtk_crtc->base);
114 
115 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
116 	if (mtk_crtc->cmdq_client.chan)
117 		return;
118 #endif
119 
120 	spin_lock_irqsave(&mtk_crtc->config_lock, flags);
121 	if (!mtk_crtc->config_updating && mtk_crtc->pending_needs_vblank) {
122 		mtk_crtc_finish_page_flip(mtk_crtc);
123 		mtk_crtc->pending_needs_vblank = false;
124 	}
125 	spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
126 }
127 
128 static void mtk_crtc_destroy(struct drm_crtc *crtc)
129 {
130 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
131 	int i;
132 
133 	mtk_mutex_put(mtk_crtc->mutex);
134 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
135 	if (mtk_crtc->cmdq_client.chan) {
136 		cmdq_pkt_destroy(&mtk_crtc->cmdq_client, &mtk_crtc->cmdq_handle);
137 		mbox_free_channel(mtk_crtc->cmdq_client.chan);
138 		mtk_crtc->cmdq_client.chan = NULL;
139 	}
140 #endif
141 
142 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
143 		struct mtk_ddp_comp *comp;
144 
145 		comp = mtk_crtc->ddp_comp[i];
146 		mtk_ddp_comp_unregister_vblank_cb(comp);
147 	}
148 
149 	drm_crtc_cleanup(crtc);
150 }
151 
152 static void mtk_crtc_reset(struct drm_crtc *crtc)
153 {
154 	struct mtk_crtc_state *state;
155 
156 	if (crtc->state)
157 		__drm_atomic_helper_crtc_destroy_state(crtc->state);
158 
159 	kfree(to_mtk_crtc_state(crtc->state));
160 	crtc->state = NULL;
161 
162 	state = kzalloc(sizeof(*state), GFP_KERNEL);
163 	if (state)
164 		__drm_atomic_helper_crtc_reset(crtc, &state->base);
165 }
166 
167 static struct drm_crtc_state *mtk_crtc_duplicate_state(struct drm_crtc *crtc)
168 {
169 	struct mtk_crtc_state *state;
170 
171 	state = kmalloc(sizeof(*state), GFP_KERNEL);
172 	if (!state)
173 		return NULL;
174 
175 	__drm_atomic_helper_crtc_duplicate_state(crtc, &state->base);
176 
177 	WARN_ON(state->base.crtc != crtc);
178 	state->base.crtc = crtc;
179 	state->pending_config = false;
180 
181 	return &state->base;
182 }
183 
184 static void mtk_crtc_destroy_state(struct drm_crtc *crtc,
185 				   struct drm_crtc_state *state)
186 {
187 	__drm_atomic_helper_crtc_destroy_state(state);
188 	kfree(to_mtk_crtc_state(state));
189 }
190 
191 static enum drm_mode_status
192 mtk_crtc_mode_valid(struct drm_crtc *crtc, const struct drm_display_mode *mode)
193 {
194 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
195 	enum drm_mode_status status = MODE_OK;
196 	int i;
197 
198 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
199 		status = mtk_ddp_comp_mode_valid(mtk_crtc->ddp_comp[i], mode);
200 		if (status != MODE_OK)
201 			break;
202 	}
203 	return status;
204 }
205 
206 static bool mtk_crtc_mode_fixup(struct drm_crtc *crtc,
207 				const struct drm_display_mode *mode,
208 				struct drm_display_mode *adjusted_mode)
209 {
210 	/* Nothing to do here, but this callback is mandatory. */
211 	return true;
212 }
213 
214 static void mtk_crtc_mode_set_nofb(struct drm_crtc *crtc)
215 {
216 	struct mtk_crtc_state *state = to_mtk_crtc_state(crtc->state);
217 
218 	state->pending_width = crtc->mode.hdisplay;
219 	state->pending_height = crtc->mode.vdisplay;
220 	state->pending_vrefresh = drm_mode_vrefresh(&crtc->mode);
221 	wmb();	/* Make sure the above parameters are set before update */
222 	state->pending_config = true;
223 }
224 
225 static int mtk_crtc_ddp_clk_enable(struct mtk_crtc *mtk_crtc)
226 {
227 	int ret;
228 	int i;
229 
230 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
231 		ret = mtk_ddp_comp_clk_enable(mtk_crtc->ddp_comp[i]);
232 		if (ret) {
233 			DRM_ERROR("Failed to enable clock %d: %d\n", i, ret);
234 			goto err;
235 		}
236 	}
237 
238 	return 0;
239 err:
240 	while (--i >= 0)
241 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
242 	return ret;
243 }
244 
245 static void mtk_crtc_ddp_clk_disable(struct mtk_crtc *mtk_crtc)
246 {
247 	int i;
248 
249 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
250 		mtk_ddp_comp_clk_disable(mtk_crtc->ddp_comp[i]);
251 }
252 
253 static
254 struct mtk_ddp_comp *mtk_ddp_comp_for_plane(struct drm_crtc *crtc,
255 					    struct drm_plane *plane,
256 					    unsigned int *local_layer)
257 {
258 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
259 	struct mtk_ddp_comp *comp;
260 	int i, count = 0;
261 	unsigned int local_index = plane - mtk_crtc->planes;
262 
263 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
264 		comp = mtk_crtc->ddp_comp[i];
265 		if (local_index < (count + mtk_ddp_comp_layer_nr(comp))) {
266 			*local_layer = local_index - count;
267 			return comp;
268 		}
269 		count += mtk_ddp_comp_layer_nr(comp);
270 	}
271 
272 	WARN(1, "Failed to find component for plane %d\n", plane->index);
273 	return NULL;
274 }
275 
276 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
277 static void ddp_cmdq_cb(struct mbox_client *cl, void *mssg)
278 {
279 	struct cmdq_cb_data *data = mssg;
280 	struct cmdq_client *cmdq_cl = container_of(cl, struct cmdq_client, client);
281 	struct mtk_crtc *mtk_crtc = container_of(cmdq_cl, struct mtk_crtc, cmdq_client);
282 	struct mtk_crtc_state *state;
283 	unsigned int i;
284 	unsigned long flags;
285 
286 	if (data->sta < 0)
287 		return;
288 
289 	state = to_mtk_crtc_state(mtk_crtc->base.state);
290 
291 	spin_lock_irqsave(&mtk_crtc->config_lock, flags);
292 	if (mtk_crtc->config_updating)
293 		goto ddp_cmdq_cb_out;
294 
295 	state->pending_config = false;
296 
297 	if (mtk_crtc->pending_planes) {
298 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
299 			struct drm_plane *plane = &mtk_crtc->planes[i];
300 			struct mtk_plane_state *plane_state;
301 
302 			plane_state = to_mtk_plane_state(plane->state);
303 
304 			plane_state->pending.config = false;
305 		}
306 		mtk_crtc->pending_planes = false;
307 	}
308 
309 	if (mtk_crtc->pending_async_planes) {
310 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
311 			struct drm_plane *plane = &mtk_crtc->planes[i];
312 			struct mtk_plane_state *plane_state;
313 
314 			plane_state = to_mtk_plane_state(plane->state);
315 
316 			plane_state->pending.async_config = false;
317 		}
318 		mtk_crtc->pending_async_planes = false;
319 	}
320 
321 ddp_cmdq_cb_out:
322 
323 	if (mtk_crtc->pending_needs_vblank) {
324 		mtk_crtc_finish_page_flip(mtk_crtc);
325 		mtk_crtc->pending_needs_vblank = false;
326 	}
327 
328 	spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
329 
330 	mtk_crtc->cmdq_vblank_cnt = 0;
331 	wake_up(&mtk_crtc->cb_blocking_queue);
332 }
333 #endif
334 
335 static int mtk_crtc_ddp_hw_init(struct mtk_crtc *mtk_crtc)
336 {
337 	struct drm_crtc *crtc = &mtk_crtc->base;
338 	struct drm_connector *connector;
339 	struct drm_encoder *encoder;
340 	struct drm_connector_list_iter conn_iter;
341 	unsigned int width, height, vrefresh, bpc = MTK_MAX_BPC;
342 	int ret;
343 	int i;
344 
345 	if (WARN_ON(!crtc->state))
346 		return -EINVAL;
347 
348 	width = crtc->state->adjusted_mode.hdisplay;
349 	height = crtc->state->adjusted_mode.vdisplay;
350 	vrefresh = drm_mode_vrefresh(&crtc->state->adjusted_mode);
351 
352 	drm_for_each_encoder(encoder, crtc->dev) {
353 		if (encoder->crtc != crtc)
354 			continue;
355 
356 		drm_connector_list_iter_begin(crtc->dev, &conn_iter);
357 		drm_for_each_connector_iter(connector, &conn_iter) {
358 			if (connector->encoder != encoder)
359 				continue;
360 			if (connector->display_info.bpc != 0 &&
361 			    bpc > connector->display_info.bpc)
362 				bpc = connector->display_info.bpc;
363 		}
364 		drm_connector_list_iter_end(&conn_iter);
365 	}
366 
367 	ret = pm_runtime_resume_and_get(crtc->dev->dev);
368 	if (ret < 0) {
369 		DRM_ERROR("Failed to enable power domain: %d\n", ret);
370 		return ret;
371 	}
372 
373 	ret = mtk_mutex_prepare(mtk_crtc->mutex);
374 	if (ret < 0) {
375 		DRM_ERROR("Failed to enable mutex clock: %d\n", ret);
376 		goto err_pm_runtime_put;
377 	}
378 
379 	ret = mtk_crtc_ddp_clk_enable(mtk_crtc);
380 	if (ret < 0) {
381 		DRM_ERROR("Failed to enable component clocks: %d\n", ret);
382 		goto err_mutex_unprepare;
383 	}
384 
385 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
386 		if (!mtk_ddp_comp_connect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
387 					  mtk_crtc->ddp_comp[i + 1]->id))
388 			mtk_mmsys_ddp_connect(mtk_crtc->mmsys_dev,
389 					      mtk_crtc->ddp_comp[i]->id,
390 					      mtk_crtc->ddp_comp[i + 1]->id);
391 		if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
392 			mtk_mutex_add_comp(mtk_crtc->mutex,
393 					   mtk_crtc->ddp_comp[i]->id);
394 	}
395 	if (!mtk_ddp_comp_add(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
396 		mtk_mutex_add_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
397 	mtk_mutex_enable(mtk_crtc->mutex);
398 
399 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
400 		struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[i];
401 
402 		if (i == 1)
403 			mtk_ddp_comp_bgclr_in_on(comp);
404 
405 		mtk_ddp_comp_config(comp, width, height, vrefresh, bpc, NULL);
406 		mtk_ddp_comp_start(comp);
407 	}
408 
409 	/* Initially configure all planes */
410 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
411 		struct drm_plane *plane = &mtk_crtc->planes[i];
412 		struct mtk_plane_state *plane_state;
413 		struct mtk_ddp_comp *comp;
414 		unsigned int local_layer;
415 
416 		plane_state = to_mtk_plane_state(plane->state);
417 
418 		/* should not enable layer before crtc enabled */
419 		plane_state->pending.enable = false;
420 		comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
421 		if (comp)
422 			mtk_ddp_comp_layer_config(comp, local_layer,
423 						  plane_state, NULL);
424 	}
425 
426 	return 0;
427 
428 err_mutex_unprepare:
429 	mtk_mutex_unprepare(mtk_crtc->mutex);
430 err_pm_runtime_put:
431 	pm_runtime_put(crtc->dev->dev);
432 	return ret;
433 }
434 
435 static void mtk_crtc_ddp_hw_fini(struct mtk_crtc *mtk_crtc)
436 {
437 	struct drm_device *drm = mtk_crtc->base.dev;
438 	struct drm_crtc *crtc = &mtk_crtc->base;
439 	unsigned long flags;
440 	int i;
441 
442 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
443 		mtk_ddp_comp_stop(mtk_crtc->ddp_comp[i]);
444 		if (i == 1)
445 			mtk_ddp_comp_bgclr_in_off(mtk_crtc->ddp_comp[i]);
446 	}
447 
448 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
449 		if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
450 			mtk_mutex_remove_comp(mtk_crtc->mutex,
451 					      mtk_crtc->ddp_comp[i]->id);
452 	mtk_mutex_disable(mtk_crtc->mutex);
453 	for (i = 0; i < mtk_crtc->ddp_comp_nr - 1; i++) {
454 		if (!mtk_ddp_comp_disconnect(mtk_crtc->ddp_comp[i], mtk_crtc->mmsys_dev,
455 					     mtk_crtc->ddp_comp[i + 1]->id))
456 			mtk_mmsys_ddp_disconnect(mtk_crtc->mmsys_dev,
457 						 mtk_crtc->ddp_comp[i]->id,
458 						 mtk_crtc->ddp_comp[i + 1]->id);
459 		if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
460 			mtk_mutex_remove_comp(mtk_crtc->mutex,
461 					      mtk_crtc->ddp_comp[i]->id);
462 	}
463 	if (!mtk_ddp_comp_remove(mtk_crtc->ddp_comp[i], mtk_crtc->mutex))
464 		mtk_mutex_remove_comp(mtk_crtc->mutex, mtk_crtc->ddp_comp[i]->id);
465 	mtk_crtc_ddp_clk_disable(mtk_crtc);
466 	mtk_mutex_unprepare(mtk_crtc->mutex);
467 
468 	pm_runtime_put(drm->dev);
469 
470 	if (crtc->state->event && !crtc->state->active) {
471 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
472 		drm_crtc_send_vblank_event(crtc, crtc->state->event);
473 		crtc->state->event = NULL;
474 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
475 	}
476 }
477 
478 static void mtk_crtc_ddp_config(struct drm_crtc *crtc,
479 				struct cmdq_pkt *cmdq_handle)
480 {
481 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
482 	struct mtk_crtc_state *state = to_mtk_crtc_state(mtk_crtc->base.state);
483 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
484 	unsigned int i;
485 	unsigned int local_layer;
486 
487 	/*
488 	 * TODO: instead of updating the registers here, we should prepare
489 	 * working registers in atomic_commit and let the hardware command
490 	 * queue update module registers on vblank.
491 	 */
492 	if (state->pending_config) {
493 		mtk_ddp_comp_config(comp, state->pending_width,
494 				    state->pending_height,
495 				    state->pending_vrefresh, 0,
496 				    cmdq_handle);
497 
498 		if (!cmdq_handle)
499 			state->pending_config = false;
500 	}
501 
502 	if (mtk_crtc->pending_planes) {
503 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
504 			struct drm_plane *plane = &mtk_crtc->planes[i];
505 			struct mtk_plane_state *plane_state;
506 
507 			plane_state = to_mtk_plane_state(plane->state);
508 
509 			if (!plane_state->pending.config)
510 				continue;
511 
512 			comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
513 
514 			if (comp)
515 				mtk_ddp_comp_layer_config(comp, local_layer,
516 							  plane_state,
517 							  cmdq_handle);
518 			if (!cmdq_handle)
519 				plane_state->pending.config = false;
520 		}
521 
522 		if (!cmdq_handle)
523 			mtk_crtc->pending_planes = false;
524 	}
525 
526 	if (mtk_crtc->pending_async_planes) {
527 		for (i = 0; i < mtk_crtc->layer_nr; i++) {
528 			struct drm_plane *plane = &mtk_crtc->planes[i];
529 			struct mtk_plane_state *plane_state;
530 
531 			plane_state = to_mtk_plane_state(plane->state);
532 
533 			if (!plane_state->pending.async_config)
534 				continue;
535 
536 			comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
537 
538 			if (comp)
539 				mtk_ddp_comp_layer_config(comp, local_layer,
540 							  plane_state,
541 							  cmdq_handle);
542 			if (!cmdq_handle)
543 				plane_state->pending.async_config = false;
544 		}
545 
546 		if (!cmdq_handle)
547 			mtk_crtc->pending_async_planes = false;
548 	}
549 }
550 
551 static void mtk_crtc_update_config(struct mtk_crtc *mtk_crtc, bool needs_vblank)
552 {
553 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
554 	struct cmdq_pkt *cmdq_handle = &mtk_crtc->cmdq_handle;
555 #endif
556 	struct drm_crtc *crtc = &mtk_crtc->base;
557 	struct mtk_drm_private *priv = crtc->dev->dev_private;
558 	unsigned int pending_planes = 0, pending_async_planes = 0;
559 	int i;
560 	unsigned long flags;
561 
562 	mutex_lock(&mtk_crtc->hw_lock);
563 
564 	spin_lock_irqsave(&mtk_crtc->config_lock, flags);
565 	mtk_crtc->config_updating = true;
566 	spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
567 
568 	if (needs_vblank)
569 		mtk_crtc->pending_needs_vblank = true;
570 
571 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
572 		struct drm_plane *plane = &mtk_crtc->planes[i];
573 		struct mtk_plane_state *plane_state;
574 
575 		plane_state = to_mtk_plane_state(plane->state);
576 		if (plane_state->pending.dirty) {
577 			plane_state->pending.config = true;
578 			plane_state->pending.dirty = false;
579 			pending_planes |= BIT(i);
580 		} else if (plane_state->pending.async_dirty) {
581 			plane_state->pending.async_config = true;
582 			plane_state->pending.async_dirty = false;
583 			pending_async_planes |= BIT(i);
584 		}
585 	}
586 	if (pending_planes)
587 		mtk_crtc->pending_planes = true;
588 	if (pending_async_planes)
589 		mtk_crtc->pending_async_planes = true;
590 
591 	if (priv->data->shadow_register) {
592 		mtk_mutex_acquire(mtk_crtc->mutex);
593 		mtk_crtc_ddp_config(crtc, NULL);
594 		mtk_mutex_release(mtk_crtc->mutex);
595 	}
596 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
597 	if (mtk_crtc->cmdq_client.chan) {
598 		mbox_flush(mtk_crtc->cmdq_client.chan, 2000);
599 		cmdq_handle->cmd_buf_size = 0;
600 		cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event);
601 		cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false);
602 		mtk_crtc_ddp_config(crtc, cmdq_handle);
603 		cmdq_pkt_eoc(cmdq_handle);
604 		dma_sync_single_for_device(mtk_crtc->cmdq_client.chan->mbox->dev,
605 					   cmdq_handle->pa_base,
606 					   cmdq_handle->cmd_buf_size,
607 					   DMA_TO_DEVICE);
608 		/*
609 		 * CMDQ command should execute in next 3 vblank.
610 		 * One vblank interrupt before send message (occasionally)
611 		 * and one vblank interrupt after cmdq done,
612 		 * so it's timeout after 3 vblank interrupt.
613 		 * If it fail to execute in next 3 vblank, timeout happen.
614 		 */
615 		mtk_crtc->cmdq_vblank_cnt = 3;
616 
617 		spin_lock_irqsave(&mtk_crtc->config_lock, flags);
618 		mtk_crtc->config_updating = false;
619 		spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
620 
621 		mbox_send_message(mtk_crtc->cmdq_client.chan, cmdq_handle);
622 		mbox_client_txdone(mtk_crtc->cmdq_client.chan, 0);
623 	}
624 #else
625 	spin_lock_irqsave(&mtk_crtc->config_lock, flags);
626 	mtk_crtc->config_updating = false;
627 	spin_unlock_irqrestore(&mtk_crtc->config_lock, flags);
628 #endif
629 
630 	mutex_unlock(&mtk_crtc->hw_lock);
631 }
632 
633 static void mtk_crtc_ddp_irq(void *data)
634 {
635 	struct drm_crtc *crtc = data;
636 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
637 	struct mtk_drm_private *priv = crtc->dev->dev_private;
638 
639 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
640 	if (!priv->data->shadow_register && !mtk_crtc->cmdq_client.chan)
641 		mtk_crtc_ddp_config(crtc, NULL);
642 	else if (mtk_crtc->cmdq_vblank_cnt > 0 && --mtk_crtc->cmdq_vblank_cnt == 0)
643 		DRM_ERROR("mtk_crtc %d CMDQ execute command timeout!\n",
644 			  drm_crtc_index(&mtk_crtc->base));
645 #else
646 	if (!priv->data->shadow_register)
647 		mtk_crtc_ddp_config(crtc, NULL);
648 #endif
649 	mtk_drm_finish_page_flip(mtk_crtc);
650 }
651 
652 static int mtk_crtc_enable_vblank(struct drm_crtc *crtc)
653 {
654 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
655 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
656 
657 	mtk_ddp_comp_enable_vblank(comp);
658 
659 	return 0;
660 }
661 
662 static void mtk_crtc_disable_vblank(struct drm_crtc *crtc)
663 {
664 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
665 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
666 
667 	mtk_ddp_comp_disable_vblank(comp);
668 }
669 
670 static void mtk_crtc_update_output(struct drm_crtc *crtc,
671 				   struct drm_atomic_state *state)
672 {
673 	int crtc_index = drm_crtc_index(crtc);
674 	int i;
675 	struct device *dev;
676 	struct drm_crtc_state *crtc_state = state->crtcs[crtc_index].new_state;
677 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
678 	struct mtk_drm_private *priv;
679 	unsigned int encoder_mask = crtc_state->encoder_mask;
680 
681 	if (!crtc_state->connectors_changed)
682 		return;
683 
684 	if (!mtk_crtc->num_conn_routes)
685 		return;
686 
687 	priv = ((struct mtk_drm_private *)crtc->dev->dev_private)->all_drm_private[crtc_index];
688 	dev = priv->dev;
689 
690 	dev_dbg(dev, "connector change:%d, encoder mask:0x%x for crtc:%d\n",
691 		crtc_state->connectors_changed, encoder_mask, crtc_index);
692 
693 	for (i = 0; i < mtk_crtc->num_conn_routes; i++) {
694 		unsigned int comp_id = mtk_crtc->conn_routes[i].route_ddp;
695 		struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
696 
697 		if (comp->encoder_index >= 0 &&
698 		    (encoder_mask & BIT(comp->encoder_index))) {
699 			mtk_crtc->ddp_comp[mtk_crtc->ddp_comp_nr - 1] = comp;
700 			dev_dbg(dev, "Add comp_id: %d at path index %d\n",
701 				comp->id, mtk_crtc->ddp_comp_nr - 1);
702 			break;
703 		}
704 	}
705 }
706 
707 int mtk_crtc_plane_check(struct drm_crtc *crtc, struct drm_plane *plane,
708 			 struct mtk_plane_state *state)
709 {
710 	unsigned int local_layer;
711 	struct mtk_ddp_comp *comp;
712 
713 	comp = mtk_ddp_comp_for_plane(crtc, plane, &local_layer);
714 	if (comp)
715 		return mtk_ddp_comp_layer_check(comp, local_layer, state);
716 	return 0;
717 }
718 
719 void mtk_crtc_async_update(struct drm_crtc *crtc, struct drm_plane *plane,
720 			   struct drm_atomic_state *state)
721 {
722 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
723 
724 	if (!mtk_crtc->enabled)
725 		return;
726 
727 	mtk_crtc_update_config(mtk_crtc, false);
728 }
729 
730 static void mtk_crtc_atomic_enable(struct drm_crtc *crtc,
731 				   struct drm_atomic_state *state)
732 {
733 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
734 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
735 	int ret;
736 
737 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
738 
739 	ret = mtk_ddp_comp_power_on(comp);
740 	if (ret < 0) {
741 		DRM_DEV_ERROR(comp->dev, "Failed to enable power domain: %d\n", ret);
742 		return;
743 	}
744 
745 	mtk_crtc_update_output(crtc, state);
746 
747 	ret = mtk_crtc_ddp_hw_init(mtk_crtc);
748 	if (ret) {
749 		mtk_ddp_comp_power_off(comp);
750 		return;
751 	}
752 
753 	drm_crtc_vblank_on(crtc);
754 	mtk_crtc->enabled = true;
755 }
756 
757 static void mtk_crtc_atomic_disable(struct drm_crtc *crtc,
758 				    struct drm_atomic_state *state)
759 {
760 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
761 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[0];
762 	int i;
763 
764 	DRM_DEBUG_DRIVER("%s %d\n", __func__, crtc->base.id);
765 	if (!mtk_crtc->enabled)
766 		return;
767 
768 	/* Set all pending plane state to disabled */
769 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
770 		struct drm_plane *plane = &mtk_crtc->planes[i];
771 		struct mtk_plane_state *plane_state;
772 
773 		plane_state = to_mtk_plane_state(plane->state);
774 		plane_state->pending.enable = false;
775 		plane_state->pending.config = true;
776 	}
777 	mtk_crtc->pending_planes = true;
778 
779 	mtk_crtc_update_config(mtk_crtc, false);
780 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
781 	/* Wait for planes to be disabled by cmdq */
782 	if (mtk_crtc->cmdq_client.chan)
783 		wait_event_timeout(mtk_crtc->cb_blocking_queue,
784 				   mtk_crtc->cmdq_vblank_cnt == 0,
785 				   msecs_to_jiffies(500));
786 #endif
787 	/* Wait for planes to be disabled */
788 	drm_crtc_wait_one_vblank(crtc);
789 
790 	drm_crtc_vblank_off(crtc);
791 	mtk_crtc_ddp_hw_fini(mtk_crtc);
792 	mtk_ddp_comp_power_off(comp);
793 
794 	mtk_crtc->enabled = false;
795 }
796 
797 static void mtk_crtc_atomic_begin(struct drm_crtc *crtc,
798 				  struct drm_atomic_state *state)
799 {
800 	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
801 									  crtc);
802 	struct mtk_crtc_state *mtk_crtc_state = to_mtk_crtc_state(crtc_state);
803 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
804 	unsigned long flags;
805 
806 	if (mtk_crtc->event && mtk_crtc_state->base.event)
807 		DRM_ERROR("new event while there is still a pending event\n");
808 
809 	if (mtk_crtc_state->base.event) {
810 		mtk_crtc_state->base.event->pipe = drm_crtc_index(crtc);
811 		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
812 
813 		spin_lock_irqsave(&crtc->dev->event_lock, flags);
814 		mtk_crtc->event = mtk_crtc_state->base.event;
815 		spin_unlock_irqrestore(&crtc->dev->event_lock, flags);
816 
817 		mtk_crtc_state->base.event = NULL;
818 	}
819 }
820 
821 static void mtk_crtc_atomic_flush(struct drm_crtc *crtc,
822 				  struct drm_atomic_state *state)
823 {
824 	struct mtk_crtc *mtk_crtc = to_mtk_crtc(crtc);
825 	int i;
826 
827 	if (crtc->state->color_mgmt_changed)
828 		for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
829 			mtk_ddp_gamma_set(mtk_crtc->ddp_comp[i], crtc->state);
830 			mtk_ddp_ctm_set(mtk_crtc->ddp_comp[i], crtc->state);
831 		}
832 	mtk_crtc_update_config(mtk_crtc, !!mtk_crtc->event);
833 }
834 
835 static const struct drm_crtc_funcs mtk_crtc_funcs = {
836 	.set_config		= drm_atomic_helper_set_config,
837 	.page_flip		= drm_atomic_helper_page_flip,
838 	.destroy		= mtk_crtc_destroy,
839 	.reset			= mtk_crtc_reset,
840 	.atomic_duplicate_state	= mtk_crtc_duplicate_state,
841 	.atomic_destroy_state	= mtk_crtc_destroy_state,
842 	.enable_vblank		= mtk_crtc_enable_vblank,
843 	.disable_vblank		= mtk_crtc_disable_vblank,
844 };
845 
846 static const struct drm_crtc_helper_funcs mtk_crtc_helper_funcs = {
847 	.mode_fixup	= mtk_crtc_mode_fixup,
848 	.mode_set_nofb	= mtk_crtc_mode_set_nofb,
849 	.mode_valid	= mtk_crtc_mode_valid,
850 	.atomic_begin	= mtk_crtc_atomic_begin,
851 	.atomic_flush	= mtk_crtc_atomic_flush,
852 	.atomic_enable	= mtk_crtc_atomic_enable,
853 	.atomic_disable	= mtk_crtc_atomic_disable,
854 };
855 
856 static int mtk_crtc_init(struct drm_device *drm, struct mtk_crtc *mtk_crtc,
857 			 unsigned int pipe)
858 {
859 	struct drm_plane *primary = NULL;
860 	struct drm_plane *cursor = NULL;
861 	int i, ret;
862 
863 	for (i = 0; i < mtk_crtc->layer_nr; i++) {
864 		if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_PRIMARY)
865 			primary = &mtk_crtc->planes[i];
866 		else if (mtk_crtc->planes[i].type == DRM_PLANE_TYPE_CURSOR)
867 			cursor = &mtk_crtc->planes[i];
868 	}
869 
870 	ret = drm_crtc_init_with_planes(drm, &mtk_crtc->base, primary, cursor,
871 					&mtk_crtc_funcs, NULL);
872 	if (ret)
873 		goto err_cleanup_crtc;
874 
875 	drm_crtc_helper_add(&mtk_crtc->base, &mtk_crtc_helper_funcs);
876 
877 	return 0;
878 
879 err_cleanup_crtc:
880 	drm_crtc_cleanup(&mtk_crtc->base);
881 	return ret;
882 }
883 
884 static int mtk_crtc_num_comp_planes(struct mtk_crtc *mtk_crtc, int comp_idx)
885 {
886 	struct mtk_ddp_comp *comp;
887 
888 	if (comp_idx > 1)
889 		return 0;
890 
891 	comp = mtk_crtc->ddp_comp[comp_idx];
892 	if (!comp->funcs)
893 		return 0;
894 
895 	if (comp_idx == 1 && !comp->funcs->bgclr_in_on)
896 		return 0;
897 
898 	return mtk_ddp_comp_layer_nr(comp);
899 }
900 
901 static inline
902 enum drm_plane_type mtk_crtc_plane_type(unsigned int plane_idx,
903 					unsigned int num_planes)
904 {
905 	if (plane_idx == 0)
906 		return DRM_PLANE_TYPE_PRIMARY;
907 	else if (plane_idx == (num_planes - 1))
908 		return DRM_PLANE_TYPE_CURSOR;
909 	else
910 		return DRM_PLANE_TYPE_OVERLAY;
911 
912 }
913 
914 static int mtk_crtc_init_comp_planes(struct drm_device *drm_dev,
915 				     struct mtk_crtc *mtk_crtc,
916 				     int comp_idx, int pipe)
917 {
918 	int num_planes = mtk_crtc_num_comp_planes(mtk_crtc, comp_idx);
919 	struct mtk_ddp_comp *comp = mtk_crtc->ddp_comp[comp_idx];
920 	int i, ret;
921 
922 	for (i = 0; i < num_planes; i++) {
923 		ret = mtk_plane_init(drm_dev,
924 				&mtk_crtc->planes[mtk_crtc->layer_nr],
925 				BIT(pipe),
926 				mtk_crtc_plane_type(mtk_crtc->layer_nr, num_planes),
927 				mtk_ddp_comp_supported_rotations(comp),
928 				mtk_ddp_comp_get_blend_modes(comp),
929 				mtk_ddp_comp_get_formats(comp),
930 				mtk_ddp_comp_get_num_formats(comp), i);
931 		if (ret)
932 			return ret;
933 
934 		mtk_crtc->layer_nr++;
935 	}
936 	return 0;
937 }
938 
939 struct device *mtk_crtc_dma_dev_get(struct drm_crtc *crtc)
940 {
941 	struct mtk_crtc *mtk_crtc = NULL;
942 
943 	if (!crtc)
944 		return NULL;
945 
946 	mtk_crtc = to_mtk_crtc(crtc);
947 	if (!mtk_crtc)
948 		return NULL;
949 
950 	return mtk_crtc->dma_dev;
951 }
952 
953 int mtk_crtc_create(struct drm_device *drm_dev, const unsigned int *path,
954 		    unsigned int path_len, int priv_data_index,
955 		    const struct mtk_drm_route *conn_routes,
956 		    unsigned int num_conn_routes)
957 {
958 	struct mtk_drm_private *priv = drm_dev->dev_private;
959 	struct device *dev = drm_dev->dev;
960 	struct mtk_crtc *mtk_crtc;
961 	unsigned int num_comp_planes = 0;
962 	int ret;
963 	int i;
964 	bool has_ctm = false;
965 	uint gamma_lut_size = 0;
966 	struct drm_crtc *tmp;
967 	int crtc_i = 0;
968 
969 	if (!path)
970 		return 0;
971 
972 	priv = priv->all_drm_private[priv_data_index];
973 
974 	drm_for_each_crtc(tmp, drm_dev)
975 		crtc_i++;
976 
977 	for (i = 0; i < path_len; i++) {
978 		enum mtk_ddp_comp_id comp_id = path[i];
979 		struct device_node *node;
980 		struct mtk_ddp_comp *comp;
981 
982 		node = priv->comp_node[comp_id];
983 		comp = &priv->ddp_comp[comp_id];
984 
985 		/* Not all drm components have a DTS device node, such as ovl_adaptor,
986 		 * which is the drm bring up sub driver
987 		 */
988 		if (!node && comp_id != DDP_COMPONENT_DRM_OVL_ADAPTOR) {
989 			dev_info(dev,
990 				"Not creating crtc %d because component %d is disabled or missing\n",
991 				crtc_i, comp_id);
992 			return 0;
993 		}
994 
995 		if (!comp->dev) {
996 			dev_err(dev, "Component %pOF not initialized\n", node);
997 			return -ENODEV;
998 		}
999 	}
1000 
1001 	mtk_crtc = devm_kzalloc(dev, sizeof(*mtk_crtc), GFP_KERNEL);
1002 	if (!mtk_crtc)
1003 		return -ENOMEM;
1004 
1005 	mtk_crtc->mmsys_dev = priv->mmsys_dev;
1006 	mtk_crtc->ddp_comp_nr = path_len;
1007 	mtk_crtc->ddp_comp = devm_kcalloc(dev,
1008 					  mtk_crtc->ddp_comp_nr + (conn_routes ? 1 : 0),
1009 					  sizeof(*mtk_crtc->ddp_comp),
1010 					  GFP_KERNEL);
1011 	if (!mtk_crtc->ddp_comp)
1012 		return -ENOMEM;
1013 
1014 	mtk_crtc->mutex = mtk_mutex_get(priv->mutex_dev);
1015 	if (IS_ERR(mtk_crtc->mutex)) {
1016 		ret = PTR_ERR(mtk_crtc->mutex);
1017 		dev_err(dev, "Failed to get mutex: %d\n", ret);
1018 		return ret;
1019 	}
1020 
1021 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1022 		unsigned int comp_id = path[i];
1023 		struct mtk_ddp_comp *comp;
1024 
1025 		comp = &priv->ddp_comp[comp_id];
1026 		mtk_crtc->ddp_comp[i] = comp;
1027 
1028 		if (comp->funcs) {
1029 			if (comp->funcs->gamma_set && comp->funcs->gamma_get_lut_size) {
1030 				unsigned int lut_sz = mtk_ddp_gamma_get_lut_size(comp);
1031 
1032 				if (lut_sz)
1033 					gamma_lut_size = lut_sz;
1034 			}
1035 
1036 			if (comp->funcs->ctm_set)
1037 				has_ctm = true;
1038 		}
1039 
1040 		mtk_ddp_comp_register_vblank_cb(comp, mtk_crtc_ddp_irq,
1041 						&mtk_crtc->base);
1042 	}
1043 
1044 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++)
1045 		num_comp_planes += mtk_crtc_num_comp_planes(mtk_crtc, i);
1046 
1047 	mtk_crtc->planes = devm_kcalloc(dev, num_comp_planes,
1048 					sizeof(struct drm_plane), GFP_KERNEL);
1049 	if (!mtk_crtc->planes)
1050 		return -ENOMEM;
1051 
1052 	for (i = 0; i < mtk_crtc->ddp_comp_nr; i++) {
1053 		ret = mtk_crtc_init_comp_planes(drm_dev, mtk_crtc, i, crtc_i);
1054 		if (ret)
1055 			return ret;
1056 	}
1057 
1058 	/*
1059 	 * Default to use the first component as the dma dev.
1060 	 * In the case of ovl_adaptor sub driver, it needs to use the
1061 	 * dma_dev_get function to get representative dma dev.
1062 	 */
1063 	mtk_crtc->dma_dev = mtk_ddp_comp_dma_dev_get(&priv->ddp_comp[path[0]]);
1064 
1065 	ret = mtk_crtc_init(drm_dev, mtk_crtc, crtc_i);
1066 	if (ret < 0)
1067 		return ret;
1068 
1069 	if (gamma_lut_size)
1070 		drm_mode_crtc_set_gamma_size(&mtk_crtc->base, gamma_lut_size);
1071 	drm_crtc_enable_color_mgmt(&mtk_crtc->base, 0, has_ctm, gamma_lut_size);
1072 	mutex_init(&mtk_crtc->hw_lock);
1073 	spin_lock_init(&mtk_crtc->config_lock);
1074 
1075 #if IS_REACHABLE(CONFIG_MTK_CMDQ)
1076 	i = priv->mbox_index++;
1077 	mtk_crtc->cmdq_client.client.dev = mtk_crtc->mmsys_dev;
1078 	mtk_crtc->cmdq_client.client.tx_block = false;
1079 	mtk_crtc->cmdq_client.client.knows_txdone = true;
1080 	mtk_crtc->cmdq_client.client.rx_callback = ddp_cmdq_cb;
1081 	mtk_crtc->cmdq_client.chan =
1082 			mbox_request_channel(&mtk_crtc->cmdq_client.client, i);
1083 	if (IS_ERR(mtk_crtc->cmdq_client.chan)) {
1084 		dev_dbg(dev, "mtk_crtc %d failed to create mailbox client, writing register by CPU now\n",
1085 			drm_crtc_index(&mtk_crtc->base));
1086 		mtk_crtc->cmdq_client.chan = NULL;
1087 	}
1088 
1089 	if (mtk_crtc->cmdq_client.chan) {
1090 		ret = of_property_read_u32_index(priv->mutex_node,
1091 						 "mediatek,gce-events",
1092 						 i,
1093 						 &mtk_crtc->cmdq_event);
1094 		if (ret) {
1095 			dev_dbg(dev, "mtk_crtc %d failed to get mediatek,gce-events property\n",
1096 				drm_crtc_index(&mtk_crtc->base));
1097 			mbox_free_channel(mtk_crtc->cmdq_client.chan);
1098 			mtk_crtc->cmdq_client.chan = NULL;
1099 		} else {
1100 			ret = cmdq_pkt_create(&mtk_crtc->cmdq_client,
1101 					      &mtk_crtc->cmdq_handle,
1102 					      PAGE_SIZE);
1103 			if (ret) {
1104 				dev_dbg(dev, "mtk_crtc %d failed to create cmdq packet\n",
1105 					drm_crtc_index(&mtk_crtc->base));
1106 				mbox_free_channel(mtk_crtc->cmdq_client.chan);
1107 				mtk_crtc->cmdq_client.chan = NULL;
1108 			}
1109 		}
1110 
1111 		/* for sending blocking cmd in crtc disable */
1112 		init_waitqueue_head(&mtk_crtc->cb_blocking_queue);
1113 	}
1114 #endif
1115 
1116 	if (conn_routes) {
1117 		for (i = 0; i < num_conn_routes; i++) {
1118 			unsigned int comp_id = conn_routes[i].route_ddp;
1119 			struct device_node *node = priv->comp_node[comp_id];
1120 			struct mtk_ddp_comp *comp = &priv->ddp_comp[comp_id];
1121 
1122 			if (!comp->dev) {
1123 				dev_dbg(dev, "comp_id:%d, Component %pOF not initialized\n",
1124 					comp_id, node);
1125 				/* mark encoder_index to -1, if route comp device is not enabled */
1126 				comp->encoder_index = -1;
1127 				continue;
1128 			}
1129 
1130 			mtk_ddp_comp_encoder_index_set(&priv->ddp_comp[comp_id]);
1131 		}
1132 
1133 		mtk_crtc->num_conn_routes = num_conn_routes;
1134 		mtk_crtc->conn_routes = conn_routes;
1135 
1136 		/* increase ddp_comp_nr at the end of mtk_crtc_create */
1137 		mtk_crtc->ddp_comp_nr++;
1138 	}
1139 
1140 	return 0;
1141 }
1142